A method for realizing a large dynamic and high linearity analog amplifier

Abstract

The present invention discloses an analog amplifier with large dynamic range and high linearity. The analog amplifier of the present invention comprises a bias circuit, an amplifier differential input stage, and a push-pull output stage in sequence. The bias circuit provides bias current for the amplifier differential input stage and the push-pull output stage; the amplifier differential input stage adopts a complementary folded common source and common gate structure to realize rail-to-rail input, and uses current adaptation to improve the change of transconductance of the amplifier differential input stage under different working states, and improves the linearity of the transconductance of the amplifier differential input stage through cross-coupling technology; and adopts a class AB push-pull structure to realize the amplifier high linearity output stage. The present invention has the characteristics of large input dynamic range and high linearity, and can be used in circuits such as variable gain amplifiers, continuous time filters, and unit gain buffers.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, and in particular to a large dynamic and high linearity analog amplifier. Background Art

[0002] Analog amplifiers are widely used in products such as variable gain amplifiers, continuous time filters, unity gain buffers, analog-to-digital / digital-to-analog converters, etc. Their performance determines the quality of the product. In view of the reduction in power supply voltage caused by the reduction in the size of semiconductor devices, rail-to-rail amplifiers can increase the common-mode input range of operational amplifiers and improve the efficiency of power supply voltage utilization.

[0003] However, the traditional rail-to-rail amplifier uses a PMOS and NMOS complementary differential pair as the input stage, which has a large change in input transconductance amplitude, causing large changes in parameters such as loop gain, resulting in system instability. 【1】 At the same time, the amplifier cannot guarantee good linearity within a wide input voltage range, cannot effectively reduce harmonic distortion, and is difficult to meet the needs of high-performance products. 【2】 .

[0004] References

[0005] 【1】Tang Junlong. A constant transconductance high gain rail-to-rail operational amplifier [J]. Microelectronics, 2018, 48(4), 458-462.

[0006] 【2】Li Xiaochao. Design of full swing constant transconductance amplifier in 0.18um CMOS process

J

[0007] The present invention aims to solve the problems existing in the above-mentioned traditional rail-to-rail amplifier and proposes an analog amplifier with large dynamic range and high linearity.

[0008] The technical solution adopted by the present invention to solve the above technical problems is: an analog amplifier with large dynamic range and high linearity, characterized in that it includes a bias circuit, an amplifier differential input stage, and a push-pull output stage; the bias circuit is composed of a low-voltage Cascode structure current mirror tube, which provides a bias voltage for the amplifier differential input stage and the push-pull output stage; the amplifier differential input tube adopts a complementary folded common source and common gate structure to achieve rail-to-rail input, and uses current adaptation to improve the change of the transconductance of the amplifier differential input stage under different working states, so that the input stage transconductance remains constant, and the nonlinearity of the transconductance of the amplifier differential input stage is improved by cross-coupling technology; the push-pull output stage adopts an AB class push-pull structure with a common drain configuration to achieve high efficiency and high linearity output.

[0009] Specifically, the bias circuit includes resistors R1, R2, R3, NMOS tubes MN21, MN22, MN23, MN24, MN23, MN24, MN25, MN26, and PMOS tubes MP20, MP21, P22, MP23;

[0010] The amplifier differential input stage includes PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, tubes MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, resistor R4, NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN13, MN14, MN15, MN16, MN17, resistor R5;

[0011] The push-pull output stage includes PMOS tubes MP17, MP18, MP19, NMOS tubes MN18, MN19, MN20; wherein the upper end of the resistor R1 is connected to the gate of the NMOS tube MN22 and the gate of MN24 as a bias current input terminal, the lower end of the resistor R1 is connected to the drain of MN22, the source of MN22 is connected to the drain of MN21, the source of MN21 is connected to the ground, the source of MN23 is connected to the ground, the drain is connected to the source of MN24, the drain of NM24 is connected to the lower end of the resistor R2, the gate of MNP20 and the gate of MP23, the upper end of the resistor R2 is connected to the drain of MP20 and the gates of MP21 and MP22, the source of MP20 is connected to the drain of MP21, the sources of MP21 and MP22 are both connected to the power supply, and MP23 is connected to the ground. The source of MP22 is connected to the drain of MP23, the drain of MP23 is connected to the upper end of resistor R3 and the gate of MN25, the drain of MN25 is connected to the lower end of resistor R3 and the gate of MN26, the source of MN26 is connected to the drain of MN26, the source of MN26 is connected to the ground, the sources of MP5, MP6, MP7, MP10, MP11, and MP12 are all connected to the power supply, the gates of MP6 and MP7 are all connected to the gate of MP21, the drain of MP6 is connected to the source of MP3, the source of MP4, the source of MP8 and the drain of MP10, the drain of MP7 is connected to the source of MP1, the source of MP2, the source of MP9 and the drain of MP11, the gate of MP8 is connected to the gate of MP9, the drain is connected to the drain and gate of MN6, the drain of MP9 is connected to the drain and gate of MN8,The gate of MP12 is connected to its own drain and the gate of MP11 with the drain of MN11, the gate of MP5 is connected to its own drain and the gate of MP10 with the drain of MN13, the gate of MP1, the gate of MP4, the gate of MN1 and the gate of MN3 are all connected to the differential input negative terminal VIN, the gate of MP2, the gate of MP3, the gate of MN2 and the gate of MN4 are all connected to the differential input positive terminal VIP, the drain of MP1 is connected to the drain of MP3 and the drain of MP13 and the source of MP15, the drain of MP2 is connected to the drain of MP4 and the drain of MP The drain of MN11 is connected to the source of MP16, the source of MN1 is connected to MN4, the source of MN16 is connected to the drain of MN14, the source of MN2 is connected to MN3, the source of MN17 is connected to the drain of MN15, the source of MN5, the source of MN6, the source of MN7, the source of MN8, the source of MN9, and the source of MN10 are all connected to ground, the drain of MN5 and the drain of MN10, the source of MN3 and the source of NM4 are connected to the source of MN11, the drain of MN7 and the drain of MN9, the source of MN1 and the source of NM2 are connected to the source of MN13, and the drain of MN 9 is connected to the gate of MN10, the gates of MN13 and NM11 are connected, the source of MP13 and the source of MP14 are connected to the power supply, the gate of MP13, the gate of MP14, and the drain of MP15 are connected to the upper end of the resistor R4, the gates of MP15 and MP16 are connected to the gate of MP20, the lower end of the resistor R4 is connected to the upper end of the resistor R5, the source of MN15 and the source of NMOSMN14 are connected to the ground, the gate of MN15, the gate of MN14, and the drain of MN17 are connected to the lower end of the resistor R5, and MN17 and MN16 are connected to the lower end of the resistor R5. Connected to MN26, MP16 drain, MN16 drain, MP17 gate, MN19 gate are connected, MN17 source is connected to MP18 drain and MN20 gate, MN17 drain is grounded, MP18 gate is connected to MP21, MP18 source and MN20 drain are both connected to the power supply, MN18 gate is connected to MN25 gate, MN18 source and MP19 drain are connected to ground, MN18 drain is connected to MN19 source and MP19 gate, MP19 drain is connected to MN20 source. The size ratio of MP6 and MP7 is 8:1, and the size ratio of MN9 and MN10 is 8:1. The size ratio of MN6 and MN5 is 1:3, the size ratio of MN8 and MN7 is 1:3, the size ratio of MP5 and MP10 is 1:3, and the size ratio of MP12 and MP11 is 1:3. The size ratio of MP4 to MP1 is 2:1, the size ratio of MP3 to MP2 is 2:1, the size ratio of MP8 to MP4 is 2:1, the size ratio of MP9 to MP1 is 2:1, the size ratio of MN3 to MN1 is 2:1, the size ratio of MN4 to MN2 is 2:1, the size ratio of MN11 to MN3 is 2:1, and the size ratio of MN13 to MN1 is 2:1. ,

[0012] The present invention has the advantages of large input dynamic range and high linearity. Compared with the traditional rail-to-rail operational amplifier and the conventional constant transconductance design scheme, the present invention not only ensures that the input stage transconductance is a constant value, but also improves the linearity of the input stage transconductance, and can meet the system requirements of circuit modules such as variable gain amplifiers, continuous time filters, and unit gain buffers. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the input stage structure of a conventional rail-to-rail operational amplifier according to the background technology of the present invention.

[0014] Figure 2 Schematic diagram of the amplifier differential input stage structure based on current adaptation and cross-coupling.

[0015] Figure 3 Schematic diagram of the overall circuit structure of the large dynamic and high linearity analog operational amplifier of the present invention. DETAILED DESCRIPTION

[0016] The present invention is described in detail below in conjunction with the accompanying drawings. The large dynamic range, high linearity analog amplifier of the present invention includes a bias circuit, an amplifier differential input stage, and a push-pull output stage. Compared with the traditional rail-to-rail amplifier input stage ( Figure 1 ) compared to the amplifier differential input stage ( Figure 2 ) The complementary differential pair is used to ensure large dynamics, and the current adaptive technology is used to reduce the change of input transconductance amplitude in different working states, and the linearity of input transconductance is further improved by combining cross-coupling technology. The push-pull output stage adopts a class AB push-pull structure with a common drain configuration to achieve higher output efficiency and linearity. The bias circuit is composed of a low-voltage Cascode structure current mirror, which has the characteristics of high output impedance and small current error.

[0017] Figure 3 The overall circuit structure of the large dynamic and high linearity analog amplifier in the present invention, specifically, the bias circuit includes resistors R1, R2, R3, NMOS tubes MN21, MN22, MN23, MN24, MN23, MN24, MN25, MN26, and PMOS tubes MP20, MP21, P22, MP23;

[0018] The amplifier differential input stage includes PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, tubes MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, resistor R4, NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN13, MN14, MN15, MN16, MN17, resistor R5;

[0019] The push-pull output stage includes PMOS tubes MP17, MP18, MP19, NMOS tubes MN18, MN19, MN20; wherein the upper end of the resistor R1 is connected to the gate of the NMOS tube MN22 and the gate of MN24 as a bias current input terminal, the lower end of the resistor R1 is connected to the drain of MN22, the source of MN22 is connected to the drain of MN21, the source of MN21 is connected to the ground, the source of MN23 is connected to the ground, the drain is connected to the source of MN24, the drain of NM24 is connected to the lower end of the resistor R2, the gate of MNP20 and the gate of MP23, the upper end of the resistor R2 is connected to the drain of MP20 and the gates of MP21 and MP22, the source of MP20 is connected to the drain of MP21, the sources of MP21 and MP22 are both connected to the power supply, and MP23 is connected to the ground. The source of MP22 is connected to the drain of MP23, the drain of MP23 is connected to the upper end of resistor R3 and the gate of MN25, the drain of MN25 is connected to the lower end of resistor R3 and the gate of MN26, the source of MN26 is connected to the drain of MN26, the source of MN26 is connected to the ground, the sources of MP5, MP6, MP7, MP10, MP11, and MP12 are all connected to the power supply, the gates of MP6 and MP7 are all connected to the gate of MP21, the drain of MP6 is connected to the source of MP3, the source of MP4, the source of MP8 and the drain of MP10, the drain of MP7 is connected to the source of MP1, the source of MP2, the source of MP9 and the drain of MP11, the gate of MP8 is connected to the gate of MP9, the drain is connected to the drain and gate of MN6, the drain of MP9 is connected to the drain and gate of MN8,The gate of MP12 is connected to its own drain and the gate of MP11 with the drain of MN11, the gate of MP5 is connected to its own drain and the gate of MP10 with the drain of MN13, the gate of MP1, the gate of MP4, the gate of MN1 and the gate of MN3 are all connected to the differential input negative terminal VIN, the gate of MP2, the gate of MP3, the gate of MN2 and the gate of MN4 are all connected to the differential input positive terminal VIP, the drain of MP1 is connected to the drain of MP3 and the drain of MP13 and the source of MP15, the drain of MP2 is connected to the drain of MP4 and the drain of MP The drain of MN11 is connected to the source of MP16, the source of MN1 is connected to MN4, the source of MN16 is connected to the drain of MN14, the source of MN2 is connected to MN3, the source of MN17 is connected to the drain of MN15, the source of MN5, the source of MN6, the source of MN7, the source of MN8, the source of MN9, and the source of MN10 are all connected to ground, the drain of MN5 and the drain of MN10, the source of MN3 and the source of NM4 are connected to the source of MN11, the drain of MN7 and the drain of MN9, the source of MN1 and the source of NM2 are connected to the source of MN13, and the drain of MN 9 is connected to the gate of MN10, the gates of MN13 and NM11 are connected, the source of MP13 and the source of MP14 are connected to the power supply, the gate of MP13, the gate of MP14, and the drain of MP15 are connected to the upper end of the resistor R4, the gates of MP15 and MP16 are connected to the gate of MP20, the lower end of the resistor R4 is connected to the upper end of the resistor R5, the source of MN15 and the source of NMOSMN14 are connected to the ground, the gate of MN15, the gate of MN14, and the drain of MN17 are connected to the lower end of the resistor R5, and MN17 and MN16 are connected to the lower end of the resistor R5. Connected to MN26, MP16 drain, MN16 drain, MP17 gate, MN19 gate are connected, MN17 source is connected to MP18 drain and MN20 gate, MN17 drain is grounded, MP18 gate is connected to MP21, MP18 source and MN20 drain are both connected to the power supply, MN18 gate is connected to MN25 gate, MN18 source and MP19 drain are connected to ground, MN18 drain is connected to MN19 source and MP19 gate, MP19 drain is connected to MN20 source. The size ratio of MP6 and MP7 is 8:1, and the size ratio of MN9 and MN10 is 8:1. The size ratio of MN6 and MN5 is 1:3, the size ratio of MN8 and MN7 is 1:3, the size ratio of MP5 and MP10 is 1:3, and the size ratio of MP12 and MP11 is 1:3. The size ratio of MP4 to MP1 is 2:1, the size ratio of MP3 to MP2 is 2:1, the size ratio of MP8 to MP4 is 2:1, the size ratio of MP9 to MP1 is 2:1, the size ratio of MN3 to MN1 is 2:1, the size ratio of MN4 to MN2 is 2:1, the size ratio of MN11 to MN3 is 2:1, and the size ratio of MN13 to MN1 is 2:1. ,

[0020] Working principle of the present invention:

[0021] Each transistor in the bias circuit works in the saturation region, and the Cascode structure is used to increase the output impedance, reduce the transistor channel modulation effect, reduce the current output error, and provide bias current for the analog operational amplifier.

[0022] The amplifier differential input stage consists of an NMOS differential input pair consisting of MN1, MN2, MN3, and MN4, which can achieve (V dsat9,10 +V thMN1 ~4)~V DD The common-mode input range of MP1, MP2, MP3, and MP4 is a PMOS differential input pair that can achieve V SS ~(V DD -V dsat6,7 -V thMP1 ~4), the two differential input pairs can be combined to achieve V SS ~V DD The common-mode input range can achieve large dynamic performance. In addition, when the common-mode input level is relatively low, the NMOS differential input pair composed of MN1, MN2, MN3, and MN4 is in the cut-off state, and the tail current provided by transistors MN9 and MN10 flows through MN13 and MN11 respectively. After the 1:3 mirror relationship, MP11 and MP10 provide 3 times the current to the PMOS differential input pair composed of MP1, MP2, MP3, and MP4 respectively, and MP6 and MP7 provide 1 times the current respectively. At this time, the amplifier differential input pair works at 4 times the current; similarly, when the common-mode input voltage is relatively high, the PMOS differential input pair composed of MP1, MP2, MP3, and MP4 is in the cut-off state, and the NMOS differential input pair composed of MN1, MN2, MN3, and MN4 works at 4 times the current. In the design, the width-to-length ratio of the PMOS differential pair and the NMOS differential pair is set to ensure that the input transconductance values ​​are equal in the two states, that is,

[0023] g mn =g mp =g m

[0024] When the input common-mode level is in the middle state, MN11, MN13, MP8, and MP9 are cut off, and the NMOS input differential pair and the PMOS input differential pair work at 1 times the current respectively. In this state, the transconductance of the amplifier differential input pair is:

[0025]

[0026] The current adaptive technology ensures that the transconductance value of the amplifier is constant within the common-mode input voltage range, reducing the change of the transconductance value.

[0027] In addition, the width-to-length ratio of MN1 and MN2 is set to be the same, the width-to-length ratio of MN3 and MN4 is the same, the width-to-length ratio of MN1 and MN3 is 1:2, the current ratio of MN9 and MN10 is 1:8, the width-to-length ratio of MP1 and MNP is the same, the width-to-length ratio of MP3 and MP4 is the same, the width-to-length ratio of MP1 and MP3 is 1:2, and the current ratio of MP6 and MP7 is 1:8, thereby utilizing cross-coupling technology to eliminate the third-order coefficient in the input transconductance and improving the linearity performance of the analog amplifier.

[0028] The push-pull output stage works in class AB mode. MN20 and MP19 form a complementary output stage. MP17 and MN19 enable the two output transistors to directly maintain the voltage difference, eliminating the influence of crossover distortion and improving the output linearity of the analog amplifier.

Claims

1. A high dynamic range, high linearity analog amplifier, characterized in that: It includes a bias circuit, an amplifier differential input stage, and a push-pull output stage; the bias circuit is composed of a current mirror tube, which provides a bias voltage for the amplifier differential input stage and the push-pull output stage; the amplifier differential input stage adopts a complementary folded common source and common gate structure to achieve rail-to-rail input, and uses current adaptation to improve the change of transconductance of the amplifier differential input stage under different working conditions, and uses cross-coupling technology to improve the nonlinearity of transconductance of the amplifier differential input stage; the push-pull output stage adopts a class AB push-pull structure with a common drain configuration to achieve high linearity output; The bias circuit includes resistors R1, R2, R3, NMOS tubes MN21, MN22, MN23, MN24, MN25, MN26, and PMOS tubes MP20, MP21, MP22, MP23; The amplifier differential input stage includes PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, a resistor R4, NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN13, MN14, MN15, MN16, MN17, and a resistor R5; The push-pull output stage includes PMOS tubes MP17, MP18, MP19, and NMOS tubes MN18, MN19, MN20; The upper end of the resistor R1 in the bias circuit is connected to the gate of the NMOS tube MN22 and the gate of MN24 as a bias current input terminal, the lower end of the resistor R1 is connected to the drain of MN22, the gate of MN21, and the gate of MN23, the source of MN22 is connected to the drain of MN21, the source of MN21 is connected to the ground, the source of MN23 is connected to the ground, and the drain is connected to the source of MN24, the drain of NM24 is connected to the lower end of the resistor R2 and the gate of MNP20 and the gate of MP23. The upper end of the resistor R2 is connected to the drain of MP20 and the gates of MP21 and MP22, the source of MP20 is connected to the drain of MP21, the sources of MP21 and MP22 are both connected to the power supply, the source of MP23 is connected to the drain of MP22, the drain of MP23 is connected to the upper end of the resistor R3 and the gate of MN25, the drain of MN25 is connected to the lower end of the resistor R3 and the gate of MN26, the source is connected to the drain of MN26, and the source of MN26 is connected to the ground; The sources of the amplifier differential input stage MP5, MP6, MP7, MP10, MP11, and MP12 are all connected to the power supply, the gates of MP6 and MP7 are all connected to the gate of MP21, the drain of MP6 is connected to the source of MP3, the source of MP4, the source of MP8, and the drain of MP10, the drain of MP7 is connected to the source of MP1, the source of MP2, the source of MP9, and the drain of MP11, the gate of MP8 is connected to the gate of MP9, the drain is connected to the drain and gate of MN6, the drain of MP9 is connected to the drain and gate of MN8, the gate of MP12 is connected to its own drain and the gate of MP11 and the drain of MN13, the gate of MP5 is connected to Its own drain and MP10 gate are connected to the drain of MN11, MP1 gate, MP4 gate, MN1 gate, and MN3 gate are all connected to the differential input negative terminal VIN, MP2 gate, MP3 gate, MN2 gate, and MN4 gate are all connected to the differential input positive terminal VIP, MP1 drain, MP3 drain, MP14 drain, and MP16 source are connected, MP2 drain, MP4 drain, MP13 drain, and MP15 source are connected, MN1 drain, MN4 drain, MN16 source, and MN14 drain are connected, MN2 drain, MN3 drain, MN17 source, and MN15 drain are connected, MN5 source, MN6 source, and MN7 source are connected. , MN8 source, MN9 source, MN10 source are all connected to ground, MN5 drain and MN10 drain, MN3 source and NM4 source are connected to MN11 source, MN7 drain and MN9 drain, MN1 source and NM2 source are connected to MN13 source, MN9 is connected to MN10 gate, MN13 is connected to NM11 gate, MP13 source and MP14 source are all connected to power supply, MP13 gate, MP14 gate, MP15 drain are all connected to the upper end of resistor R4, MP15 and MP16 gate are all connected to MP20 gate, resistor R4 lower end is connected to resistor R5 upper end, MN15 source and MN14 source are all connected to ground, the gate of MN15, the gate of MN14 and the drain of MN17 are all connected to the lower end of the resistor R5, the gate of MN17 and the gate of MN16 are all connected to the gate of MN26, the drain of MP16, the drain of MN16, the gate of MP17 and the gate of MN19 are connected, the source of MN17 is connected to the drain of MP18 and the gate of MN20, the drain of MN17 is grounded, the gate of MP18 is connected to MP21, the source of MP18 and the drain of MN20 are both connected to the power supply, the gate of MN18 is connected to the gate of MN26, the source of MN18 and the drain of MP19 are connected to ground, the drain of MN18 is connected to the source of MN19 and the gate of MP19, and the source of MP19 is connected to the source of MN20.

2. The high dynamic range, high linearity analog amplifier according to claim 1, characterized in that: The size ratio of MP6 and MP7 is 8:1, and the size ratio of MN9 and MN10 is 8:

1.

3. The high dynamic range, high linearity analog amplifier according to claim 1, characterized in that: The size ratio of MN6 to MN5 is 1:3, the size ratio of MN8 to MN7 is 1:3, the size ratio of MP5 to MP10 is 1:3, and the size ratio of MP12 to MP11 is 1:

3.

4. The high dynamic range, high linearity analog amplifier according to claim 1, characterized in that: The size ratio of MP4 and MP1 is 2:1, the size ratio of MP3 and MP2 is 2:1, the size ratio of MP8 and MP4 is 2:1, the size ratio of MP9 and MP1 is 2:1, the size ratio of MN3 and MN1 is 2:1, the size ratio of MN4 and MN2 is 2:1, the size ratio of MN11 and MN3 is 2:1, and the size ratio of MN13 and MN1 is 2:1.

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