An I2C controller detection method, device, switch and storage medium

Abstract

The application provides an I2C controller detection method and device, a switch and a storage medium. The method comprises the following steps: monitoring an operation index of an I2C controller based on a test equipment, and obtaining an operation index monitoring result of the I2C controller; in a state conversion process of the test equipment, determining a signal quality detection result of the I2C controller according to a read-write state change between the I2C controller and the test equipment; determining an abnormal processing measure detection result of the I2C controller according to an abnormal processing measure taken by the I2C controller when the test equipment is in an abnormal state; and determining a performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormal processing measure detection result. The automatic test of all performances of the I2C controller is realized by using the test equipment, and the detection efficiency of the I2C controller is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an I2C controller detection method, device, switch, and storage medium. Background Technology

[0002] Currently, a large number of I2C controllers are used in the management plane of switch products. The number of I2C controllers that come with the CPU is generally insufficient, so it is necessary to develop our own I2C controllers. The testing of self-developed I2C controllers has naturally become a problem that needs to be solved.

[0003] In existing technologies, I2C controller performance testing is typically performed by testers using an oscilloscope. However, this manual testing process is cumbersome and reduces the efficiency of I2C controller testing. Summary of the Invention

[0004] This application provides an I2C controller detection method, device, switch, and storage medium to address the shortcomings of existing technologies, such as reduced detection efficiency of I2C controllers.

[0005] The first aspect of this application provides an I2C controller detection method applied to a switch, the switch including an I2C controller and a test device, the test device being used as an I2C receiver, the method comprising:

[0006] During the operation of the I2C controller, the monitoring results of the I2C controller's operating indicators are obtained based on the monitoring of the accompanying testing device.

[0007] The accompanying testing device is configured to switch from an abnormal I2C signal state to a normal I2C signal state. During the state transition of the accompanying testing device, the signal quality detection result of the I2C controller is determined based on the changes in the read and write states between the I2C controller and the accompanying testing device.

[0008] The companion device is configured to be in a functional abnormal state. Based on the abnormal handling measures taken by the I2C controller when the companion device is in a functional abnormal state, the detection result of the abnormal handling measures of the I2C controller is determined.

[0009] Based on the monitoring results of the operating indicators, signal quality detection results, and anomaly handling measures of the I2C controller, the performance test results of the I2C controller are determined.

[0010] Optionally, the configuration of the companion device to switch from an abnormal I2C signal state to a normal I2C signal state, during the state transition process of the companion device, determines the signal quality detection result of the I2C controller based on the read / write state changes between the I2C controller and the companion device, including:

[0011] Configure the accompanying testing device to an I2C signal abnormal state;

[0012] The I2C controller is controlled to send read / write commands to the test device in an abnormal I2C signal state.

[0013] If the I2C controller and the test device have not entered the read / write state, the test device will be restored to the normal I2C signal state, and the I2C controller will be controlled to send read / write commands to the test device.

[0014] Determine whether the I2C controller and the accompanying device have entered the read / write state normally, and obtain the signal quality detection result of the I2C controller.

[0015] Optionally, the abnormal functional state includes a busy state, and determining the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the test device is in a abnormal functional state includes:

[0016] Configure the accompanying testing device to a busy state;

[0017] The I2C controller is controlled to send read and write commands to the test device in a busy state; wherein, after receiving the read and write command, the test device in a busy state sends a wait request to the I2C controller;

[0018] If the I2C controller enters a waiting state after receiving a waiting request, then the detection result of the abnormal handling measures of the I2C controller is determined to be normal.

[0019] If the I2C controller does not enter a waiting state after receiving a waiting request, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

[0020] Optionally, the abnormal functional state includes a low I2C SDA signal state. The step of determining the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the device under test is in a abnormal functional state includes:

[0021] Configure the accompanying testing device to a low I2C SDA signal state;

[0022] The I2C controller is controlled to send read and write commands to the companion device in the I2C SDA signal low state; wherein, the I2C controller determines whether the companion device is in the I2CSDA signal low state based on the companion device's response to the read and write commands;

[0023] If the I2C controller determines that the device under test is in a low I2C SDA signal state, and sends a target repair command to the device under test, then the abnormal handling measures detection result of the I2C controller is determined to be normal.

[0024] If the I2C controller determines that the device under test is in a low I2C SDA signal state and does not send a target repair command to the device under test, then the abnormal handling measure detection result of the I2C controller is determined to be abnormal.

[0025] Optionally, the abnormal functional state includes a single command response abnormal state, and determining the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the test device is in a abnormal functional state includes:

[0026] Configure the accompanying testing device to a single command response abnormal state;

[0027] The I2C controller is controlled to send read / write commands to the companion device in an abnormal single command response state.

[0028] If the I2C controller resends the read / write command to the test device when the test device does not respond, then the abnormal handling measures detection result of the I2C controller is determined to be normal.

[0029] If the I2C controller does not resend the read / write command to the test device, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

[0030] Optionally, determining the performance test results of the I2C controller based on the monitoring results of the I2C controller's operating indicators, signal quality detection results, and anomaly handling measures detection results includes:

[0031] Based on the monitoring results of the I2C controller's operating indicators, signal quality detection results, and anomaly handling measures detection results, a performance test report for the I2C controller is generated; the performance test report includes the performance test results of the I2C controller.

[0032] Optionally, the operational metrics may include at least CLK frequency, communication throughput, Tbuf time, and communication data accuracy.

[0033] A second aspect of this application provides an I2C controller testing device applied to a switch, the switch including an I2C controller and a testing device, the testing device being used as an I2C receiver, the device comprising:

[0034] The monitoring module is used to monitor the operating indicators of the I2C controller based on the accompanying testing device during the operation of the I2C controller, and obtain the monitoring results of the operating indicators of the I2C controller.

[0035] The first determining module is used to configure the companion device to switch from an abnormal I2C signal state to a normal I2C signal state. During the state transition of the companion device, the signal quality detection result of the I2C controller is determined based on the read / write state changes between the I2C controller and the companion device.

[0036] The second determining module is used to configure the companion device to a functional abnormal state, and determine the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the companion device is in a functional abnormal state.

[0037] The detection module is used to determine the performance test results of the I2C controller based on the monitoring results of the I2C controller's operating indicators, signal quality detection results, and anomaly handling measures detection results.

[0038] Optionally, the first determining module is specifically used for:

[0039] Configure the accompanying testing device to an I2C signal abnormal state;

[0040] The I2C controller is controlled to send read / write commands to the test device in an abnormal I2C signal state.

[0041] If the I2C controller and the test device have not entered the read / write state, the test device will be restored to the normal I2C signal state, and the I2C controller will be controlled to send read / write commands to the test device.

[0042] Determine whether the I2C controller and the accompanying device have entered the read / write state normally, and obtain the signal quality detection result of the I2C controller.

[0043] Optionally, the abnormal functional state includes a busy state, and the second determining module is specifically used for:

[0044] Configure the accompanying testing device to a busy state;

[0045] The I2C controller is controlled to send read and write commands to the test device in a busy state; wherein, after receiving the read and write command, the test device in a busy state sends a wait request to the I2C controller;

[0046] If the I2C controller enters a waiting state after receiving a waiting request, then the detection result of the abnormal handling measures of the I2C controller is determined to be normal.

[0047] If the I2C controller does not enter a waiting state after receiving a waiting request, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

[0048] Optionally, the abnormal functional state includes a low I2C SDA signal state, and the second determining module is specifically used for:

[0049] Configure the accompanying testing device to a low I2C SDA signal state;

[0050] The I2C controller is controlled to send read and write commands to the companion device in the I2C SDA signal low state; wherein, the I2C controller determines whether the companion device is in the I2CSDA signal low state based on the companion device's response to the read and write commands;

[0051] If the I2C controller determines that the device under test is in a low I2C SDA signal state, and sends a target repair command to the device under test, then the abnormal handling measures detection result of the I2C controller is determined to be normal.

[0052] If the I2C controller determines that the device under test is in a low I2C SDA signal state and does not send a target repair command to the device under test, then the abnormal handling measure detection result of the I2C controller is determined to be abnormal.

[0053] Optionally, the functional abnormal state includes a single command response abnormal state, and the second determining module is specifically used for:

[0054] Configure the accompanying testing device to a single command response abnormal state;

[0055] The I2C controller is controlled to send read / write commands to the companion device in an abnormal single command response state.

[0056] If the I2C controller resends the read / write command to the test device when the test device does not respond, then the abnormal handling measures detection result of the I2C controller is determined to be normal.

[0057] If the I2C controller does not resend the read / write command to the test device, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

[0058] Optionally, the detection module is specifically used for:

[0059] Based on the monitoring results of the I2C controller's operating indicators, signal quality detection results, and anomaly handling measures detection results, a performance test report for the I2C controller is generated; the performance test report includes the performance test results of the I2C controller.

[0060] Optionally, the operational metrics may include at least CLK frequency, communication throughput, Tbuf time, and communication data accuracy.

[0061] A third aspect of this application provides a switch, comprising: an I2C controller, a test device, at least one processor, and a memory;

[0062] The accompanying testing device is used as an I2C receiver;

[0063] The memory stores computer-executed instructions;

[0064] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method described in the first aspect above and various possible designs of the first aspect.

[0065] The fourth aspect of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the method described in the first aspect above and various possible designs of the first aspect.

[0066] The technical solution of this application has the following advantages:

[0067] This application provides an I2C controller testing method, apparatus, switch, and storage medium. The method includes: during the operation of the I2C controller, monitoring the operating indicators of the I2C controller based on a test device to obtain the monitoring results of the I2C controller's operating indicators; configuring the test device to switch from an abnormal I2C signal state to a normal I2C signal state; during the state transition of the test device, determining the signal quality detection result of the I2C controller based on the changes in the read / write state between the I2C controller and the test device; configuring the test device to a functionally abnormal state; determining the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the test device is in a functionally abnormal state; and determining the performance detection result of the I2C controller based on the I2C controller's operating indicator monitoring results, signal quality detection results, and abnormal handling measures detection results. The method provided above achieves automated testing of all performance aspects of the I2C controller by utilizing a test device, thereby improving the testing efficiency of the I2C controller. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0069] Figure 1 This is a schematic diagram of the structure of the I2C controller detection system on which the embodiments of this application are based;

[0070] Figure 2 A flowchart illustrating the I2C controller detection method provided in this application embodiment;

[0071] Figure 3 A schematic diagram of the structure of an exemplary I2C controller detection system provided in an embodiment of this application;

[0072] Figure 4 A flowchart illustrating an exemplary I2C controller detection method provided in this application embodiment;

[0073] Figure 5 A flowchart illustrating another exemplary I2C controller detection method provided in this application embodiment;

[0074] Figure 6 A schematic flowchart illustrating another exemplary I2C controller detection method provided in this application embodiment;

[0075] Figure 7 This is a schematic diagram of the structure of the I2C controller detection device provided in the embodiments of this application;

[0076] Figure 8 This is a schematic diagram of the structure of the switch provided in the embodiments of this application;

[0077] Figure 9 This is a schematic diagram of the structure of an exemplary switch provided in an embodiment of this application.

[0078] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0080] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the following descriptions of embodiments, "a plurality of" means two or more, unless otherwise explicitly defined.

[0081] In existing technologies, I2C controller performance testing is typically performed by testers using an oscilloscope. However, this manual testing process is cumbersome and reduces the efficiency of I2C controller testing.

[0082] To address the aforementioned issues, this application provides an I2C controller testing method, apparatus, switch, and storage medium. The method includes: during I2C controller operation, monitoring the I2C controller's operational indicators using a test device to obtain the I2C controller's operational indicator monitoring results; configuring the test device to transition from an abnormal I2C signal state to a normal I2C signal state; during the state transition process of the test device, determining the I2C controller's signal quality detection results based on the changes in the read / write states between the I2C controller and the test device; configuring the test device to a functionally abnormal state; determining the I2C controller's abnormal handling measure detection results based on the abnormal handling measures taken by the I2C controller when the test device is in a functionally abnormal state; and determining the I2C controller's performance detection results based on the I2C controller's operational indicator monitoring results, signal quality detection results, and abnormal handling measure detection results. The method provided above, by utilizing a test device, achieves automated testing of all I2C controller performance, improving the I2C controller testing efficiency.

[0083] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0084] First, the structure of the I2C controller detection system on which this application is based will be described:

[0085] The I2C controller detection method, apparatus, switch, and storage medium provided in this application are applicable to the automated detection of self-developed I2C controllers in switches. Figure 1 The diagram shown is a structural schematic of the I2C controller detection system based on the embodiments of this application. It mainly includes an I2C controller, a test device, and an I2C controller detection device. Specifically, the I2C controller and the test device can be controlled based on the I2C controller detection device, so as to use the test device to perform automated detection of the I2C controller.

[0086] This application provides an I2C controller testing method applied to a switch. The switch includes an I2C controller and a testing device, which acts as an I2C receiver. This method is used to automatically test a self-developed I2C controller in the switch. The execution subject of this application embodiment is an electronic device, such as a switch, server, desktop computer, laptop computer, tablet computer, or other electronic devices that can be used for I2C controller testing.

[0087] like Figure 2 The diagram shown is a flowchart illustrating the I2C controller detection method provided in an embodiment of this application. The method includes:

[0088] Step 201: During the operation of the I2C controller, the operating indicators of the I2C controller are monitored based on the monitoring equipment to obtain the monitoring results of the operating indicators of the I2C controller.

[0089] The operational metrics include at least CLK frequency, communication throughput, Tbuf time, and communication data accuracy.

[0090] like Figure 3 The diagram shown is a schematic representation of an exemplary I2C controller detection system provided in this application embodiment. The I2C controller and the test device are connected via an I2C bus. The I2C bus includes SCL and SDA, where SCL is used to transmit the clock and SDA is used to transmit data. The I2C controller includes multiple I2C initiators (such as I2C Master1 and I2C Master2), and the test device includes multiple I2C receivers (such as I2C Slave1 and I2C Slave2). A command channel is also provided between the I2C controller and the test device.

[0091] Specifically, such as Figure 4 The diagram illustrates an exemplary I2C controller testing method provided in this application, primarily demonstrating the process of determining the monitoring results of operational indicators. This method is used to statistically analyze and test the normal functions and performance data of the I2C controller. First, the CLK frequency monitoring function, communication throughput statistics function, Tbuf time monitoring function, and data correctness verification function of the test device are sequentially activated. The Tbuf time is the interval between the end of the current communication and the start of the next communication; at a 100K communication frequency, the minimum interval requirement is 4.7µs. The correctness of the communication data sent by the I2C controller is determined by calibrating the data. Second, the I2C controller sends read / write commands to the test device to check whether both the I2C controller and the test device have entered the read / write state normally. After stopping the test, the I2C controller obtains all monitoring data (I2C controller operational indicators) from the test device through the command channel. Furthermore, based on the relationship between each operational indicator and a preset threshold, the monitoring results of the I2C controller's operational indicators are determined, and a corresponding test report is generated.

[0092] Step 202: Configure the companion device to switch from the abnormal state of the I2C signal to the normal state of the I2C signal. During the state transition of the companion device, determine the signal quality detection result of the I2C controller based on the changes in the read and write states between the I2C controller and the companion device.

[0093] Specifically, by configuring a test device to switch from an abnormal I2C signal state to a normal I2C signal state, the simulation of I2C controller communication abnormality is realized. This test mode is mainly used to test the robustness of the I2C controller.

[0094] Step 203: Configure the test device to a functional abnormal state, and determine the detection result of the abnormal handling measures of the I2C controller based on the abnormal handling measures taken by the I2C controller when the test device is in a functional abnormal state.

[0095] Specifically, to perform additional functional testing on the I2C controller, the test device can be configured to several abnormal functional states. The appropriateness of the I2C controller's handling measures when the test device is in an abnormal state is determined, thus establishing the test results for the I2C controller's abnormal handling measures. Abnormal handling measures include retries and sending bus clear commands. When a specified fault occurs, the I2C controller should execute the corresponding recovery measures (abnormal handling measures). The accuracy of these measures can be verified using the test device. This allows for determination of whether the functional abnormality has been resolved based on the final communication results, and further detailed verification can be obtained through the I2C bus monitoring function of the test device.

[0096] Step 204: Determine the performance test results of the I2C controller based on the monitoring results of the I2C controller's operating indicators, signal quality test results, and anomaly handling measures test results.

[0097] Specifically, the performance test results of the I2C controller can be obtained by summarizing the monitoring results of the I2C controller's operating indicators, signal quality test results, and anomaly handling measures test results.

[0098] Specifically, in one embodiment, a performance test report for the I2C controller can be generated based on the monitoring results of the I2C controller's operating indicators, signal quality detection results, and anomaly handling measures detection results; the performance test report includes the performance test results of the I2C controller.

[0099] Specifically, according to the preset performance test report template, the I2C controller's performance test report can be generated based on the monitoring results of the I2C controller's operating indicators, signal quality test results, and anomaly handling measures test results. The performance test report includes information such as the I2C controller's performance test results and test time.

[0100] Based on the above embodiments, as an implementable approach, in one embodiment, a test device is configured to transition from an abnormal I2C signal state to a normal I2C signal state. During the state transition process of the test device, the signal quality detection result of the I2C controller is determined based on the changes in the read / write state between the I2C controller and the test device, including:

[0101] Step 2021: Configure the test device to an I2C signal abnormal state;

[0102] Step 2022: Control the I2C controller to send read / write commands to the test device in an abnormal I2C signal state;

[0103] Step 2023: If the I2C controller and the test device have not entered the read / write state, restore the test device to the normal I2C signal state and control the I2C controller to send read / write commands to the test device.

[0104] Step 2024: Determine whether the I2C controller and the device under test have entered the read / write state normally, and obtain the signal quality detection result of the I2C controller.

[0105] Specifically, the test device simulates various I2C signal anomalies according to its configuration. First, it controls the I2C controller to send read / write commands when the test device's I2C signal is abnormal. When the fault simulation is canceled, it controls the I2C controller to send read / write commands again to verify whether the I2C controller's function has returned to normal. The I2C controller should be able to communicate normally after the test device recovers from the anomaly. If the I2C controller continues to malfunction, it indicates a problem with the robustness of the I2C controller design, meaning the signal quality detection result of the I2C controller is abnormal.

[0106] Among them, such as Figure 5 The diagram shown illustrates another exemplary I2C controller detection method provided in this application. First, the test device is configured to an I2C signal abnormality state (SCL / SDA signal abnormality state) via a command channel. This simulates an SCL / SDA signal abnormality. The I2C controller then sends read / write commands to the test device in the I2C signal abnormality state. The system determines whether the I2C controller and the test device have entered a read / write state. If they have, the read / write operation is successful, and the signal quality detection result of the I2C controller is determined to be abnormal. If not, the operation is considered unsuccessful. If the read / write operation fails, the test device is restored to a normal I2C signal state. This means the simulation function of the abnormal SCL / SDA signal on the test device is canceled. Then, the I2C controller sends read / write commands to the test device and further judges the read / write status. If the I2C controller and the test device enter the read / write state normally, it means that the I2C controller can read and write normally after the test device switches to a normal I2C signal state. Therefore, the signal quality detection result of the I2C controller is determined to be normal. Otherwise, it is abnormal.

[0107] Based on the above embodiments, as an implementable approach, in one embodiment, the abnormal functional state includes a busy state. The abnormal handling measures taken by the I2C controller when the device under test is in a abnormal functional state are determined, including:

[0108] Step 2031: Configure the accompanying testing device to a busy state;

[0109] Step 2032: Control the I2C controller to send read / write commands to the test device in the busy state; wherein, after receiving the read / write command, the test device in the busy state sends a wait request to the I2C controller;

[0110] Step 2033: If the I2C controller enters a waiting state after receiving a waiting request, then the detection result of the abnormal handling measures of the I2C controller is determined to be normal.

[0111] Step 2034: If the I2C controller does not enter the waiting state after receiving the waiting request, then the detection result of the abnormal handling measures of the I2C controller is determined to be abnormal.

[0112] Specifically, such as Figure 6 The diagram illustrates a flowchart of another exemplary I2C controller detection method provided in this application. First, a configuration command is sent to the test device to configure it into a busy state, simulating an I2C clockstretch. In this state, the test device pauses a transmission by pulling the SCL line low until it is released to a high level, at which point the transmission resumes. Then, the I2C controller sends read / write commands to the busy test device. Upon receiving the commands, the test device sends a wait request to the I2C controller, prompting it to wait a preset time before initiating the read / write command again. Therefore, if the I2C controller enters a wait state after receiving the wait request, it indicates that the I2C controller has taken the correct exception handling measures, thus determining that the I2C controller's exception handling measure detection result is normal; otherwise, it is abnormal.

[0113] Specifically, in one embodiment, the abnormal functional state includes an I2C SDA signal low state. The test device can be configured to be in an I2C SDA signal low state. The I2C controller sends read and write commands to the test device in the I2C SDA signal low state. The I2C controller determines whether the test device is in an I2C SDA signal low state based on the test device's response to the read and write commands. If the I2C controller determines that the test device is in an I2C SDA signal low state and sends a target repair command to the test device, the abnormal handling measure detection result of the I2C controller is determined to be normal. If the I2C controller determines that the test device is in an I2C SDA signal low state but does not send a target repair command to the test device, the abnormal handling measure detection result of the I2C controller is determined to be abnormal.

[0114] Specifically, such as Figure 6As shown, firstly, a configuration command is sent to the test device to configure it to a low I2C SDA signal state, simulating an I2C SDA signal low state where SDA is continuously pulled low. Then, the I2C controller sends read and write commands to the test device in this low I2C SDA signal state. The I2C controller can determine the current low I2C SDA signal state based on the test device's response to these commands. If the I2C controller first sends a target repair command (I2C bus clear) to the test device and then sends read and write commands again, the I2C controller's anomaly handling detection result is considered normal. If the I2C controller does not send a target repair command to the test device, the anomaly handling detection result is considered abnormal. Here, "I2C bus clear" involves sending nine consecutive CLK clock cycles to attempt to recover the I2C bus.

[0115] Specifically, in one embodiment, the functional abnormal state includes a single command response abnormal state. The test device can be configured to a single command response abnormal state. The I2C controller is controlled to send read and write commands to the test device in the single command response abnormal state. If the test device does not respond to the read and write commands, and the I2C controller resends the read and write commands to the test device, the abnormal handling measure detection result of the I2C controller is determined to be normal. If the I2C controller does not resend the read and write commands to the test device, the abnormal handling measure detection result of the I2C controller is determined to be abnormal.

[0116] Specifically, such as Figure 6 As shown, a configuration command is first sent to the test device to configure it to a single-command response anomaly state, simulating a single-communication ACK signal response anomaly. Then, the I2C controller sends read / write commands to the test device in this state. The test device will not respond to these commands. If the I2C controller resends the read / write command to the test device, the anomaly handling mechanism detection result is considered normal; otherwise, if the I2C controller does not resend the read / write command, the anomaly handling mechanism detection result is considered abnormal.

[0117] The I2C controller testing method provided in this application obtains the monitoring results of the I2C controller's operating indicators based on a test device during the I2C controller's operation. The test device is configured to transition from an abnormal I2C signal state to a normal I2C signal state. During the state transition, the signal quality detection result of the I2C controller is determined based on the changes in the read / write state between the I2C controller and the test device. The test device is then configured to a functionally abnormal state, and the abnormal handling measures taken by the I2C controller when the test device is in a functionally abnormal state are used to determine the abnormal handling measure detection result of the I2C controller. Finally, the performance detection result of the I2C controller is determined based on the I2C controller's operating indicator monitoring results, signal quality detection results, and abnormal handling measure detection results. This method, by utilizing a test device, achieves automated testing of all I2C controller performance, improving the I2C controller testing efficiency and laying the foundation for improving the R&D quality and efficiency of switches.

[0118] This application provides an I2C controller detection device for executing the I2C controller detection method provided in the above embodiments.

[0119] like Figure 7 The diagram shown is a structural schematic of the I2C controller detection device provided in an embodiment of this application. The I2C controller detection device 70 includes: a monitoring module 701, a first determination module 702, a second determination module 703, and a detection module 704.

[0120] The system includes the following modules: a monitoring module, used to monitor the I2C controller's operating indicators based on the accompanying test device during operation, and obtain the monitoring results of the I2C controller's operating indicators; a first determination module, used to configure the accompanying test device to switch from an abnormal I2C signal state to a normal I2C signal state, and to determine the signal quality detection result of the I2C controller based on the changes in the read / write state between the I2C controller and the accompanying test device during the state transition; a second determination module, used to configure the accompanying test device to a functionally abnormal state, and to determine the detection result of the abnormal handling measures of the I2C controller based on the abnormal handling measures taken by the I2C controller when the accompanying test device is in a functionally abnormal state; and a detection module, used to determine the performance detection result of the I2C controller based on the monitoring results of the I2C controller's operating indicators, the signal quality detection result, and the abnormal handling measures detection result.

[0121] Specifically, in one embodiment, the first determining module is specifically used for:

[0122] Configure the accompanying testing device to an I2C signal abnormal state;

[0123] Control the I2C controller to send read and write commands to the test device when the I2C signal is abnormal;

[0124] If the I2C controller and the device under test have not entered the read / write state, the device under test will be restored to the normal I2C signal state, and the I2C controller will be controlled to send read / write commands to the device under test.

[0125] Determine whether the I2C controller and the device under test have entered the read / write state normally, and obtain the signal quality detection result of the I2C controller.

[0126] Specifically, in one embodiment, the abnormal functional state includes a busy state, and the second determining module is specifically used for:

[0127] Configure the accompanying testing equipment to be in a busy state;

[0128] The I2C controller sends read and write commands to the test device in a busy state; upon receiving the read and write command, the test device in a busy state sends a wait request to the I2C controller.

[0129] If the I2C controller enters a waiting state after receiving a waiting request, then the detection result of the I2C controller's abnormal handling measures is determined to be normal.

[0130] If the I2C controller does not enter the waiting state after receiving the waiting request, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

[0131] Specifically, in one embodiment, the abnormal functional state includes an I2C SDA signal low state, and the second determining module is specifically used for:

[0132] Configure the test equipment to be in a low I2C SDA signal state;

[0133] The I2C controller sends read and write commands to the test device when the I2C SDA signal is in a low state; the I2C controller determines whether the test device is in a low state of I2C SDA signal based on the test device's response to the read and write commands.

[0134] If the I2C controller determines that the device under test is in a low state of I2C SDA signal, it sends a target repair command to the device under test, and then the detection result of the abnormal handling measures of the I2C controller is determined to be normal.

[0135] If the I2C controller determines that the device under test is in a low I2C SDA signal state and does not send a target repair command to the device under test, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

[0136] Specifically, in one embodiment, the functional abnormal state includes a single command response abnormal state, and the second determining module is specifically used for:

[0137] Configure the monitoring device to respond to an abnormal state on a single command;

[0138] Control the I2C controller to send read and write commands to the test device in an abnormal single command response state;

[0139] If the I2C controller resends the read / write command to the test device when the test device does not respond, the test result of the I2C controller's abnormal handling measures is determined to be normal.

[0140] If the I2C controller does not resend the read / write command to the device under test, the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

[0141] Specifically, in one embodiment, the detection module is specifically used for:

[0142] Based on the monitoring results of the I2C controller's operating indicators, signal quality test results, and anomaly handling measures test results, a performance test report for the I2C controller is generated; the performance test report includes the performance test results of the I2C controller.

[0143] Specifically, in one embodiment, the operating metrics include at least CLK frequency, communication throughput, Tbuf time, and communication data accuracy.

[0144] Regarding the I2C controller detection device in this embodiment, the specific methods by which each module performs its operations have been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0145] The I2C controller detection device provided in this application embodiment is used to execute the I2C controller detection method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0146] This application provides a switch for executing the I2C controller detection method provided in the above embodiments.

[0147] like Figure 8 The diagram shown is a structural schematic of a switch provided in an embodiment of this application. The switch 80 includes: an I2C controller 81, a test device 82, at least one processor 83, and a memory 84.

[0148] The testing device is used as an I2C receiver to implement all the functions of an I2C Slave; the memory stores computer-executed instructions; at least one processor executes the computer-executed instructions stored in the memory, causing at least one processor to execute the I2C controller detection method provided in the above embodiment.

[0149] like Figure 9 The diagram shown is a schematic of an exemplary switch provided in this application embodiment. The FPGA implements the function of a PCIe to I2C controller. The CPLD module, acting as a companion device, implements the I2C Slave function and all the monitoring and fault simulation functions required for automated testing. The CPLD simulates multiple I2C slaves as a companion device for the I2C controller. This companion device simulates multiple I2CSlave interfaces for testing, while also providing one I2C Slave interface for receiving test configurations and obtaining test results.

[0150] The present application provides a switch for executing the I2C controller detection method provided in the above embodiments. Its implementation method and principle are the same, and will not be described again.

[0151] This application provides a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the I2C controller detection method provided in any of the above embodiments.

[0152] The storage medium containing computer-executable instructions in the embodiments of this application can be used to store the computer-executable instructions of the I2C controller detection method provided in the foregoing embodiments. Its implementation method and principle are the same, and will not be described again.

[0153] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0154] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0155] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0156] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0157] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is merely an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An I2C controller detection method, applied to a switch, characterized in that, The switch includes an I2C controller and a test device, the test device being used as an I2C receiver, and the method includes: During the operation of the I2C controller, the operating indicators of the I2C controller are monitored based on the accompanying testing device to obtain the monitoring results of the operating indicators of the I2C controller; the operating indicators include at least CLK frequency, communication throughput, Tbuf time, and communication data accuracy. The accompanying testing device is configured to switch from an abnormal I2C signal state to a normal I2C signal state. During the state transition of the accompanying testing device, the signal quality detection result of the I2C controller is determined based on the changes in the read and write states between the I2C controller and the accompanying testing device. The companion device is configured to be in a functional abnormal state. Based on the abnormal handling measures taken by the I2C controller when the companion device is in a functional abnormal state, the detection result of the abnormal handling measures of the I2C controller is determined. Based on the monitoring results of the operating indicators, signal quality detection results, and anomaly handling measures of the I2C controller, the performance detection results of the I2C controller are determined. The configuration of the companion device involves transitioning the I2C signal from an abnormal state to a normal state. During this transition, the signal quality detection result of the I2C controller is determined based on the read / write state changes between the I2C controller and the companion device, including: Configure the accompanying testing device to an I2C signal abnormal state; The I2C controller is controlled to send read / write commands to the test device in an abnormal I2C signal state. If the I2C controller and the test device have not entered the read / write state, the test device will be restored to the normal I2C signal state, and the I2C controller will be controlled to send read / write commands to the test device. Determine whether the I2C controller and the accompanying device have entered the read / write state normally, and obtain the signal quality detection result of the I2C controller.

2. The method according to claim 1, characterized in that, The abnormal functional state includes a busy state. The determination of the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the device under test is in a abnormal functional state includes: Configure the accompanying testing device to a busy state; The I2C controller is controlled to send read and write commands to the test device in a busy state; wherein, after receiving the read and write command, the test device in a busy state sends a wait request to the I2C controller; If the I2C controller enters a waiting state after receiving a waiting request, then the detection result of the abnormal handling measures of the I2C controller is determined to be normal. If the I2C controller does not enter a waiting state after receiving a waiting request, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

3. The method according to claim 1, characterized in that, The abnormal functional state includes a low I2C SDA signal state. The determination of the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the device under test is in a abnormal functional state includes: Configure the accompanying testing device to a low I2C SDA signal state; The I2C controller is controlled to send read and write commands to the companion device in the I2C SDA signal low state; wherein, the I2C controller determines whether the companion device is in the I2C SDA signal low state based on the companion device's response to the read and write commands; If the I2C controller determines that the device under test is in a low I2C SDA signal state, and sends a target repair command to the device under test, then the abnormal handling measures detection result of the I2C controller is determined to be normal. If the I2C controller determines that the device under test is in a low I2C SDA signal state and does not send a target repair command to the device under test, then the abnormal handling measures detection result of the I2C controller is determined to be abnormal.

4. The method according to claim 1, characterized in that, The abnormal functional state includes a single command response abnormal state. The step of determining the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the device under test is in a abnormal functional state includes: Configure the accompanying testing device to a single command response abnormal state; The I2C controller is controlled to send read / write commands to the companion device in an abnormal single command response state. If the I2C controller resends the read / write command to the test device when the test device does not respond, then the detection result of the abnormal handling measures of the I2C controller is determined to be normal. If the I2C controller does not resend the read / write command to the test device, then the detection result of the I2C controller's abnormal handling measures is determined to be abnormal.

5. The method according to claim 1, characterized in that, The determination of the performance test results of the I2C controller based on the monitoring results of the I2C controller's operating indicators, signal quality detection results, and anomaly handling measures detection results includes: Based on the monitoring results of the I2C controller's operating indicators, signal quality detection results, and anomaly handling measures detection results, a performance test report for the I2C controller is generated; the performance test report includes the performance test results of the I2C controller.

6. An I2C controller detection device, applied to a switch, characterized in that, The switch includes an I2C controller and a test device, the test device being used as an I2C receiver, the device comprising: The monitoring module is used to monitor the operating indicators of the I2C controller based on the accompanying testing device during the operation of the I2C controller, and obtain the monitoring results of the operating indicators of the I2C controller; the operating indicators include at least CLK frequency, communication throughput, Tbuf time, and communication data accuracy. The first determining module is used to configure the companion device to switch from an abnormal I2C signal state to a normal I2C signal state. During the state transition of the companion device, the signal quality detection result of the I2C controller is determined based on the read / write state changes between the I2C controller and the companion device. The second determining module is used to configure the companion device to a functional abnormal state, and determine the abnormal handling measures detection result of the I2C controller based on the abnormal handling measures taken by the I2C controller when the companion device is in a functional abnormal state. The detection module is used to determine the performance test results of the I2C controller based on the monitoring results of the I2C controller's operating indicators, signal quality test results, and anomaly handling measures test results. The first determining module is specifically used for: Configure the accompanying testing device to an I2C signal abnormal state; The I2C controller is controlled to send read / write commands to the test device in an abnormal I2C signal state. If the I2C controller and the test device have not entered the read / write state, the test device will be restored to the normal I2C signal state, and the I2C controller will be controlled to send read / write commands to the test device. Determine whether the I2C controller and the accompanying device have entered the read / write state normally, and obtain the signal quality detection result of the I2C controller.

7. A switch, characterized in that, include: I2C controller, test device, at least one processor and memory; The accompanying testing device is used as an I2C receiver; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the method as described in any one of claims 1 to 5.

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