Pixel circuit

Abstract

A pixel circuit. The pixel circuit includes a light emitting diode, a voltage selection region, and a driving region. The light emitting diode has an anode and a cathode receiving a system low voltage. The voltage selection region receives a first system high voltage, a second system high voltage, and a gray scale signal to output one of the first system high voltage and the second system high voltage as a system high voltage based on the gray scale signal, wherein the first system high voltage is higher than the second system high voltage. The driving region is coupled to the anode of the light emitting diode and the voltage selection region, and receives a data voltage and the system high voltage to provide a driving current to the light emitting diode based on the data voltage and the system high voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to a pixel circuit, and particularly relates to a light emitting diode pixel circuit. BACKGROUND

[0002] Due to the increasing environmental awareness, the demands of energy saving, service life, color saturation and power quality gradually become the factors considered by consumers when purchasing, and the rapid development of semiconductor technology and cost reduction drive light emitting elements to become the mainstream of the future lighting and display market. Among them, organic light emitting diodes (OLED) and micro light emitting diodes (uLED) are the main elements used in self-luminous display panels at present.

[0003] Since micro light emitting diodes (uLED) require a large driving current, when outputting high brightness, the large current will cause the driving transistor to enter the linear region, causing the driving current to be difficult to control. Although increasing the voltage across the system voltage can solve the above problem, it will increase power consumption. Therefore, in order to solve the problem of power consumption, the existing driving circuit needs to be modified or redesigned accordingly. SUMMARY

[0004] The present application provides a pixel circuit, which can reduce the voltage across the system voltage terminals when outputting low brightness, to achieve the effect of saving power consumption.

[0005] The pixel circuit of the present application includes a light emitting diode, a voltage selection region and a driving region. The light emitting diode has an anode and a cathode that receives a system low voltage. The voltage selection region receives a first system high voltage, a second system high voltage, and a gray scale signal to output one of the first system high voltage and the second system high voltage as a system high voltage based on the gray scale signal, wherein the first system high voltage is higher than the second system high voltage. The driving region is coupled to the anode of the light emitting diode and the voltage selection region, and receives a data voltage and a system high voltage to provide a driving current to the light emitting diode based on the data voltage and the system high voltage.

[0006] Based on the above, the pixel circuit of the present application embodiment outputs one of the first system high voltage and the second system high voltage based on the gray scale signal, that is, by modulating the voltage level of the system high voltage under high gray scale and low gray scale, the voltage across the system high voltage and the system low voltage required when the low gray scale is reduced, and the power consumption of the pixel circuit is reduced.

[0007] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are specifically described below, and the detailed description is made in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1A circuit schematic of a pixel circuit according to an embodiment of the present application.

[0009] Figure 2 A schematic of a driving waveform of a pixel circuit according to an embodiment of the present application to display a low gray scale.

[0010] Figure 3 A schematic of a driving waveform of a pixel circuit according to an embodiment of the present application to display a high gray scale.

[0011] BRIEF DESCRIPTION OF DRAWINGS

[0012] 100: Pixel circuit

[0013] 110: Voltage selection region

[0014] 120: Driving region

[0015] A, B, C, D, E, F: Node voltage

[0016] Ad1: First adjustment period

[0017] Ad2: Second adjustment period

[0018] C1: First capacitor

[0019] C2: Second capacitor

[0020] C3: Third capacitor

[0021] Cmp: Compensation period

[0022] EM1: First emission control signal

[0023] EM2: Second emission control signal

[0024] Emi: Emission period

[0025] Idr: Driving current

[0026] LD1: Light emitting diode

[0027] Poff: Off period

[0028] Rst: Reset period

[0029] S1: First control signal

[0030] S2: Second control signal

[0031] S3: Third control signal

[0032] T1: First transistor

[0033] T10: Tenth transistor

[0034] T2: Second transistor

[0035] T3: third transistor

[0036] T4: fourth transistor

[0037] T5: fifth transistor

[0038] T6: sixth transistor

[0039] T7: seventh transistor

[0040] T8: eighth transistor

[0041] T9: ninth transistor

[0042] V DATA : data voltage

[0043] VDD: system high voltage

[0044] VDD_H: first system high voltage

[0045] VDD_L: second system high voltage

[0046] V GH : gate high voltage

[0047] V GL : gate low voltage

[0048] V GRAY : gray scale signal

[0049] V GRAY_H : gray scale high voltage

[0050] V GRAY_L : gray scale low voltage

[0051] V H : high voltage

[0052] V REF : reference voltage

[0053] VSS: system low voltage DETAILED DESCRIPTION

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] It should be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one," unless the content clearly indicates otherwise. "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood by those within the art that, in some aspects of the disclosure, terms such as "including," and / or "having," etc., are intended to mean "including, without limitation," "comprising, without limitation," "consisting, without limitation," "having, without limitation," or "including at least" that is, that not all equivalents are present.

[0057] Figure 1 A circuit schematic diagram of a pixel circuit according to an embodiment of the present disclosure. Please refer to Figure 1 In the embodiment of the present disclosure, the pixel circuit 100 includes a light emitting diode LD1, a voltage selection region 110, and a driving region 120. The light emitting diode LD1 includes, for example, a micro light emitting diode, but the embodiment of the present disclosure is not limited thereto.

[0058] The light emitting diode LD1 has an anode and a cathode receiving a system low voltage VSS. The voltage selection region 110 receives a first system high voltage VDD H, a second system high voltage VDD L, and a gray scale signal V GRAY to output one of the first system high voltage VDD H and the second system high voltage VDD L as a system high voltage VDD based on the gray scale signal VGRAY, wherein the first system high voltage VDD H is higher than the second system high voltage VDD L. The driving region 120 is coupled to the anode of the light emitting diode LD1 and the voltage selection region 110 and receives a data voltage VDATA and a system low voltage VSS. DATA to provide a driving current Idr to the light emitting diode LD1 with the system high voltage VDD. DATA to provide a driving current Idr to the light emitting diode LD1 with the system high voltage VDD.

[0059] According to the above, the voltage selection region 110 outputs one of the first system high voltage VDD H and the second system high voltage VDD L as the system high voltage VDD based on the gray scale signal V GRAYThe output of one of the first system high voltage VDD_H and the second system high voltage VDD_L, that is, by modulating the voltage level of the system high voltage VDD under the high gray scale and the low gray scale, the cross voltage between the system high voltage VDD and the system low voltage VSS required at the low gray scale is reduced, and the power consumption of the pixel circuit 100 is reduced.

[0060] In this embodiment, the voltage selection region 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2, wherein the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are each taken as an example of a P-type transistor, but embodiments of the present application are not limited thereto.

[0061] The first transistor T1 has a first end receiving the first system high voltage VDD_H, a control end, and a second end providing the system high voltage VDD. The second transistor T2 has a first end receiving the gray scale signal V GRAY , a control end receiving the first control signal S1, and a second end. The third transistor T3 has a first end receiving the high voltage V H , a control end coupled to the second end of the second transistor T2, and a second end coupled to the control end of the first transistor T1. The first capacitor C1 is coupled between the control end of the first transistor T1 and the first light emitting control signal EM1.

[0062] The fourth transistor T4 has a first end receiving the gray scale signal V GRAY , a control end receiving the second control signal S2, and a second end. The fifth transistor T5 has a first end, a control end coupled to the second end of the fourth transistor T4, and a second end receiving the high voltage V H . The sixth transistor T6 has a first end receiving the second system high voltage VDD_L, a control end coupled to the first end of the fifth transistor T5, and a second end coupled to the first end of the first transistor T1. The second capacitor C2 is coupled between the control end of the sixth transistor T6 and the first light emitting control signal EM1.

[0063] In this embodiment, the driving region 120 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a third capacitor C3, wherein the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are each taken as an example of a P-type transistor, but embodiments of the present application are not limited thereto.

[0064] The seventh transistor T7 has a first terminal receiving the system high voltage VDD, a control terminal, and a second terminal coupled to an anode of the light emitting diode LD1. The eighth transistor T8 has a first terminal coupled to the control terminal of the seventh transistor T7, a control terminal receiving the third control signal S3, and a second terminal receiving a reference voltage V REF . The ninth transistor T9 has a first terminal receiving the system high voltage VDD, a control terminal receiving the first light emitting control signal EM1, and a second terminal. The third capacitor C3 is coupled between the second terminal of the ninth transistor T9 and the control terminal of the seventh transistor T7. The tenth transistor T10 has a first terminal coupled to the second terminal of the ninth transistor T9, a control terminal receiving the data voltage V DATA , and a second terminal receiving the second light emitting control signal EM2.

[0065] In an embodiment of the present application, the seventh transistor T7 can be matched with the tenth transistor T10, i.e. the aspect ratio of the seventh transistor T7 is the same as the aspect ratio of the tenth transistor T10.

[0066] In an embodiment of the present application, when the luminance displayed by the pixel circuit 100 is in a low gray scale range (e.g. gray scale 0-31), the second system high voltage VDD_L does not cause the seventh transistor T7 to operate in a linear region, i.e. the seventh transistor T7 operates in a saturation region; when the luminance displayed by the pixel circuit 100 is in a high gray scale range (e.g. gray scale 32-255), the second system high voltage VDD_L causes the seventh transistor T7 to operate in a linear region. Moreover, regardless of whether it is a high gray scale range or a low gray scale range, the second system high voltage VDD_L does not cause the seventh transistor T7 to operate in a linear region.

[0067] In an embodiment of the present application, when the gray scale signal V GRAY corresponds to a low gray scale (e.g. gray scale 0-31), the voltage selection region 110 outputs the second system high voltage VDD_L as the system high voltage VDD, and when the gray scale signal V GRAY corresponds to a high gray scale (e.g. gray scale 32-255), the voltage selection region 110 outputs the first system high voltage VDD_H as the system high voltage VDD.

[0068] In an embodiment of the present application, the gray scale signal V GRAY is provided by a control circuit (e.g. a timing controller) external to the pixel circuit 100, and each pixel circuit 100 receives a single gray scale signal V GRAY , i.e. the gray scale signal V GRAY received by the pixel circuit 100 is different from the gray scale signal V GRAY of another pixel circuit.

[0069] Figure 2Fig. 1 shows a driving waveform diagram of a pixel circuit according to an embodiment of the present application for displaying a low gray scale. In the following description, the pixel circuit 100 is operated in sequence in a reset period Rst, a first adjusting period Adl, a compensation period Cmp, a second adjusting period Ad2, an emission period Emi, and an off period Poff. Figure 1 Figure 2 In this embodiment, the pixel circuit 100 is operated in sequence in the reset period Rst, the first adjusting period Adl, the compensation period Cmp, the second adjusting period Ad2, the emission period Emi, and the off period Poff.

[0070] In the reset period Rst, the first control signal S1 and the third control signal S3 are enabled (e.g., a gate low voltage V GL ), and the second control signal S2, the first emission control signal EM1, and the second emission control signal EM2 are disabled (e.g., a gate high voltage V GH ). At this time, the gray scale signal V GRAY is a low gray scale voltage V GRAY_L . In this case, the second transistor T2 and the eighth transistor T8 are turned on, and the fourth transistor T4 and the ninth transistor T9 are turned off. The node voltage A at the control end of the first transistor T1 is a high voltage V H , the node voltage B at the control end of the sixth transistor T6 is an unknown voltage V X , the node voltage C at the control end of the seventh transistor T7 is a reference voltage V REF , the node voltage D at the second end of the ninth transistor T9 is a gate high voltage V GH , the node voltage E at the control end of the third transistor T3 is a low gray scale voltage V GRAY_L , and the node voltage F at the control end of the fifth transistor T5 is an unknown voltage V X . In addition, the first transistor T1 is turned off due to the node voltage A, the third transistor T3 is turned on due to the node voltage E, the fifth transistor T5 is in an unknown state due to the node voltage F, the sixth transistor T6 is in an unknown state due to the node voltage B, the seventh transistor T7 is turned off due to the node voltage C, and the tenth transistor T10 is turned on due to the data voltage V DATA .

[0071] In the first adjusting period Adl, the same operation state as in the reset period Rst is maintained.

[0072] In the compensation period Cmp, the second control signal S2, the third control signal S3, and the second emission control signal EM2 are enabled, and the first control signal S1 and the first emission control signal EM1 are disabled. At this time, the gray scale signal V GRAY is a low gray scale voltage V GRAY_L . In this case, the fourth transistor T4 and the eighth transistor T8 are turned on, and the second transistor T2 and the ninth transistor T9 are turned off. The node voltage A at the control end of the first transistor T1 is a high voltage V H ​, the node voltage B of the control end of the sixth transistor T6 is a high voltage V H , the node voltage C of the control end of the seventh transistor T7 is a reference voltage V REF , the node voltage D of the second end of the ninth transistor T9 is a data voltage V DATA ┼ the threshold voltage V of the tenth transistor T10 TH10 , the node voltage E of the control end of the third transistor T3 is a gray scale low voltage V GRAY_L , the node voltage F of the control end of the fifth transistor T5 is a gray scale low voltage V GRAY_L . And the first transistor T1 is turned off due to the node voltage A, the third transistor T3 is turned on due to the node voltage E, the fifth transistor T5 is turned on due to the node voltage F, the sixth transistor T6 is turned off due to the node voltage B, the seventh transistor T7 is turned off due to the node voltage C, and the tenth transistor T10 is turned on due to the data voltage V DATA .

[0073] In the second adjustment period Ad2, the operation of the pixel circuit 100 is substantially the same as in the compensation period Cmp, except that the gray scale signal V GRAY is changed to a gray scale high voltage V GRAY_H , so that the node voltage F of the control end of the fifth transistor T5 is changed to a gray scale high voltage V GRAY_H . At this time, the fifth transistor T5 is turned off due to the node voltage F.

[0074] In the emission period Emi, the first emission control signal EM1 and the second emission control signal EM2 are enabled levels, and the first control signal S1, the second control signal S2 and the third control signal S3 are disabled levels, wherein the voltage level of the gray scale signal V GRAY has no effect on the operation of the pixel circuit 100, and can be set for the next pixel circuit 100. At this time, the ninth transistor T9 is turned on, and the second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned off. Among them, the node voltage A of the control end of the first transistor T1 is a high voltage V H , the node voltage B of the control end of the sixth transistor T6 is a high voltage V H ┼ gate low voltage V GL - gate high voltage V GH , the node voltage C of the control end of the seventh transistor T7 is (second system high voltage VDD_L - data voltage V DATA ┼ threshold voltage V of the tenth transistor T10 TH10 )┼ reference voltage V REF , the node voltage D of the second end of the ninth transistor T9 is the second system high voltage VDD_L, and the node voltage E of the control end of the third transistor T3 is a gray scale low voltage V GRAY_LThe node voltage F of the control end of the fifth transistor T5 is a gray scale high voltage V GRAY_H . Moreover, the first transistor T1 is turned off due to the node voltage A, the third transistor T3 is turned on due to the node voltage E, the fifth transistor T5 is turned off due to the node voltage F, the sixth transistor T6 is turned on due to the node voltage B, the seventh transistor T7 is turned on due to the node voltage C, and the tenth transistor T10 is turned off due to the data voltage V DATA . At this time, the driving current Idr is related to the data voltage V DATA and the reference voltage V REF .

[0075] In the off period Poff, the first control signal S1, the second control signal S2, the third control signal S3, the first light emitting control signal EM1 and the second light emitting control signal EM2 are disabled voltage levels, in which the voltage level of the gray scale signal V GRAY has no effect on the operation of the pixel circuit 100. The second transistor T2, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 are turned off. In which, the node voltage A of the control end of the first transistor T1 is a high voltage V H , the node voltage B of the control end of the sixth transistor T6 is a high voltage V H , the node voltage C of the control end of the seventh transistor T7 is (gate high voltage V GH - data voltage V DATA ┼ threshold voltage V TH10 ┼ reference voltage V REF , the node voltage D of the second end of the ninth transistor T9 is a gate high voltage V GH , the node voltage E of the control end of the third transistor T3 is a gray scale low voltage V GRAY_L , the node voltage F of the control end of the fifth transistor T5 is a gray scale high voltage V GRAY_H . Moreover, the first transistor T1 is turned off due to the node voltage A, the third transistor T3 is turned on due to the node voltage E, the fifth transistor T5 is turned off due to the node voltage F, the sixth transistor T6 is turned off due to the node voltage B, the seventh transistor T7 is turned off due to the node voltage C, and the tenth transistor T10 is turned on due to the data voltage V DATA .

[0076] Figure 3 is a driving waveform diagram of a pixel circuit for displaying a high gray scale according to an embodiment of the present application. In reference to Figure 1 , Figure 2 and Figure 3 , the operation of the pixel circuit 100 in this embodiment is substantially the same as shown in Figure 2 , in which the same or similar elements use the same or similar reference numerals. Figure 2 and Figure 3The difference between the embodiments is that, in the first adjustment period Ad1, the node voltage E of the control end of the third transistor T3 is the gray scale high voltage V GRAY_H , so that the third transistor T3 is in cutoff; in the second adjustment period Ad2, the node voltage F of the control end of the fifth transistor T5 is the gray scale low voltage V GRAY_L , so that the fifth transistor T5 is in conduction; in the light emitting period Emi, the node voltage C of the control end of the seventh transistor T7 is (the first system high voltage VDD_H - the data voltage V DATA ┼ the threshold voltage V of the tenth transistor T10 TH10 )┼ the reference voltage V REF , the node voltage D of the second end of the ninth transistor T9 is the first system high voltage VDD_H.

[0077] Referring to the embodiments of the present application Figure 2 and Figure 3 , the waveform of the gray scale signal V GRAY corresponding to the low gray scale is different from the waveform of the gray scale signal V GRAY corresponding to the high gray scale.

[0078] According to the above, the embodiments of the present application can propose a 10T3C circuit architecture for a micro light emitting diode pixel circuit, which is applied to a micro light emitting diode tiled display. Wherein, the pixel circuit 100 can reduce the cross voltage between the system high voltage VDD and the system low voltage VSS required at the low gray scale by modulating the voltage level of the system high voltage VDD at the high gray scale and the low gray scale, thereby reducing the power consumption of the pixel circuit 100. Further, by matching the seventh transistor T7 with the tenth transistor T10, the threshold voltage variation of the driving transistor (i.e. the seventh transistor T7) can be compensated, and the level waveform of the gray scale signal V GRAY is used to select the current path, i.e. when displaying the high gray scale, the sixth transistor T6 is cut off, and the cross voltage of the current path is the first system high voltage VDD_H to the system low voltage VSS; on the contrary, when displaying the low gray scale, the first transistor T1 is cut off, and the cross voltage of the current path is the second system high voltage VDD_L to the system low voltage VSS, so as to reduce the static power consumption at the low gray scale.

[0079] Therefore, the total cross voltage between the system high voltage VDD and the system low voltage VSS of the current path at the low gray scale is effectively reduced, the effect of saving power consumption is achieved, and the power supply voltage rise (I-R Rise) of the system low voltage VSS and the threshold voltage variation of the seventh transistor T7 can be compensated, so as to increase the consistency of the light emitting current. Moreover, when light emitting, the variation amount of the first light emitting signal EM1 can be coupled to the control end of the first transistor T1 through the third capacitor C3 to make the light emitting diode LD1 start light emitting.

[0080] In the embodiment, only the tenth transistor T10 is used to achieve the functions of resetting, compensating and cutting off, so that the overall architecture can be simplified.

[0081] In summary, in the pixel circuit of the embodiment of the present application, the voltage selection region outputs one of the first system high voltage and the second system high voltage based on the gray scale signal, that is, by modulating the voltage level of the system high voltage under high gray scale and low gray scale, the voltage across the system high voltage and the system low voltage required under low gray scale is reduced, and the power consumption of the pixel circuit is reduced.

[0082] Although the present application has been disclosed with the embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present application, so the protection scope of the present application shall be subject to the definition of the claims.

Claims

1. A pixel circuit, comprising: a light emitting diode having an anode and a cathode receiving a system low voltage; a voltage selection region receiving a first system high voltage, a second system high voltage, and a gray scale signal to output one of the first system high voltage and the second system high voltage as a system high voltage based on the gray scale signal, wherein the first system high voltage is higher than the second system high voltage; a driving region coupled to the anode of the light emitting diode and the voltage selection region and receiving a data voltage and the system high voltage to provide a driving current to the light emitting diode based on the data voltage and the system high voltage, wherein the voltage selection region comprises: a first transistor having a first terminal receiving the first system high voltage, a control terminal, and a second terminal providing the system high voltage; a second transistor having a first terminal receiving the gray scale signal, a control terminal receiving a first control signal, and a second terminal; a third transistor having a first terminal receiving a high voltage, a control terminal coupled to the second terminal of the second transistor, and a second terminal coupled to the control terminal of the first transistor; a first capacitor coupled between the control terminal of the first transistor and a first light emitting control signal; a fourth transistor having a first terminal receiving the gray scale signal, a control terminal receiving a second control signal, and a second terminal; a fifth transistor having a first terminal, a control terminal coupled to the second terminal of the fourth transistor, and a second terminal receiving the high voltage; a sixth transistor having a first terminal receiving the second system high voltage, a control terminal coupled to the first terminal of the fifth transistor, and a second terminal coupled to the first terminal of the first transistor; and a second capacitor coupled between the control terminal of the sixth transistor and the first light emitting control signal.

2. The pixel circuit of claim 1, wherein the driving region comprises: a seventh transistor having a first terminal receiving the system high voltage, a control terminal, and a second terminal coupled to the anode of the light emitting diode; an eighth transistor having a first terminal coupled to the control terminal of the seventh transistor, a control terminal receiving a third control signal, and a second terminal receiving a reference voltage; a ninth transistor having a first terminal receiving the system high voltage, a control terminal receiving the first light emitting control signal, and a second terminal; a third capacitor coupled between the second terminal of the ninth transistor and the control terminal of the seventh transistor; and a tenth transistor having a first terminal coupled to the second terminal of the ninth transistor, a control terminal receiving the data voltage, and a second terminal receiving a second light emitting control signal.

3. The pixel circuit of claim 2, wherein a length to width ratio of the seventh transistor is the same as a length to width ratio of the tenth transistor. ​ 4. The pixel circuit of claim 2, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are each a P-type transistor.

5. The pixel circuit of claim 2, wherein when a luminance displayed by the pixel circuit is in a low gray scale range, the second system high voltage does not cause the seventh transistor to operate in a linear region; when the luminance displayed by the pixel circuit is in a high gray scale range, the second system high voltage causes the seventh transistor to operate in the linear region.

6. The pixel circuit of claim 1, wherein when the gray scale signal corresponds to a low gray scale, the voltage selection region outputs the second system high voltage as the system high voltage, and when the gray scale signal corresponds to a high gray scale, the voltage selection region outputs the first system high voltage as the system high voltage.

7. The pixel circuit of claim 6, wherein a waveform of the gray scale signal corresponding to the low gray scale is different from a waveform of the gray scale signal corresponding to the high gray scale.

8. The pixel circuit of claim 1, wherein the light emitting diode comprises a micro light emitting diode.

9. The pixel circuit of claim 1, wherein the gray scale signal is different from a gray scale signal of another pixel circuit.

10. The pixel circuit of claim 1, wherein the gray scale signal is provided by a control circuit external to the pixel circuit.

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