Data processing method, forwarding chip, storage medium and program product

Abstract

The application discloses a data processing method, a forwarding chip, a storage medium and a program product, wherein the data processing method comprises the following steps: acquiring input parameters, the input parameters being used for generating index values filled in an index table; performing data duplication processing on the input parameters to obtain a plurality of input parameters; performing corresponding data mapping processing on each input parameter to obtain a plurality of output variables; and performing data integration processing on the plurality of output variables to obtain the index values. Therefore, according to the scheme of the embodiment of the application, the correlation between the index value bit positions can be reduced, the number of algorithm rounds required to ensure the independence of the output bits can be reduced, and thus the influence on the stability of the optimal filling rate and the algorithm delay can be reduced.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a data processing method, a forwarding chip, a storage medium, and a program product. Background Technology

[0002] In forwarding chips, lookup tables are typically implemented using hash table structures. The key is used as the input value to the hash function to obtain the hash table's index value. In related technologies, the Cyclic Redundancy Check (CRC) algorithm is often used as the hash function in forwarding chips. However, this presents some problems. For example, the index value bits output by the CRC algorithm are a simple XOR of certain bits in the key. Therefore, the index value bits of this algorithm have a high correlation, which can seriously affect the stability of the hash table's optimal fill rate. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This invention provides a data processing method, a forwarding chip, a storage medium, and a program product, which can reduce the correlation between index value bits and reduce the number of algorithm rounds required to ensure the independence of output bits, thereby reducing the impact on the stability of the optimal fill rate and the algorithm latency.

[0005] In a first aspect, embodiments of the present invention provide a data processing method, including:

[0006] The process involves: acquiring input parameters, which are used to generate index values ​​to fill an index table; performing data copying on the input parameters to obtain multiple input parameters; performing corresponding data mapping on each input parameter to obtain multiple output variables; and performing data integration on the multiple output variables to obtain the index values.

[0007] In a second aspect, embodiments of the present invention also provide a forwarding chip, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the data processing method described in the first aspect above.

[0008] Thirdly, embodiments of the present invention also provide a computer-readable storage medium storing computer-executable instructions for performing the data processing method described above.

[0009] Fourthly, embodiments of the present invention also provide a computer program product, including a computer program or computer instructions, wherein the computer program or computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, causing the computer device to perform the data processing method as described above.

[0010] This invention includes: acquiring input parameters, which are used to generate index values ​​to fill an index table; performing data copying on the input parameters to obtain multiple input parameters; performing corresponding data mapping on each input parameter to obtain multiple output variables; and performing data integration on the multiple output variables to obtain index values. In other words, by performing data copying on the input parameters to obtain multiple input parameters, and performing parallel data mapping on these multiple input parameters to obtain a mixture of multiple output variables, this design structure reduces the critical path latency of the fully-laid circuit. Therefore, by mixing multiple output variables, the number of algorithm rounds required to ensure the independence of output bits is effectively reduced, thereby reducing algorithm latency. Furthermore, since the correlation between different output variables obtained by performing corresponding data mapping on each input parameter is low, the bits of the index values ​​obtained by integrating multiple of these output variables have low correlation, thus reducing the impact on the stability of the optimal fill rate. Therefore, the solution of this invention can reduce the correlation between index value bits and reduce the number of algorithm rounds required to ensure the independence of output bits, thereby reducing the impact on the stability of the optimal fill rate and algorithm latency.

[0011] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0012] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0013] Figure 1 This is a flowchart of a data processing method provided in one embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of a non-last round mapping process provided in an embodiment of the present invention;

[0015] Figure 3This is a schematic diagram of the final round mapping process provided in one embodiment of the present invention;

[0016] Figure 4 yes Figure 1 A flowchart of a specific method for step S120;

[0017] Figure 5 yes Figure 4 A flowchart of a specific method for step S210;

[0018] Figure 6 yes Figure 4 A flowchart of another specific method for step S210;

[0019] Figure 7 yes Figure 1 A flowchart of a specific method for step S140;

[0020] Figure 8 This is a schematic diagram of a data processing method provided in a specific example of the present invention;

[0021] Figure 9 This is a schematic diagram of the structure of a forwarding chip provided in one embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0023] It should be noted that although the flowchart shows a logical order, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. In the description of the specification, claims, and the foregoing drawings, "multiple" means two or more; "greater than," "less than," and "exceeding" are understood to exclude the stated number; "above," "below," and "within" are understood to include the stated number. The use of terms such as "first" and "second" is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly specifying the number of indicated technical features or their sequential relationship.

[0024] This invention provides a data processing method, a forwarding chip, a storage medium, and a program product. The method involves acquiring input parameters, which are used to generate index values ​​to fill an index table; copying the input parameters to obtain multiple input parameters; performing corresponding data mapping on each input parameter to obtain multiple output variables; and integrating the multiple output variables to obtain the index value. In other words, by copying the input parameters to obtain multiple input parameters and performing parallel data mapping on these multiple input parameters to obtain a mixture of multiple output variables, this design structure reduces the critical path latency of the entire circuit. Therefore, by mixing multiple output variables, the number of algorithm rounds required to ensure the independence of output bits is effectively reduced, thereby reducing algorithm latency. Furthermore, since the correlation between different output variables obtained by corresponding data mapping on each input parameter is low, the bits of the index value obtained by integrating multiple of these output variables also have low correlation, thus reducing the impact on the stability of the optimal fill rate. Therefore, the solution of this invention can reduce the correlation between index value bits and reduce the number of algorithm rounds required to ensure the independence of output bits, thereby reducing the impact on the stability of the optimal fill rate and algorithm latency.

[0025] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0026] like Figure 1 As shown, Figure 1 This is a flowchart of a data processing method provided in an embodiment of the present invention. The data processing method may include, but is not limited to, steps S110, S120, S130 and S140.

[0027] Step S110: Obtain input parameters, which are used to generate index values ​​to populate the index table.

[0028] In this step, the input parameters can be of any length, such as 16 bits, 32 bits, 128 bits, 512 bits, or other numerical bit lengths, etc., without any specific limitations.

[0029] Step S120: Perform data copying on the input parameters to obtain multiple input parameters.

[0030] In this step, since multiple input parameters are obtained by data copying of the input parameters, subsequent steps can perform different data mapping processes on these multiple input parameters in parallel.

[0031] Step S130: Perform corresponding data mapping processing on each input parameter to obtain multiple output variables.

[0032] In this step, since multiple input parameters are obtained by data copying in step S120, the corresponding data mapping processing of each input parameter can be performed simultaneously in this step to obtain multiple output variables. That is, by mixing multi-branch output variables, the number of algorithm rounds required to ensure the independence of output bits can be effectively reduced, thereby reducing the algorithm latency.

[0033] It should be noted that the data mapping process includes non-final round mapping and final round mapping. Non-final round mapping includes S-box processing, bit transposition processing, and matrix multiplication, while final round mapping includes S-box processing and bit transposition processing. The bit transposition processes differ between the different data mapping processes. Because a partially linear layer design is used in the final round mapping process—that is, only S-box processing and bit transposition processing are performed, without matrix multiplication—this embodiment can further optimize processing latency and the circuit area of ​​the algorithm implementation while maintaining the independence of the algorithm's output bits.

[0034] It should be noted that the bit transposition process differs in different data mapping processes, which is reflected in the different values ​​of the bit transposition process.

[0035] It should be noted that in cryptography, the S-box (Substitution-box) is the basic structure for symmetric key algorithms to perform permutation calculations. The function of the S-box is simply a "substitution" operation.

[0036] It should be noted that there is no limit to the number of times the corresponding data mapping process is performed on each input parameter. The number of mapping processes in non-final rounds can be 2, 3, or other times, and no specific restrictions are imposed here.

[0037] It should be noted that this embodiment performs corresponding data mapping processing on each input parameter, which enables the data processing method to maintain good diffusion and confusion capabilities. That is to say, the classic SPN (substitution-permutation network) structure is used in the design of each branch algorithm, which enables the data processing method to maintain good diffusion and confusion capabilities.

[0038] In one embodiment, during non-final rounds of mapping processing, the output parameters of the S-box processing in the current round of mapping are used as input parameters for bit-position transposition processing, the output parameters of the bit-position transposition processing are used as input parameters for matrix multiplication processing, and the output parameters of the matrix multiplication processing are used as input parameters for the S-box processing in the next round of mapping processing; while during the final round of mapping processing, the output parameters of the matrix multiplication processing in the previous round of mapping are used as input parameters for the S-box processing in the final round of mapping processing, and the output parameters of the S-box processing are used as input parameters for bit-position transposition processing.

[0039] In one embodiment, reference is made to Figure 2 Assuming the input parameter has 128 bits, data copying is performed to obtain multiple input parameters (i.e., input parameters for multiple branches). Each branch's input parameter is split into 32 temporary variables (S-box input parameters for processing S) by half-byte (4 bits) splitting. If the j-th branch's input parameter undergoes two rounds of data mapping, during the non-last round of mapping (i.e., during the first round), the current round's S-box input parameter for processing S is... Where r represents the index of the previous round of data mapping processing, 0 ≤ r < 2, and All are 4 bits, where j represents the label of one of the multiple branches. When r = 0, that is, during the first round of data mapping processing, the input parameters for the S-box processing are... The S-box processing is performed to obtain the output parameters of the S-box processing (i.e., the input parameters for bit-position transposition processing). Then, the output parameters of the S-box processing are subjected to bit-position transposition processing to obtain the output parameters for bit-position transposition processing (i.e., the input parameters for matrix multiplication processing). Finally, matrix multiplication is performed on the output parameters of the bit-position transposition processing (i.e., dividing the output parameters into four parts and multiplying each part by a preset matrix M). C XORing yields the output parameters of the matrix multiplication process, i.e. Next, we will process the output parameters of the matrix multiplication process. Perform the second round of data mapping processing (i.e., the final round of mapping processing).

[0040] In one embodiment, reference is made to Figure 3 In the final round of mapping processing, since the final round of mapping processing does not include matrix multiplication, assuming the output parameters of the matrix multiplication process in the previous round of mapping processing are... right Perform S-box processing to obtain the output parameters of the S-box processing (i.e., the input parameters of the bit-position transposition processing). Then, perform bit-position transposition processing on the output parameters of the S-box processing to obtain the output parameters of the bit-position transposition processing, which is the output variable of the j-th branch. At this point, the two rounds of data mapping processing are complete, where j represents the label of one of the multiple branches, r represents the label of the previous round of data mapping processing, and 0 ≤ r < 2.

[0041] In one embodiment, the S-box processing includes the following steps:

[0042] The input parameters are split to obtain multiple first temporary variables;

[0043] Multiple second temporary variables are obtained based on multiple first temporary variables and a pre-defined substitution table;

[0044] Multiple second temporary variables are integrated to obtain the first substitution variable.

[0045] It should be noted that the default substitution table can be represented in decimal, hexadecimal, or binary form, etc., without any specific restrictions.

[0046] In one embodiment, assuming that the input parameters are copied to obtain J branches of input parameters, and the input parameters of each branch are mapped for R rounds, and the bit length of each input parameter is 128, the 128 bits of the input parameter can be split to obtain 32 first temporary variables. The first temporary variable t can be represented as...

[0047]

[0048] In formula (1), The value is the sum of the values ​​of four consecutive bits in the input parameters. That is, the first temporary variable t is the value obtained by combining the values ​​of four consecutive bits in the input parameters.

[0049] If the same preset substitution table is used to replace each first temporary variable t, then the second temporary variable s can be represented as

[0050]

[0051] In formula (2), Let || represent the values ​​of four consecutive bits, and in formulas (1) and (2), || represents a cascade operation, i represents the bit label and 0≤i<32, j represents the branch label and 0≤j<J, and r represents the label of the previous round of data mapping processing and 0≤r<R.

[0052] It should be noted that J represents the total number of branches of the input parameters obtained by data copying the input parameters, and J can take any value. Similarly, R represents the number of different data mapping processes performed on the first intermediate variable, and R can also take any value, for example, R≥2.5, without specific restrictions here.

[0053] To illustrate the S-box processing process more clearly, a specific example will be provided below.

[0054] Example 1:

[0055] Table 1. Decimal Substitution Table

[0056] x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S(x) 4 0 2 1 6 8 3 13 12 10 14 11 15 9 7 5

[0057] Referring to Table 1, where x represents the first temporary variable and S(x) represents the second temporary variable. Assuming the input parameter is 0xe847d4140d779a657028602bd4c29b16, the input parameter is split into multiple first temporary variables. Specifically, 0xe847d4140d779a657028602bd4c29b16 is split into e, 8, 4, ..., b, 1, 6. These first temporary variables are then converted to decimal, i.e., e, 8, 4, ..., b, 1, 6 are converted to 14, 8, 4, ..., 11, 1, 6 respectively. Then, referring to Table 1, 14, 8, 4, ..., 11, 1, 6 are substituted... We obtain 7, 12, 6, ..., 11, 0, 3, meaning that when x = 14, S(x) = 7; when x = 8, S(x) = 12; ...; when x = 6, S(x) = 3, and so on. Then, we convert 7, 12, 6, ..., 11, 0, 3 into hexadecimal to obtain multiple second temporary variables, namely 7, c, 6, ..., b, 0, 3. After integrating these multiple second temporary variables, the final first substitution variable is 0x7c6d960649ddae38d42c342b96f2ab03.

[0058] Example 2:

[0059] Table 2 Hexadecimal Substitution Table

[0060] x 0 1 2 3 4 5 6 7 8 9 e b c d e f S(x) 4 0 2 1 6 8 3 d c a e b f 9 7 5

[0061] Referring to Table 2, x represents the first temporary variable, and S(x) represents the second temporary variable. Assuming the input parameter is 0xe847d4140d779a657028602bd4c29b16, the input parameter is split into multiple first temporary variables. Specifically, 0xe847d4140d779a657028602bd4c29b16 is split into e, 8, 4, ..., b, 1, 6. Referring to Table 2, these first temporary variables e, 8, 4, ..., b, 1, 6 are replaced. Multiple second temporary variables are obtained, namely 7, c, 6, ..., b, 0, 3. That is, when x = e, S(x) = 7; when x = 8, S(x) = c; ...; when x = 6, S(x) = 3, and so on. Then, the multiple second temporary variables are integrated and processed to finally obtain the first substitution variable 0x7c6d960649ddae38d42c342b96f2ab03.

[0062] In one embodiment, the bit transposition process specifically includes the following steps:

[0063] Based on the preset bit position transposition table and the value of each bit in the first generation transposition variable, the target position corresponding to each bit is obtained.

[0064] The positions of each bit in the first substitution variable are adjusted according to the target position to obtain the second substitution variable.

[0065] In one embodiment, assuming the input parameter has a bit length of 128 and the data mapping process has R rounds, where R represents the number of different data mapping processes performed on the first intermediate variable, if the input parameter is copied to obtain 4 input parameters, then the 4 input parameters can be processed by S-box to obtain 4 first substitution variables. Therefore, based on the first substitution variables and the following formula (3), the value of each bit in the corresponding second substitution variable is calculated. Right now

[0066]

[0067] In formula (3), i represents the bit label, and 0 ≤ i < 128; j represents the branch label, and 0 ≤ j < 4; r represents the label of the previous round of data mapping processing, and 0 ≤ r < R; P b,j [i] represents the label (i.e., the target position) of each bit in the second-generation permutation variable. This represents the value of each bit in the first generation of the permutation variable.

[0068] Specifically, referring to the preset bit position transposition table shown in Table 3, i represents the bit number in the first generation transposition variable, P b,0 [i] represents the bit label of the second-generation permutation variable in the first branch, P b,1 [i] represents the bit label of the second substitution variable in the second branch, P b,2 [i] represents the bit label of the second-generation permutation variable in the third branch, P b,3 [i] represents the bit index of the second substitution variable in the fourth branch, where 0 ≤ i < 127.

[0069] Let the first substitution variable of the first branch be 0x7c6d960649ddae38d42c342b96f2ab03. If i = 0, from Table 3 and Formula (3), we can see that... That is, in the first substitution variable, a bit of 0 corresponds to a bit of 6 at the target position in the preset bit position table. From the first substitution variable, we know that the value of the first eight bits is 01111100. The value of bit 6 in the second substitution variable (i.e....) ) represents the value of the first-generation substitution variable where the bit is 0 (i.e. ), and so on, so the result after the substitution is 01111100. After the above steps are performed 128 times, the second generation substitution variable is finally obtained as 0x35c4f873b69f8e222aeba00d792c818f. This embodiment does not impose specific limitations on this.

[0070] Table 3 Preset Bit Position Transformation Table

[0071]

[0072]

[0073] In another embodiment, the matrix multiplication process specifically includes the following steps:

[0074] The second-generation permutation variable is divided into bits to obtain multiple third temporary variables with the first data length;

[0075] Each third temporary variable is XORed with each row element of the preset matrix to obtain multiple fourth temporary variables. The length of each row element and the length of each column element in the preset matrix are both the first data length.

[0076] Multiple fourth temporary variables are integrated to obtain the third replacement variable.

[0077] In one embodiment, assuming the second substitution variable has a bit length of 128, the second substitution variable is divided into four 32-bit third temporary variables. Based on the third temporary variables and the following formula (4), the value x[i] of each bit in the fourth temporary variable is calculated, i.e.

[0078]

[0079] In formula (4), M b [i][m] is a preset matrix M b The element in the i-th row and m-th column, z[m] is the value of bit m in the third temporary variable, where i represents the bit index, and 0 ≤ i < 32. The preset matrix M... b As shown in Table 4 below.

[0080] Specifically, if the values ​​of each bit in the 32-bit fourth temporary variable are represented as x[0], ..., x

[31] , when i = 0, we have

[0081]

[0082] If the third temporary variable of the first one is 0011 0101 1100 0100 1111 1000 0111 0011, that is, z[0] = 0,

[0083] z[1] = 0, ..., z

[31] = 1. From formula (5), the value of x[0] in the fourth temporary variable with a bit of 0 is:

[0084]

[0085] Table 4 Preset Matrix M b

[0086]

[0087]

[0088] Step S140: Perform data integration processing on multiple output variables to obtain index values.

[0089] In this embodiment, by employing a data processing method including steps S110 to S140, input parameters are first obtained. Then, the input parameters are copied to obtain multiple input parameters. Next, each input parameter is mapped to obtain multiple output variables. Finally, the multiple output variables are integrated to obtain an index value. That is, the input parameters are copied to obtain multiple input parameters, and the multiple input parameters are mapped in parallel to obtain a mixture of multiple output variables. This design structure reduces the critical path delay of the full-lay circuit. Therefore, by mixing multiple output variables, the number of algorithm rounds required to ensure the independence of output bits is effectively reduced, thereby reducing algorithm delay. Moreover, since the correlation between different output variables obtained by corresponding data mapping of each input parameter is low, the bits of the index value obtained by integrating multiple output variables have low correlation, thereby reducing the impact on the stability of the optimal fill rate. Therefore, the solution of this embodiment can reduce the correlation between index value bits and reduce the number of algorithm rounds required to ensure the independence of output bits, thereby reducing the impact on the stability of the optimal fill rate and algorithm delay.

[0090] It is worth noting that while custom hash functions, such as MD5 (Message Digest Algorithm 5), are based on MD (Message Digest) structures that can reduce the impact on the stability of the optimal fill rate, they suffer from drawbacks such as long rounds and large group lengths. Therefore, the modulo operation used in this algorithm is not conducive to hardware implementation and also leads to problems such as large hardware area and increased latency. In contrast, this embodiment allows for an unlimited number of data mapping processes for each input parameter, such as 2.5 times, thus reducing the number of data mapping processes. Furthermore, this embodiment performs data compression on the input parameters, shortening the group length. Therefore, compared to hash functions based on multiple MD structures, this embodiment not only reduces algorithm latency but also optimizes the circuit area for algorithm implementation.

[0091] In one embodiment, such as Figure 4 As shown, step S120 will be further explained, which includes, but is not limited to, steps S210 and S220.

[0092] Step S210: Perform data compression processing on the input parameters to obtain compressed input parameters.

[0093] In this step, the input parameters are compressed to obtain compressed input parameters. The bit length of the compressed input parameters is fixed, which is beneficial for supporting variable-length inputs of the algorithm. The compressed input parameters optimize the circuit area for subsequent calculations.

[0094] Step S220: Perform data copying processing on the compressed input parameters.

[0095] In this embodiment, by employing a data processing method including the above steps S210 and S220, the input parameters are first compressed to obtain compressed input parameters, and then the compressed input parameters are copied. Therefore, this embodiment can optimize the circuit area of ​​the algorithm implementation and reduce the algorithm latency.

[0096] In one embodiment, such as Figure 5 As shown, step S210 will be further explained. Step S210 may include, but is not limited to, steps S310 and S320.

[0097] Step S310: When the number of bits of the input parameter is equal to the preset number of bits, perform byte division on the input parameter to obtain multiple parameters to be processed;

[0098] Step S320: Perform an XOR operation on multiple parameters to be processed to obtain the compressed input parameters.

[0099] In this embodiment, by employing the data processing method including the above steps S310 and S320, the number of bits of the input parameter is first determined. When the number of bits of the input parameter is equal to the preset number of bits, the input parameter can be compressed, that is, the input parameter is divided into bytes to obtain multiple parameters to be processed. Then, the multiple parameters to be processed are XORed to obtain the compressed input parameter. Therefore, this embodiment can optimize the circuit area of ​​the algorithm implementation.

[0100] It should be noted that the preset number of bits can be any value, such as 128 bits, 512 bits, 64 bits, 32 bits, or 16 bits, etc., which can be selected according to the actual situation, and no specific restrictions are made here.

[0101] It is understandable that performing byte partitioning on the input parameters involves dividing the input parameters into equal parts.

[0102] In another embodiment, such as Figure 6 As shown, step S210 will be further explained. Step S210 may include, but is not limited to, steps S410, S420 and S430.

[0103] Step S410: When the number of bits in the input parameter is less than the preset number of bits, perform data padding on the input parameter to obtain the padded input parameter.

[0104] It should be noted that data padding of input parameters can be performed by padding the high-order bits of the input parameters with zeros to make the number of bits of the input parameters equal to the preset number of bits, or it can be performed in other ways. No specific restrictions are made here.

[0105] Step S420: Perform byte division on the padded input parameters to obtain multiple parameters to be processed.

[0106] It is understandable that performing byte partitioning on the input parameters involves dividing the input parameters into equal parts.

[0107] Step S430: Perform an XOR operation on multiple parameters to be processed to obtain the compressed input parameters.

[0108] In this embodiment, by employing the data processing method including steps S410 to S430 described above, the number of bits of the input parameter is first determined. When the number of bits of the input parameter is less than the preset number of bits, the input parameter can be padded to obtain the padded input parameter. Then, the padded input parameter is compressed, that is, the input parameter is divided into bytes to obtain multiple parameters to be processed. Then, the multiple parameters to be processed are XORed to obtain the compressed input parameter. Therefore, this embodiment can optimize the circuit area of ​​the algorithm implementation.

[0109] It should be noted that, Figure 5 The illustrated embodiments and Figure 6 The embodiments shown are parallel embodiments and correspond to input parameters of different bit lengths.

[0110] In one embodiment, such as Figure 7 As shown, step S140 will be further explained. Step S140 may include, but is not limited to, steps S510 and S520.

[0111] Step S510: Perform an XOR operation on multiple output variables to obtain the output parameters.

[0112] In this step, since multiple output variables are obtained by simultaneously performing corresponding data mapping processing on each input parameter in step S130, the output parameter obtained by XORing multiple output variables in this step is a mixture of multiple output variables. This design structure ensures that the time consumed by performing different data mapping processing on multiple input parameters simultaneously is not the sum of the time consumed by performing different data mapping processing on all input parameters, but rather the maximum value among the times consumed by performing different data mapping processing on multiple input parameters simultaneously. That is to say, the critical path length of the fully laid circuit is not the sum of the delays of multiple branches, but the maximum delay among multiple branches. At the same time, by mixing the output parameters of multiple branches, the number of algorithm rounds required to ensure the independence of output bits is effectively reduced, thereby reducing the algorithm delay.

[0113] Step S520: Perform data truncation processing based on the output parameters to obtain the index value.

[0114] It should be noted that there are different ways to obtain the index value by truncating the data based on the output parameters. For example, the values ​​of each bit in the output parameters can be arbitrarily truncated. Assuming the output parameter is 11111100, the values ​​of bit 1, bit 3, bit 0, and bit 7 can be truncated in sequence, and the truncated values ​​can be integrated to obtain the index value 0111. Alternatively, assuming the output parameter is 0xf4f91566d9b2d8c34f68ee5d0d20449c, the values ​​of the eighth half-byte, the first half-byte, and the seventh half-byte can be truncated in sequence, and the truncated values ​​can be integrated to obtain the index value 0x6f6. This embodiment does not impose specific limitations on this.

[0115] It should be noted that output parameters and index values ​​can be represented in any form, such as binary, octal, decimal, or hexadecimal, without any specific restrictions.

[0116] It should also be noted that the index value can be of any bit length and can be set according to the actual situation; no specific restrictions are imposed here.

[0117] The data processing method provided in the above embodiments will be described in detail below with specific examples:

[0118] In one embodiment, reference is made to Figure 8 Assuming the preset bit depth is 512, if the input parameter has 145 bits, then the input parameter needs to be padded with data, such as padding the high-order bits with zeros, until the input parameter has 512 bits. If the input parameter already has 512 bits, then no padding is needed. The input parameter is represented as... The input parameters are then divided into byte segments of 16 bytes (128 bits) to obtain four parameters to be processed. Then, based on the four parameters to be processed and the following formula (6), the input parameter X used to obtain the compressed result can be calculated, that is:

[0119]

[0120] After calculating the compressed input parameter X according to the above formula (6), X can be copied into four 128-bit input parameters, namely X0, X1, X2, and X3. X0, X1, X2, and X3 are processed through the first branch, the second branch, the third branch, and the fourth branch, respectively. The number of rounds used in each branch is r rounds, where r ≥ 2.5, that is, the minimum number of rounds of r is 2.5 rounds. Finally, four 128-bit output variables C0, C1, C2, and C3 are obtained. Then, the 128-bit output parameter C can be calculated according to the four output variables and the following formula (7), that is:

[0121]

[0122] Specifically, if the input parameter is 0xbabc22665930405d3d0bc0a0b86da94b600b8dff8260db9e4c73f31e4ee84a038ed5fbb6080e132fbd0e5230a5fad04abc25803bde291289bc5e01a587bda814, the input parameter is compressed, which means dividing the input parameter into byte segments to obtain four parameters to be processed, namely ba bc22665930405d3d0bc0a0b86da94b、600b8dff8260db9e4c73f31e4ee84a03、8ed5fbb6080e132fbd0e5230a5fad04a、bc25803bde291289bc5e01a587bda814、According to formula (6), the four parameters to be processed are XORed to obtain the compressed input parameters, as shown in Table 5. Among them, the input parameters of S-box processing are expressed as The input parameters for bit position transposition processing, i.e., the first-order transposition variables, are expressed as follows: The input parameters for matrix multiplication, i.e., the permutation variables of the second substitution, are expressed as follows: Where j represents the branch number, and 0≤j<4, and r represents the round number of the previous round of data mapping processing, and 0≤r<3.

[0123] Table 5 shows the test results used to execute the data processing methods.

[0124]

[0125] Regarding the data processing method provided in the above embodiments, the test results of the forwarding chip executing the data processing method are described in detail below with specific examples, wherein the data processing method is assumed to be the Chime algorithm.

[0126] Test Result 1:

[0127] Table 6. Hardware Comprehensive Evaluation Comparison Results of CRC16 and Chime Algorithms under UMC55nm Library

[0128]

[0129] As shown in Table 6, the output hash value of the CRC16 algorithm has a bit width of 16 bits, while the output hash value of the Chime algorithm has a bit width of 128 bits. When the input parameter is 128 bits, the overall area (GE) of the Chime algorithm is approximately 25 times that of the CRC16 algorithm, and the area per unit output bit (Area / Bit) of the Chime algorithm is approximately 3 times that of the CRC16 algorithm, with delay and frequency (Freq) being comparable. When the input parameter is 512 bits, the overall area (GE) of the Chime algorithm is 5 times that of the CRC16 algorithm, and the area per unit output bit (Area / Bit) of the Chime algorithm is approximately 3 times that of the CRC16 algorithm. The area / bit (GE) is approximately 6 / 10 of the area / bit (GE) per unit output bit of the CRC16 algorithm. The Chime algorithm has a slightly larger latency and a slightly lower frequency, but it is also a suitable algorithm for chip implementation. Here, CRC16_128 represents the CRC16 algorithm with 128-bit input parameters, Chime_128 represents the Chime algorithm with 128-bit input parameters, CRC16_512 represents the CRC16 algorithm with 512-bit input parameters, and Chime_512 represents the Chime algorithm with 512-bit input parameters.

[0130] It should be noted that Area / Bit represents the area per unit output bit. Area / Bit equals Area / output bit width. The output bit width of CRC16 is 16, and the output bit width of Chime is 128. The algorithm area comparison is based on the area per unit output bit, where the area per unit output bit represents the area required to output 1 bit. Test Result 2:

[0131] Table 7. Fill rate test results of MD5 and Chime algorithms under different hash table configurations.

[0132]

[0133] As shown in Table 7, for different sub-table depths and numbers of sub-tables, the mean and standard deviation of the fill rate of the Chime algorithm and the MD5 algorithm are quite similar. Therefore, the Chime algorithm is an algorithm that can meet the chip implementation requirements and ensure the stability of the hash table fill rate.

[0134] In addition, embodiments of the present invention also provide a forwarding chip 200, such as... Figure 9 As shown, the forwarding chip 200 includes, but is not limited to:

[0135] Memory 202 is used to store programs;

[0136] The processor 201 is used to execute the program stored in the memory 202. When the processor 201 executes the program stored in the memory 202, the processor 201 is used to execute the above-mentioned data processing method.

[0137] The processor 201 and the memory 202 can be connected via a bus or other means.

[0138] The memory 202, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs, such as the data processing method described in the embodiments of the present invention. The processor 201 implements the above-described data processing method by running the non-transitory software program and instructions stored in the memory 202.

[0139] The memory 202 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data processing methods used to execute the above-described methods. Furthermore, the memory 202 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 202 may optionally include remotely located memories 202 disposed relative to the processor 201, which can be connected to the processor 201 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0140] The non-transient software program and instructions required to implement the above data processing method are stored in memory 202. When executed by one or more processors 201, the above data processing method is executed, for example, the method described above is executed. Figure 1 Method steps S110 to S150 Figure 4 Method steps S210 and S220, Figure 5 Method steps S310 to S320 Figure 6 Method steps S410 to S430 and Figure 7 The method steps S510 and S520.

[0141] The device or system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] Furthermore, one embodiment of the present invention provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, for example, by a processor in the above-described device embodiment, causing the processor to perform the data processing method described above, for example, performing the above-described... Figure 1 Method steps S110 to S150 Figure 4 Method steps S210 and S220, Figure 5 Method steps S310 to S320 Figure 6 Method steps S410 to S430 and Figure 7 The method steps S510 and S520.

[0143] Furthermore, one embodiment of the present invention also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the data processing method described above, for example, the method described above. Figure 1 Method steps S110 to S150 Figure 4 Method steps S210 and S220, Figure 5 Method steps S310 to S320 Figure 6 Method steps S410 to S430 and Figure 7 The method steps S510 and S520.

[0144] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0145] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A data processing method, comprising: Obtain input parameters, which are used to generate index values ​​to populate the index table; The input parameters are copied to obtain multiple input parameters; Each input parameter is subjected to corresponding data mapping processing to obtain multiple output variables; wherein, the data mapping processing includes non-last round mapping processing and last round mapping processing, the non-last round mapping processing includes S-box processing, bit position transposition processing and matrix multiplication processing, and the last round mapping processing includes the S-box processing and the bit position transposition processing, and the bit position transposition processing in different data mapping processes is different; The index value is obtained by integrating the data of the multiple output variables.

2. The data processing method according to claim 1, characterized in that, The data processing method includes: During the non-last round of mapping processing, the output parameters of the S-box processing in the current round of mapping processing are used as the input parameters of the bit position transposition processing, and the output parameters of the bit position transposition processing are used as the input parameters of the matrix multiplication processing, and the output parameters of the matrix multiplication processing are used as the input parameters of the S-box processing in the next round of mapping processing. In the final round of mapping processing, the output parameters of the matrix multiplication process in the previous round of mapping processing are used as the input parameters of the S-box process in the final round of mapping processing, and the output parameters of the S-box process are used as the input parameters of the bit position transposition process.

3. The data processing method according to claim 1 or 2, characterized in that, The S-box processing includes the following steps: The input parameters are split to obtain multiple first temporary variables; Multiple second temporary variables are obtained based on the multiple first temporary variables and the preset substitution table; The multiple second temporary variables are integrated to obtain the first substitution variable.

4. The data processing method according to claim 3, characterized in that, The bit swapping process includes the following steps: Based on the preset bit position table and the value of each bit in the first substitution variable, the target position corresponding to each bit is obtained. The positions of each bit in the first substitution variable are adjusted according to the target position to obtain the second substitution variable.

5. The data processing method according to claim 4, characterized in that, The matrix multiplication process includes the following steps: The second substitution variable is divided into bits to obtain multiple third temporary variables with a first data length; Each of the third temporary variables is XORed with each row element of the preset matrix to obtain multiple fourth temporary variables, wherein the length of each row element and the length of each column element in the preset matrix are both the first data length. The multiple fourth temporary variables are integrated to obtain the third substitution variable.

6. The data processing method of claim 1, wherein, The data copying process for the input parameters includes: The input parameters are compressed to obtain compressed input parameters; The compressed input parameters are then copied.

7. The data processing method according to claim 6, characterized in that, The step of performing data compression processing on the input parameters to obtain compressed input parameters includes: When the number of bits of the input parameter is equal to the preset number of bits, the input parameter is divided into bytes to obtain multiple parameters to be processed; The multiple parameters to be processed are XORed to obtain the compressed input parameters.

8. The data processing method according to claim 6, characterized in that, The step of performing data compression processing on the input parameters to obtain compressed input parameters includes: When the number of bits in the input parameter is less than the preset number of bits, the input parameter is padded to obtain the padded input parameter. The padded input parameters are divided into bytes to obtain multiple parameters to be processed; The multiple parameters to be processed are XORed to obtain the compressed input parameters.

9. The data processing method of claim 1, wherein, The process of integrating the data from the multiple output variables to obtain the index value includes: The output parameters are obtained by performing an XOR operation on the multiple output variables. The index value is obtained by truncating the data based on the output parameters.

10. A repeater chip, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the computer program, implements the data processing method as described in any one of claims 1 to 9.

11. A computer-readable storage medium storing computer-executable instructions for performing the data processing method according to any one of claims 1 to 9.

12. A computer program product, comprising a computer program or computer instructions, characterized in that, The computer program or the computer instructions are stored in a computer-readable storage medium, and the processor of the computer device reads the computer program or the computer instructions from the computer-readable storage medium. The processor executes the computer program or the computer instructions, causing the computer device to perform the data processing method as described in any one of claims 1 to 9.

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