Driving circuit, driving method and display device

Abstract

The embodiments of the present disclosure disclose a driving circuit, a driving method and a display device. The display device determines the refresh frequency corresponding to each display partition, and then calculates the target gamma voltage corresponding to each display partition according to the refresh frequency corresponding to each display partition and the first reference gamma voltage and the second reference gamma voltage stored in advance, so that the target gamma voltage corresponding to each display partition can be independently set, and the corresponding display partition can be driven to display according to the calculated target gamma voltage, thereby improving the brightness difference when the refresh frequencies of different display partitions are different.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to driving circuits, driving methods and display devices. Background Technology

[0002] The display panel supports dynamic refresh rate display, meaning it can switch between multiple refresh rates, such as 1-120Hz, but currently only the entire screen can switch simultaneously. With technological advancements, solutions have emerged that allow different areas to support different refresh rates. However, when displaying multiple areas at multiple refresh rates, a brightness difference can occur between the refreshed and held-up areas. Summary of the Invention

[0003] This disclosure provides a driving circuit configured to be electrically connected to a display panel.

[0004] The driving circuit is configured to: determine the refresh frequency corresponding to each display partition in the display panel; determine the target gamma voltage corresponding to each display partition based on the refresh frequency corresponding to each display partition and the pre-stored first reference gamma voltage and second reference gamma voltage; drive each display partition to display based on the target gamma voltage corresponding to each display partition; wherein, the display panel includes multiple display partitions, and the refresh frequencies of two adjacent display partitions are different; the first reference gamma voltage and the second reference gamma voltage corresponding to the same gray level are different.

[0005] In some possible implementations, the driving circuit is further configured to: determine a compensation coefficient for each display partition based on the refresh frequency corresponding to each display partition and a pre-stored correspondence between multiple refresh frequencies and multiple compensation coefficients; and determine a target gamma voltage for each display partition based on the compensation coefficient corresponding to each display partition, the first reference gamma voltage, and the second reference gamma voltage.

[0006] In some possible implementations, the compensation coefficient includes: a first sub-compensation coefficient and a second sub-compensation coefficient; the driving circuit is further configured to: determine the target gamma voltage corresponding to each display partition based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each display partition, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each display partition.

[0007] In some possible implementations, the target gamma voltage includes K target gamma sub-voltages, the first reference gamma voltage includes K first reference gamma sub-voltages, and the second reference gamma voltage includes K second reference gamma sub-voltages.

[0008] The driving circuit is further configured to: determine the target gamma voltage corresponding to each display partition using the following formula, based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each display partition, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each display partition;

[0009] GM n _k = a*GA_k + b*GB_k;

[0010] Among them, GM n _k represents the kth target gamma sub-voltage among the target gamma voltages corresponding to the nth display partition, GA_k represents the kth first reference gamma sub-voltage among the first reference gamma voltages, GB_k represents the kth second reference gamma sub-voltage among the second reference gamma voltages, a represents the first sub-compensation coefficient corresponding to the nth display partition, b represents the second sub-compensation coefficient corresponding to the nth display partition, k is an integer, and 1≤k≤K, where K is an integer greater than 0.

[0011] In some possible implementations, for each of the display zones corresponding to the same grayscale, the refresh rate of the display zone is reduced and the target gamma sub-voltage is increased.

[0012] In some possible implementations, for the same gray level, the first reference gamma sub-voltage is less than the second reference gamma sub-voltage.

[0013] This disclosure also provides a method for driving a display panel, including:

[0014] Determine the refresh rate corresponding to each display partition in the display panel; the display panel includes multiple display partitions, and the refresh rates of two adjacent display partitions are different;

[0015] The target gamma voltage for each display partition is determined based on the refresh rate corresponding to each display partition and the pre-stored first reference gamma voltage and second reference gamma voltage; wherein the first reference gamma voltage and the second reference gamma voltage corresponding to the same gray level are different.

[0016] Each display partition is driven to display based on the target gamma voltage corresponding to each display partition.

[0017] In some possible implementations, determining the target gamma voltage for each display partition based on the refresh rate corresponding to each display partition and the pre-stored first and second reference gamma voltages includes:

[0018] The compensation coefficient for each display partition is determined based on the refresh frequency corresponding to each display partition and the pre-stored correspondence between multiple refresh frequencies and multiple compensation coefficients.

[0019] The target gamma voltage for each display partition is determined based on the compensation coefficient corresponding to each display partition, the first reference gamma voltage, and the second reference gamma voltage.

[0020] In some possible implementations, the compensation coefficient includes: a first sub-compensation coefficient and a second sub-compensation coefficient;

[0021] The step of determining the target gamma voltage for each display partition based on the compensation coefficient corresponding to each display partition, the first reference gamma voltage, and the second reference gamma voltage includes:

[0022] Based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each of the display zones, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each of the display zones, the target gamma voltage corresponding to each of the display zones is determined.

[0023] In some possible implementations, the target gamma voltage includes K target gamma sub-voltages, the first reference gamma voltage includes K first reference gamma sub-voltages, and the second reference gamma voltage includes K second reference gamma sub-voltages.

[0024] The target gamma voltage for each display partition is determined using the following formula, based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each display partition, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each display partition.

[0025] GM n _k = a*GA_k + b*GB_k;

[0026] Among them, GM n_k represents the kth target gamma sub-voltage among the target gamma voltages corresponding to the nth display partition, GA_k represents the kth first reference gamma sub-voltage among the first reference gamma voltages, GB_k represents the kth second reference gamma sub-voltage among the second reference gamma voltages, a represents the first sub-compensation coefficient corresponding to the nth display partition, b represents the second sub-compensation coefficient corresponding to the nth display partition, k is an integer, and 1≤k≤K, where K is an integer greater than 0.

[0027] In some possible implementations, for each of the display zones corresponding to the same grayscale, the refresh rate of the display zone is reduced and the target gamma sub-voltage is increased.

[0028] In some possible implementations, for the same gray level, the first reference gamma sub-voltage is less than the second reference gamma sub-voltage.

[0029] In some possible implementations, the method for determining the first reference gamma voltage includes:

[0030] The test display panel is controlled using a first initial gamma voltage and a first refresh frequency; the first refresh frequency is the highest refresh frequency among multiple refresh frequencies supported by the display panel.

[0031] Obtain the first display brightness when the test display panel is displayed;

[0032] Determine whether the first display brightness meets the brightness threshold;

[0033] If so, the first initial gamma voltage is determined as the first reference gamma voltage;

[0034] If not, adjust the first initial gamma voltage, and based on the adjusted first initial gamma voltage and the highest refresh rate, control the test display panel to display and obtain the first display brightness again until the first display brightness meets the brightness threshold.

[0035] In some possible implementations, the method for determining the second reference gamma voltage includes:

[0036] The second initial gamma voltage is used to control the refresh and display of the test display panel.

[0037] Obtain the second display brightness when the test display panel maintains the reference display duration after refreshing;

[0038] Determine whether the second display brightness meets the brightness threshold;

[0039] If so, the second initial gamma voltage is determined as the second reference gamma voltage;

[0040] If not, adjust the second initial gamma voltage, and based on the adjusted second initial gamma voltage, control the test display panel to refresh and display and obtain the second display brightness again until the second display brightness meets the brightness threshold.

[0041] This disclosure also provides a display device, including: a display panel and the aforementioned driving circuit, wherein the driving circuit is electrically connected to the display panel. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of the display device in the embodiments of this disclosure;

[0043] Figure 2 This is a schematic diagram of the pixel circuit structure in an embodiment of this disclosure;

[0044] Figure 3 This is a signal timing diagram of the pixel circuit in an embodiment of this disclosure;

[0045] Figure 4 This is a schematic diagram of the structure of the display panel in an embodiment of this disclosure;

[0046] Figure 5 Here are some flowcharts of the driving method in the embodiments of this disclosure;

[0047] Figure 6 This is a flowchart of a method for determining the first reference gamma voltage in an embodiment of this disclosure;

[0048] Figure 7 This is a flowchart of the method for determining the second reference gamma voltage in an embodiment of this disclosure;

[0049] Figure 8 Here are some further flowcharts of the driving methods in the embodiments of this disclosure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0052] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0053] In some embodiments, such as Figure 1 As shown, the display device may include a display panel 100 and a driving circuit 200. The driving circuit 200 is electrically connected to the display panel 100 and can drive the display panel to operate. Exemplarily, the driving circuit 200 may take the form of an embodiment combining software and hardware aspects. For example, the driving circuit 200 may include an integrated circuit (IC).

[0054] For example, the display panel 100 may include a display area and a non-display area surrounding the display area, the display area including a plurality of pixel units arranged in an array. Optionally, each pixel unit includes multiple sub-pixels of different colors. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0055] The display area also includes multiple grid lines and multiple data lines. A row of subpixels can be connected to one grid line, and a column of subpixels can be connected to one data line. Of course, other connection methods can also be used, which will not be elaborated upon here.

[0056] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) offer advantages such as self-illumination and low energy consumption. In embodiments of this disclosure, each sub-pixel may include a light-emitting device and a pixel circuit connected to the light-emitting device. The pixel circuit can drive the connected light-emitting device to emit light. Exemplarily, the light-emitting device may include at least one of OLEDs, QLEDs, Micro LEDs, and Mini LEDs.

[0057] Typically, a pixel circuit may include transistors and capacitors, which work together to drive a connected light-emitting device to emit light. For example, such as... Figure 2 As shown, the pixel circuit PX may include: a driving transistor M0, a data writing transistor M1, a first reset transistor M2, a second reset transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a third reset transistor M7, and a storage capacitor CST. The cathode of the light-emitting device L is electrically connected to the second power supply terminal VSS.

[0058] For example, the gate of driving transistor M0 is electrically connected to node N1, the first terminal of driving transistor M0 is electrically connected to node N2, and the third terminal of driving transistor M0 is electrically connected to node N3. For example, as Figure 2 As shown, the driving transistor M0 can be configured as a P-type transistor; its first terminal can be its source, and its second terminal can be its drain. Of course, the driving transistor M0 can also be configured as an N-type transistor; this is not a limitation here.

[0059] For example, the gate of the data writing transistor M1 is electrically connected to the first scan signal terminal GA_P (the first scan signal terminal GA_P is connected to the corresponding gate line), the first terminal of the data writing transistor M1 is electrically connected to the data signal terminal DA (the data signal terminal DA is connected to the corresponding data line), and the second terminal of the data writing transistor M1 is electrically connected to node N2. For example, the data writing transistor M1 is turned on under the control of the level of the valid pulse of the first scan signal at the first scan signal terminal GA_P, and turned off under the control of the invalid level of the first scan signal. Optionally, as... Figure 2As shown, the data writing transistor M1 can be configured as a P-type transistor, in which case the level of the valid pulse of the first scan signal is low and the level of the invalid pulse is high. Alternatively, the data writing transistor can be configured as an N-type transistor, in which case the level of the valid pulse of the first scan signal is high and the level of the invalid pulse is low.

[0060] Exemplarily, the gate of the first reset transistor M2 is electrically connected to the first reset signal terminal RE_N, the first terminal of the first reset transistor M2 is electrically connected to the first initialization signal terminal VINIT1, and the second terminal of the first reset transistor M2 is electrically connected to node N1. Exemplarily, the first reset transistor M2 is turned on under the control of the level of the valid pulse of the first reset signal at the first reset signal terminal RE_N, and turned off under the control of the invalid level of the first reset signal. Optionally, as... Figure 2 As shown, the first reset transistor M2 can be configured as an N-type transistor, in which case the effective pulse level of the first reset signal is high and the invalid pulse level is low. Alternatively, the first reset transistor can be configured as a P-type transistor, in which case the effective pulse level of the first reset signal is low and the invalid pulse level is high.

[0061] Exemplarily, the gate of the second reset transistor M3 is electrically connected to the second reset signal terminal RE_P, the first terminal of the second reset transistor M3 is electrically connected to the second initialization signal terminal VINIT2, and the second terminal of the second reset transistor M3 is electrically connected to the anode of the light-emitting device L. Exemplarily, the second reset transistor M3 is turned on under the control of the effective pulse level of the second reset signal at the second reset signal terminal RE_P, and turned off under the control of the ineffective level of the second reset signal. Optionally, as... Figure 2 As shown, the second reset transistor M3 can be configured as a P-type transistor, in which case the effective pulse level of the second reset signal is low, and the invalid pulse level is high. Alternatively, the second reset transistor can be configured as an N-type transistor, in which case the effective pulse level of the second reset signal is high, and the invalid pulse level is low.

[0062] Exemplarily, the gate of the third reset transistor M7 is electrically connected to the second reset signal terminal RE_P, the first terminal of the third reset transistor M7 is electrically connected to the third initialization signal terminal VINIT3, and the second terminal of the third reset transistor M7 is electrically connected to node N2. Exemplarily, the third reset transistor M7 is turned on under the control of the effective pulse level of the second reset signal at the second reset signal terminal RE_P, and turned off under the control of the ineffective level of the second reset signal. Optionally, as... Figure 2As shown, the third reset transistor M7 can be configured as a P-type transistor, in which case the effective pulse level of the second reset signal is low, and the ineffective pulse level is high. Alternatively, the third reset transistor can be configured as an N-type transistor, in which case the effective pulse level of the second reset signal is high, and the ineffective pulse level is low.

[0063] Exemplarily, the gate of the threshold compensation transistor M4 is electrically connected to the second scan signal terminal GA_N, the first terminal of the threshold compensation transistor M4 is electrically connected to node N1, and the second terminal of the threshold compensation transistor M4 is electrically connected to node N3. Exemplarily, the threshold compensation transistor M4 is turned on under the control of the level of the effective pulse of the second scan signal at the second scan signal terminal GA_N, and turned off under the control of the ineffective level of the second scan signal. Optionally, as... Figure 2 As shown, the threshold compensation transistor M4 can be set as an N-type transistor, in which case the level of the valid pulse of the second scan signal is high and the level of the invalid pulse is low. Alternatively, the threshold compensation transistor can be set as a P-type transistor, in which case the level of the valid pulse of the second scan signal is low and the level of the invalid pulse is high.

[0064] Exemplarily, the gate of the first light-emitting control transistor M5 is electrically connected to the light-emitting control signal terminal EM, the first terminal of the first light-emitting control transistor M5 is electrically connected to the first power supply terminal VDD, and the second terminal of the first light-emitting control transistor M5 is electrically connected to node N2. Exemplarily, the first light-emitting control transistor M5 is turned on under the control of the effective pulse level of the light-emitting control signal at the light-emitting control signal terminal EM, and turned off under the control of the ineffective pulse level of the light-emitting control signal. Optionally, as... Figure 2 As shown, the first light-emitting control transistor M5 can be configured as a P-type transistor, in which case the effective pulse level of the light-emitting control signal is low, and the invalid level is high. Alternatively, the first light-emitting control transistor can be configured as an N-type transistor, in which case the effective pulse level of the light-emitting control signal is high, and the invalid level is low.

[0065] Exemplarily, the gate of the second light-emitting control transistor M6 is electrically connected to the light-emitting control signal terminal EM, the first terminal of the second light-emitting control transistor M6 is electrically connected to node N3, and the second terminal of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting device L. Exemplarily, the second light-emitting control transistor M6 is turned on under the control of the effective pulse level of the light-emitting control signal at the light-emitting control signal terminal EM, and turned off under the control of the ineffective pulse level of the light-emitting control signal. Optionally, as... Figure 2 As shown, the second light-emitting control transistor M6 can be configured as a P-type transistor, in which case the effective pulse level of the light-emitting control signal is low, and the ineffective level is high. Alternatively, the second light-emitting control transistor can be configured as an N-type transistor, in which case the effective pulse level of the light-emitting control signal is high, and the ineffective level is low.

[0066] The first electrode plate of the storage capacitor CST is electrically connected to node N1, and the second electrode plate of the storage capacitor CST is electrically connected to the first power supply terminal VDD.

[0067] In some embodiments of this disclosure, the first power supply terminal VDD can be configured to apply a constant first power supply voltage, which is generally positive. Similarly, the second power supply terminal VSS can apply a constant second power supply voltage, which is generally ground voltage or negative. In practical applications, the specific values ​​of the first and second power supply voltages can be designed and determined according to the actual application environment, and are not limited herein.

[0068] In some embodiments of this disclosure, the first terminal of the transistor can be used as its source and the second terminal as its drain, depending on the type of transistor and the signal of its gate; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0069] Transistors using low-temperature poly-silicon (LTPS) as the active layer generally offer advantages such as high mobility, thinner and smaller design, and lower power consumption. In practical implementation, the active layer material of each of the following transistors—driving transistor M0, data writing transistor M1, second reset transistor M3, first light-emitting control transistor M5, second light-emitting control transistor M6, and third reset transistor M7—can be set to LTPS. This allows the aforementioned transistors to be configured as LTPS transistors, enabling the pixel circuit to achieve high mobility, thinner and smaller design, and lower power consumption.

[0070] Transistors that typically use metal-oxide-semiconductor (MODS) materials as their active layers generally have lower leakage current. Therefore, to reduce leakage current, in some embodiments of this disclosure, the active layer material of each of the first reset transistor M2 and the threshold compensation transistor M4 can be set to a MODS material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials can also be used, and this is not limited here. This allows the transistors to be configured as oxide thin-film transistors, thereby reducing the leakage current of the pixel circuit.

[0071] This embodiment of the disclosure uses some transistors as LTPS type transistors and some transistors as oxide type transistors, which enables the pixel circuit in this embodiment to be configured as an LTPO type pixel circuit. By combining the two transistor fabrication processes of LTPS type transistors and oxide type transistors to fabricate the LTPO pixel circuit of low-temperature polycrystalline silicon oxide, the leakage current of the driving transistor gate can be reduced, and the power consumption can be lowered.

[0072] The above are merely examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this disclosure and are not specifically limited here.

[0073] In some examples, Figure 2 The structure of the pixel circuit shown, and the corresponding signal timing diagram, are as follows: Figure 3 As shown. In Figure 3 In this context, em represents the light-emitting control signal applied to the light-emitting control signal terminal EM, re_p represents the second reset signal applied to the second reset signal terminal RE_P, ga_p represents the first scan signal applied to the first scan signal terminal GA_P, ga_n represents the second scan signal applied to the second scan signal terminal GA_N, and re_n represents the first reset signal applied to the first reset signal terminal RE_N. Furthermore, Figure 2 Combination Figure 3 The working process is basically the same as that in existing technologies, and will not be elaborated here. It should be noted that... Figure 3 For illustrative purposes only, in practical applications, the signal timing diagram corresponding to the pixel circuit provided in this disclosure embodiment may be other forms of signal timing diagram, and no limitations are made here.

[0074] In practical applications, display panels can operate at multiple refresh rates, such as 60Hz, 90Hz, and 120Hz. Furthermore, with technological advancements, solutions have emerged that allow different areas to support different refresh rates. For example, such as... Figure 4As shown, the display panel 100 also includes a gate driving circuit and a gating circuit. The gate driving circuit includes multiple cascaded shift registers 10, and the gating circuit includes multiple gating control circuits 20. Each shift register 10 is correspondingly configured with one gating control circuit 20 and one gate line (corresponding to the first scan signal terminal of the pixel circuit). The output terminal of the shift register 10 is connected to the corresponding gate line through the corresponding gating control circuit 20. The gating control circuit 20 receives the control of the gating control signal GE to turn on and off. Specifically, the driving circuit 200 inputs a frame start signal STV to the shift register 10, triggering the shift register 10 to work, causing each shift register 10 to sequentially output the first scan signal.

[0075] For example, when the gating control signal GE is at the first level, the gating control circuit 20 is turned on, allowing the first scan signal output from the shift register to be input onto the gate line. When the gating control signal GE is at the second level, the gating control circuit 20 is turned off, preventing the first scan signal output from the shift register from being input onto the gate line. Optionally, the first level can be high and the second level can be low. Alternatively, the second level can be high and the first level can be low.

[0076] In practical implementation, the driving circuit 200 determines the multiple display zones included in the display panel and the corresponding refresh rates of these display zones based on the display data, and the refresh rates of adjacent display zones are different. For example, Figure 4 As shown, the display area AA is divided into three display partitions: aa1, aa2, and aa3. If the refresh rate of display partition aa1 is 120Hz, the refresh rate of display partition aa2 is 60Hz, and the refresh rate of display partition aa3 is 120Hz, then the drive circuit 200 generates a gating control signal GE. When all display partitions aa1 to aa3 are in a refresh frame, the gating control signal GE is at the first level, and the first scan signal output by the shift register is input to the gate lines in display partitions aa1 to aa3, thereby performing data refresh.

[0077] When display partitions aa1 and aa3 are in a refresh frame and display partition aa2 is in a hold frame, the strobe control signal GE includes a first level corresponding to display partitions aa1 and aa3 and a second level corresponding to display partition aa2. The second level corresponding to display partition aa2 is located between the first level of display partition aa1 and the first level of display partition aa3. This allows the first scan signal output by the shift register to be input to the grid lines in display partitions aa1 and aa3, thereby refreshing the data in display partitions aa1 and aa3. However, the first scan signal output by the shift register cannot be input to the grid lines in display partition aa2, thereby allowing display partition aa2 to hold the data.

[0078] However, when the display area has multiple display zones and adjacent display zones have different refresh rates, a brightness difference will exist between the refresh area and the hold area. When there are many display zones (e.g., more than 3 display zones), and each display zone has a different refresh rate, this brightness difference between different display zones will be very noticeable.

[0079] Therefore, the driving circuit provided in this embodiment determines the refresh frequency corresponding to each display partition, and then calculates the target gamma voltage corresponding to each display partition based on the refresh frequency corresponding to each display partition and the pre-stored first reference gamma voltage and second reference gamma voltage. This enables the target gamma voltage corresponding to each display partition to be set independently, thereby driving the corresponding display partition to display according to the calculated target gamma voltage, and thus improving the brightness difference when different display partitions have different refresh frequencies.

[0080] The driving circuit provided in this embodiment can execute the following driving methods, such as... Figure 5 As shown, the driving method may include the following steps:

[0081] S100. Determine the refresh rate corresponding to each display zone in the display panel. The display panel includes multiple display zones, and adjacent display zones have different refresh rates.

[0082] For example, the driving circuit 200 can receive display data and thereby determine the display zones included in the display panel and the refresh rates corresponding to these display zones based on the display data, wherein the refresh rates of two adjacent display zones are different.

[0083] S200: Based on the refresh rate corresponding to each display zone and the pre-stored first and second reference gamma voltages, determine the target gamma voltage for each display zone. The first and second reference gamma voltages for the same grayscale level are different. This setting allows for independent setting of the target gamma voltage for each display zone.

[0084] For example, the first reference gamma voltage may include K first reference gamma sub-voltages: GA_1 to GA_K. These K first reference gamma sub-voltages GA_1 to GA_K are the same as the total number of gray levels supported by the display panel. Furthermore, these K first reference gamma sub-voltages GA_1 to GA_K are configured to correspond one-to-one with each gray level. For example, if the display panel supports 256 gray levels, then K = 256, and these K first reference gamma sub-voltages GA_1 to GA_K correspond one-to-one with gray levels 0 to 255.

[0085] Exemplarily, the second reference gamma voltage may include: K second reference gamma sub-voltages: GB_1 to GB_K. The K second reference gamma sub-voltages GB_1 to GB_K are the same as the total number of gray levels supported by the display panel. Moreover, the K second reference gamma sub-voltages GB_1 to GB_K are set in one-to-one correspondence with the gray levels. For example, if the display panel supports 256 gray levels, then K = 256, and the K second reference gamma sub-voltages GB_1 to GB_K are in one-to-one correspondence with the gray levels from 0 to 255.

[0086] Therefore, the target gamma voltage obtained based on the first reference gamma voltage and the second reference gamma voltage includes: K target gamma sub-voltages, and the K target gamma sub-voltages are also set in one-to-one correspondence with the gray levels. For example, if the display panel supports 256 gray levels, then K = 256, and the K target gamma sub-voltages are in one-to-one correspondence with the gray levels from 0 to 255.

[0087] Among them, for the first reference gamma sub-voltage and the second reference gamma sub-voltage corresponding to the same gray level, the first reference gamma sub-voltage can be made less than the second reference gamma sub-voltage. For example, for the first reference gamma sub-voltage GA_1 and the second reference gamma sub-voltage GB_1 corresponding to the 0 gray level, GA_1 < GB_1 can be made.... For the first reference gamma sub-voltage GA_K and the second reference gamma sub-voltage GB_K corresponding to the 255 gray level, GA_K < GB_K can be made.

[0088] Optionally, the first reference gamma voltage and the second reference gamma voltage can be pre-stored in the driving circuit 200, and when performing step S200, the first reference gamma voltage and the second reference gamma voltage can be directly called.

[0089] Exemplarily, the first reference gamma voltage can be obtained through multiple gamma calibrations before the product leaves the factory. Exemplarily, the method for determining the first reference gamma voltage, as Figure 6 shown, may include the following steps:

[0090] S11. Control the test display panel to display by using the first initial gamma voltage and the first refresh frequency; the first refresh frequency is the highest refresh frequency among the multiple refresh frequencies supported by the display panel. That is, drive the display panel to display by using the highest refresh frequency and the first initial gamma voltage.

[0091] S12. Obtain the first display brightness when the test display panel is displaying.

[0092] S13. Determine whether the first display brightness meets the brightness threshold. Among them, if so, execute step S14, if not, execute step S15. It should be noted that the brightness threshold can be an empirical value or a value set according to the brightness requirement, which is not limited here.

[0093] S14. Determine the first initial gamma voltage as the first reference gamma voltage.

[0094] S15. Adjust the first initial gamma voltage, and based on the adjusted first initial gamma voltage and the highest refresh rate, control the test display panel to display and obtain the first display brightness again until the first display brightness meets the brightness threshold.

[0095] For example, the second reference gamma voltage can also be obtained through multiple gamma adjustments before the product leaves the factory. For example, the method for determining the second reference gamma voltage is as follows: Figure 7 As shown, it may include the following steps:

[0096] S21. Using a second initial gamma voltage, control the refresh and display of the test display panel. For example, control the test display panel to refresh once, then keep the test display panel stationary for a reference time. During this reference time, do not refresh the test display panel, but keep it displaying. During this period, the brightness of the test display panel will decrease. After the reference time, the brightness of the test display panel can be considered to have stabilized. It should be noted that the reference time can be an empirical value or a value set as needed, and is not limited here.

[0097] S22. Obtain the second display brightness when the test display panel maintains the reference display duration after refreshing.

[0098] S23. Determine whether the brightness of the second display meets the brightness threshold. If yes, proceed to step S24; otherwise, proceed to step S25. It should be noted that the brightness threshold can be an empirical value or a value set according to the brightness requirements, and is not limited here.

[0099] S24. Determine the second initial gamma voltage as the second reference gamma voltage.

[0100] S25. Adjust the second initial gamma voltage, and based on the adjusted second initial gamma voltage, control the test display panel to refresh and display and obtain the second display brightness again until the second display brightness meets the brightness threshold.

[0101] S300: Drive each display partition to display based on the target gamma voltage corresponding to each display partition. For example, the driving circuit 200 can generate a data voltage based on the grayscale and target gamma voltage in the display data, and input this data voltage onto the data line. When the first scan signal is applied to the gate line in the display partition, the data voltage on the data line can be written into node N2 of the pixel circuit.

[0102] In some embodiments of this disclosure, such as Figure 8As shown, step S200, determining the target gamma voltage for each display partition based on the refresh rate corresponding to each display partition and the pre-stored first and second reference gamma voltages, may include the following steps:

[0103] S210. Determine the compensation coefficient for each display partition based on the refresh rate corresponding to each display partition and the pre-stored correspondence between multiple refresh rates and multiple compensation coefficients. For example, Q refresh rates f1 to f2 are pre-stored. Q With Q compensation coefficients x1 to x Q The correspondence between them, for example, refresh rate f1 to refresh rate f Q The refresh rates decrease sequentially, with refresh rate f1 corresponding to compensation coefficient x1, refresh rate f2 corresponding to compensation coefficient x2, refresh rate f3 corresponding to compensation coefficient x3, and so on. Q-1 With compensation coefficient x Q-1 Correspondingly, the refresh rate f Q With compensation coefficient x Q Correspondingly, Q is an integer greater than 1. Based on this, combined with Figure 4 If display partition aa1 corresponds to refresh rate f1, then the corresponding compensation coefficient x1 can be determined. If display partition aa2 corresponds to refresh rate f2, then the corresponding compensation coefficient x2 can be determined. If display partition aa3 corresponds to refresh rate f3, then the corresponding compensation coefficient x3 can be determined. Alternatively, if display partition aa1 corresponds to refresh rate f1, then the corresponding compensation coefficient x1 can be determined. If display partition aa2 corresponds to refresh rate f3, then the corresponding compensation coefficient x3 can be determined. If display partition aa3 corresponds to refresh rate f1, then the corresponding compensation coefficient x1 can be determined.

[0104] S220. Determine the target gamma voltage for each display partition based on the compensation coefficient, the first reference gamma voltage, and the second reference gamma voltage for each display partition.

[0105] For example, the compensation coefficients can include: a first sub-compensation coefficient and a second sub-compensation coefficient, wherein the first sub-compensation coefficient can correspond to a first reference gamma voltage, and the second sub-compensation coefficient can correspond to a second reference gamma voltage. That is, compensation coefficient x1 can include a first sub-compensation coefficient ax1 and a second sub-compensation coefficient bx1, compensation coefficient x2 can include a first sub-compensation coefficient ax2 and a second sub-compensation coefficient bx2, compensation coefficient x3 can include a first sub-compensation coefficient ax3 and a second sub-compensation coefficient bx3, ..., compensation coefficient x... Q-1 Including the first sub-compensation coefficient ax Q-1 Second sub-compensation coefficient bxQ-1 Compensation coefficient x Q Including the first sub-compensation coefficient ax Q Second sub-compensation coefficient bx Q .

[0106] It should be noted that the first sub-compensation coefficients ax1 to ax2 can be made. Q All are different, and the second sub-compensation coefficients bx1~bx are made different. Q These values ​​are all different, which allows the target gamma voltages for display zones corresponding to different refresh rates to be different. Alternatively, the first sub-compensation coefficients ax1 to ax2 can also be made different. Q Some parts are the same, some parts are different, the second sub-compensation coefficients bx1~bx Q The brightness of the display zones corresponding to two refresh rates can be partially the same and partially different. For example, when the difference between two refresh rates is less than or equal to a threshold value, the brightness difference is not significant. Therefore, the first sub-compensation coefficients and corresponding second sub-compensation coefficients for these two refresh rates can be the same, resulting in the same target gamma voltage for the display zones. Conversely, when the difference between two refresh rates is greater than the threshold value, the brightness difference is more significant. Therefore, the first sub-compensation coefficients and corresponding second sub-compensation coefficients for these two refresh rates can be set differently, resulting in different target gamma voltages for the display zones, allowing for flexible control. For example, the threshold value can be an empirical value, such as 1, 3, or 5, and is not limited here.

[0107] Based on this, step S220: determining the target gamma voltage corresponding to each display partition may include: determining the target gamma voltage corresponding to each display partition according to the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each display partition, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each display partition. For example, using formula GM n _k = a*GA_k + b*GB_k, determining the target gamma voltage for each display partition. Where GM... n _k represents the kth target gamma sub-voltage among the target gamma voltages corresponding to the nth display partition, GA_k represents the kth first reference gamma sub-voltage among the first reference gamma voltages, GB_k represents the kth second reference gamma sub-voltage among the second reference gamma voltages, a represents the first sub-compensation coefficient corresponding to the nth display partition, b represents the second sub-compensation coefficient corresponding to the nth display partition, k is an integer, and 1≤k≤K.

[0108] For example, combined Figure 4As shown, if display partition aa1 corresponds to refresh frequency f1, then the first sub-compensation coefficient ax1 and the second sub-compensation coefficient bx1 corresponding to display partition aa1 can be determined. The target gamma voltage corresponding to display partition aa1 is: GM1_k = ax1*GA_k + bx1*GB_k. If display partition aa2 corresponds to refresh frequency f2, then the first sub-compensation coefficient ax2 and the second sub-compensation coefficient bx2 corresponding to display partition aa2 can be determined. The target gamma voltage corresponding to display partition aa2 is: GM2_k = ax2*GA_k + bx2*GB_k. If display partition aa3 corresponds to refresh frequency f3, then the first sub-compensation coefficient ax3 and the second sub-compensation coefficient bx3 corresponding to display partition aa3 can be determined. The target gamma voltage corresponding to display partition aa3 is: GM3_k = ax3*GA_k + bx3*GB_k.

[0109] For example, combined Figure 4 As shown, if display partition aa1 corresponds to refresh frequency f1, then the first sub-compensation coefficient ax1 and the second sub-compensation coefficient bx1 corresponding to display partition aa1 can be determined. The target gamma voltage corresponding to display partition aa1 is: GM1_k = ax1*GA_k + bx1*GB_k. If display partition aa2 corresponds to refresh frequency f3, then the first sub-compensation coefficient ax3 and the second sub-compensation coefficient bx3 corresponding to display partition aa2 can be determined. The target gamma voltage corresponding to display partition aa2 is: GM2_k = ax3*GA_k + bx3*GB_k. If display partition aa3 corresponds to refresh frequency f1, then the first sub-compensation coefficient ax1 and the second sub-compensation coefficient bx1 corresponding to display partition aa3 can be determined. The target gamma voltage corresponding to display partition aa3 is: GM3_k = ax1*GA_k + bx1*GB_k.

[0110] For example, for each display partition corresponding to the same gray level, the refresh rate of the display partition can be reduced, and the target gamma sub-voltage can be increased. For instance, if display partition aa1 corresponds to refresh rate f1, display partition aa2 corresponds to refresh rate f2, and display partition aa3 corresponds to refresh rate f3, and f1>f2>f3, and the target gamma sub-voltages GM1_k, GM2_k, and GM3_k of display partition aa1, aa2, and aa3 correspond to the same gray level, then GM1_k... <GM2_k<GM3_k。

[0111] The present disclosure will now be described in detail with reference to specific embodiments. It should be noted that these embodiments are provided for better explanation of the present disclosure and do not limit its scope. Figure 4As shown, the driving circuit 200 divides the display area into three display partitions aa1 to aa3 based on the display data, and determines the refresh frequency f1 corresponding to display partition aa1, the refresh frequency f2 corresponding to display partition aa2, and the refresh frequency f3 corresponding to display partition aa3. Then, based on the pre-stored correspondence between multiple refresh frequencies and multiple compensation coefficients, it determines the first sub-compensation coefficient ax1 and the second sub-compensation coefficient bx1 corresponding to display partition aa1, the first sub-compensation coefficient ax2 and the second sub-compensation coefficient bx2 corresponding to display partition aa2, and the first sub-compensation coefficient ax3 and the second sub-compensation coefficient bx3 corresponding to display partition aa3. Then, according to the formula GM1_k = ax1 * GA_k + bx1 * GB_k, each target gamma sub-voltage in the target gamma voltage corresponding to display partition aa1 is obtained. Similarly, according to the formula GM2_k = ax2 * GA_k + bx2 * GB_k, each target gamma sub-voltage in the target gamma voltage corresponding to display partition aa2 is obtained. According to the formula GM3_k = ax3*GA_k + bx3*GB_k, each target gamma sub-voltage in the target gamma voltage corresponding to display partition aa3 is obtained. Then, based on the grayscale in the display data and the target gamma sub-voltage GM1_k, the data voltage corresponding to display partition aa1 is generated and input to the data line. When the first scan signal is applied to the gate line in display partition aa1, the data voltage on the data line can be written into node N2 of the pixel circuit in display partition aa1. Similarly, based on the grayscale in the display data and the target gamma sub-voltage GM2_k, the data voltage corresponding to display partition aa2 is generated and input to the data line. When the first scan signal is applied to the gate line in display partition aa2, the data voltage on the data line can be written into node N2 of the pixel circuit in display partition aa2. Furthermore, based on the grayscale and target gamma sub-voltage GM2_k in the display data, a data voltage corresponding to the display partition aa2 is generated, and the data voltage is input into the data line. When the first scan signal is loaded on the gate line in the display partition aa2, the data voltage on the data line can be written into node N2 in the pixel circuit of the display partition aa2.

[0112] Based on the same disclosed concept, embodiments of this disclosure also provide a driving circuit, which is configured as follows:

[0113] Determine the refresh rate for each display zone in the display panel; the display panel includes multiple display zones, and the refresh rates of two adjacent display zones are different.

[0114] The target gamma voltage for each display partition is determined based on the refresh rate corresponding to each display partition and the pre-stored first reference gamma voltage and second reference gamma voltage; wherein the first reference gamma voltage and the second reference gamma voltage corresponding to the same gray level are different.

[0115] The display for each display zone is determined based on the target gamma voltage corresponding to each display zone.

[0116] It should be noted that the working principle and specific implementation method of this driving circuit are the same as those of the driving method in the above embodiments. Therefore, the working method of this driving circuit can be implemented by referring to the specific implementation method of the driving method in the above embodiments, and will not be repeated here.

[0117] Based on the same disclosed concept, this disclosure also provides a display device, including the display panel and driving circuit described above. The principle by which this display device solves the problem is similar to that of the aforementioned driving circuit; therefore, the implementation of this display device can refer to the implementation of the aforementioned driving circuit, and the repetitions will not be repeated here.

[0118] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0119] This disclosure provides a driving circuit, driving method, and display device. By determining the refresh frequency corresponding to each display partition, and then calculating the target gamma voltage corresponding to each display partition based on the refresh frequency corresponding to each display partition and the pre-stored first reference gamma voltage and second reference gamma voltage, the target gamma voltage corresponding to each display partition can be set independently. Thus, the corresponding display partition can be driven to display according to the calculated target gamma voltage, thereby improving the brightness difference when different display partitions have different refresh frequencies.

[0120] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0121] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0122] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0123] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0124] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0125] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A driving circuit, characterized in that, The driving circuit is configured to be electrically connected to the display panel; The driving circuit is configured to: determine the refresh frequency corresponding to each display partition in the display panel; determine the target gamma voltage corresponding to each display partition based on the refresh frequency corresponding to each display partition and a pre-stored first reference gamma voltage and a second reference gamma voltage; and drive each display partition to display based on the target gamma voltage corresponding to each display partition; wherein the display panel includes multiple display partitions, and the refresh frequencies of two adjacent display partitions are different; the first reference gamma voltage and the second reference gamma voltage corresponding to the same grayscale are different; The driving circuit is further configured to: determine the compensation coefficient corresponding to each display partition based on the refresh frequency corresponding to each display partition and the pre-stored correspondence between multiple refresh frequencies and multiple compensation coefficients; and determine the target gamma voltage corresponding to each display partition based on the compensation coefficient corresponding to each display partition, the first reference gamma voltage, and the second reference gamma voltage. The compensation coefficient includes a first sub-compensation coefficient and a second sub-compensation coefficient; the driving circuit is further configured to: determine the target gamma voltage corresponding to each display partition based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each display partition, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each display partition. The target gamma voltage includes K target gamma sub-voltages, the first reference gamma voltage includes K first reference gamma sub-voltages, and the second reference gamma voltage includes K second reference gamma sub-voltages. The driving circuit is further configured to: determine the target gamma voltage corresponding to each display partition using the following formula, based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each display partition, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each display partition; GM n _k=a GA_k+b GB_k; Among them, GM n _k represents the kth target gamma sub-voltage among the target gamma voltages corresponding to the nth display partition, GA_k represents the kth first reference gamma sub-voltage among the first reference gamma voltages, GB_k represents the kth second reference gamma sub-voltage among the second reference gamma voltages, a represents the first sub-compensation coefficient corresponding to the nth display partition, b represents the second sub-compensation coefficient corresponding to the nth display partition, k is an integer, and 1≤k≤K, where K is an integer greater than 0.

2. The driving circuit as described in claim 1, characterized in that, For each display partition corresponding to the same gray level, the refresh rate of the display partition decreases, and the target gamma sub-voltage increases.

3. The driving circuit as described in claim 1, characterized in that, For the first reference gamma sub-voltage and the second reference gamma sub-voltage corresponding to the same gray level, the first reference gamma sub-voltage is smaller than the second reference gamma voltage.

4. A driving method for a display panel, characterized in that, include: Determine the refresh rate corresponding to each display partition in the display panel; the display panel includes multiple display partitions, and the refresh rates of two adjacent display partitions are different; The target gamma voltage for each display partition is determined based on the refresh rate corresponding to each display partition and the pre-stored first reference gamma voltage and second reference gamma voltage; wherein the first reference gamma voltage and the second reference gamma voltage corresponding to the same gray level are different. Drive each display partition to display according to the target gamma voltage corresponding to each display partition; The step of determining the target gamma voltage for each display partition based on the refresh rate corresponding to each display partition and the pre-stored first and second reference gamma voltages includes: The compensation coefficient for each display partition is determined based on the refresh frequency corresponding to each display partition and the pre-stored correspondence between multiple refresh frequencies and multiple compensation coefficients. The target gamma voltage for each display partition is determined based on the compensation coefficient corresponding to each display partition, the first reference gamma voltage, and the second reference gamma voltage. The compensation coefficient includes: a first sub-compensation coefficient and a second sub-compensation coefficient; The step of determining the target gamma voltage for each display partition based on the compensation coefficient corresponding to each display partition, the first reference gamma voltage, and the second reference gamma voltage includes: Based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each of the display zones, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each of the display zones, the target gamma voltage corresponding to each of the display zones is determined. The target gamma voltage includes K target gamma sub-voltages, the first reference gamma voltage includes K first reference gamma sub-voltages, and the second reference gamma voltage includes K second reference gamma sub-voltages. The target gamma voltage for each display partition is determined using the following formula, based on the relationship between the first reference gamma voltage and the first sub-compensation coefficient corresponding to each display partition, and the relationship between the second reference gamma voltage and the second sub-compensation coefficient corresponding to each display partition. GM n _k=a GA_k+b GB_k; Among them, GM n _k represents the kth target gamma sub-voltage among the target gamma voltages corresponding to the nth display partition, GA_k represents the kth first reference gamma sub-voltage among the first reference gamma voltages, GB_k represents the kth second reference gamma sub-voltage among the second reference gamma voltages, a represents the first sub-compensation coefficient corresponding to the nth display partition, b represents the second sub-compensation coefficient corresponding to the nth display partition, k is an integer, and 1≤k≤K, where K is an integer greater than 0.

5. The driving method for the display panel as described in claim 4, characterized in that, For each display partition corresponding to the same gray level, the refresh rate of the display partition decreases, and the target gamma sub-voltage increases.

6. The driving method for the display panel as described in claim 4, characterized in that, For the first reference gamma sub-voltage and the second reference gamma sub-voltage corresponding to the same gray level, the first reference gamma sub-voltage is smaller than the second reference gamma voltage.

7. The driving method for a display panel as described in any one of claims 4-6, characterized in that, The method for determining the first reference gamma voltage includes: The test display panel is controlled using a first initial gamma voltage and a first refresh frequency; the first refresh frequency is the highest refresh frequency among multiple refresh frequencies supported by the display panel. Obtain the first display brightness when the test display panel is displayed; Determine whether the first display brightness meets the brightness threshold; If so, the first initial gamma voltage is determined as the first reference gamma voltage; If not, adjust the first initial gamma voltage, and based on the adjusted first initial gamma voltage and the highest refresh rate, control the test display panel to display and obtain the first display brightness again until the first display brightness meets the brightness threshold.

8. The driving method for a display panel as described in any one of claims 4-6, characterized in that, The method for determining the second reference gamma voltage includes: The second initial gamma voltage is used to control the refresh and display of the test display panel. Obtain the second display brightness when the test display panel maintains the reference display duration after refreshing; Determine whether the second display brightness meets the brightness threshold; If so, the second initial gamma voltage is determined as the second reference gamma voltage; If not, adjust the second initial gamma voltage, and based on the adjusted second initial gamma voltage, control the test display panel to refresh and display and obtain the second display brightness again until the second display brightness meets the brightness threshold.

9. A display device, characterized in that, include: The display panel and the driving circuit as described in any one of claims 1-3, wherein the driving circuit is electrically connected to the display panel.

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