A server cyclic restart testing device and method

Abstract

The application relates to the technical field of server testing, and particularly provides a server cyclic restart testing device and method.The device comprises a current control device and a controller, the controller is connected to an enable port of the current control device, the current control device switches on and off the power state of the circuit between the server power supply and the mainboard based on the control signal of the controller, and the controller is in communication connection with the server BMC.The application can control the on and off state of the power supply circuit, and the control start and termination can be controlled by the BMC of the tested server.The application does not need to use a fatigue machine and does not need to perform complex network setting when cyclically restarting the server.

Description

Technical Field

[0001] This invention belongs to the field of server testing technology, specifically relating to a server loop restart testing device and method. Background Technology

[0002] Server stability testing includes AC Power Cycle testing, which involves repeatedly powering on and off the server to verify that the server functions normally when the power supply is repeatedly switched on and off. Currently, solutions for automating AC Power Cycle testing typically use AC fatigue testing machines or PDU cabinets, which require setting up complex network and power environments and do not offer the convenience of debugging in research and development laboratories.

[0003] When tests fail to meet standards, R&D often needs to reproduce the problem and analyze it. However, problem reproduction usually requires repeating the AC Power cycle process multiple times. Manually plugging and unplugging the power cord to reproduce the problem is not only a waste of manpower, but also cannot eliminate the interference of human factors. Summary of the Invention

[0004] To address the shortcomings of existing technologies, such as the need to build complex network and power environments for fatigue testing and the lack of abnormal problem reproduction capabilities, this invention provides a server cyclic restart testing device and method to solve the aforementioned technical problems.

[0005] In a first aspect, the present invention provides a server loop restart testing device, comprising:

[0006] A current control device and a controller are provided. The controller is connected to the enable port of the current control device. The current control device switches the power on / off state of the circuit between the server power supply and the motherboard based on the control signal of the controller. The controller is communicatively connected to the server BMC.

[0007] Furthermore, the current control device includes an electronic fuse array, which comprises multiple electronic fuses connected in parallel. The input terminals of the electronic fuses are electrically connected to the server power supply, and the output terminals of the electronic fuses are electrically connected to the motherboard.

[0008] Furthermore, the current control device and the controller are both integrated on the board, and the board is fixedly installed inside the protective housing.

[0009] Furthermore, the controller is connected to the server power supply via an independent branch, which is inherently in a closed state, and an electronic fuse is connected in series on the independent branch.

[0010] Furthermore, the controller is also connected to the status port of the current control device, and the status port outputs a potential status signal to the controller.

[0011] Secondly, the present invention also provides a method for testing server cyclic restarts, comprising:

[0012] Before performing a reboot, the BMC collects operating system information and saves it as initial information.

[0013] Send a test start command to the controller to cause the server to cycle through restarting the test device and switching the power on and off states of the motherboard power circuit.

[0014] Each time the operating system is detected to enter the boot state, the operating system information is captured as test information, the test information is compared with the initial information for consistency, and the difference information is saved. The operating system automatically boots up when powered on and runs a shutdown script to automatically shut down after booting up.

[0015] The system counts the number of times information is captured and sends a test end command to the controller when the number of information captures reaches a preset number.

[0016] Furthermore, before sending the test start command to the controller, the method also includes:

[0017] Set the waiting time based on the time required for the operating system's boot and shutdown processes;

[0018] The waiting time is sent to the server loop restart test device so that the server loop restart test device will be powered off when the power-on duration reaches the waiting time.

[0019] Furthermore, after sending the test start command to the controller, the method further includes:

[0020] Acquire the potential signal of the server cyclic restart test device. The potential signal includes a high level and a low level. A high level indicates that the server cyclic restart test device has entered the test state, and a low level indicates that the server cyclic restart test device has not entered the test state. In the test state, the server cyclic restart test device cyclically switches between power on and power off states.

[0021] If the potential signal of the server repeatedly restarts the test device is at a low level, a test error message will be generated.

[0022] Furthermore, the method for cyclically switching the power-on and power-off states of the server restart test device includes:

[0023] The controller enables the electronic fuse array to enter the energized state by controlling the level state of the current control device's enable port.

[0024] The controller times the duration of the power-on state, and when the duration reaches the waiting time, it turns the electronic fuse array into a power-off state by pulling up the level of the electronic fuse array enable port.

[0025] The controller collects the potential status signal of the status port of the current control device. If the potential status signal is high after the enable port level is pulled high, and low after the enable port level is pulled low, then the server cycle restart test device self-test is deemed to have passed.

[0026] Furthermore, each time the operating system is detected to be booting up, operating system information is captured as test information. This test information is then compared with the initial information for consistency, and any discrepancies are saved, including:

[0027] If the operating system is detected to be in place, the operating system information is captured as test information.

[0028] The test information is then compared with the initial information for consistency.

[0029] If the two are consistent, the test information is saved in a way that overwrites the previous test information;

[0030] If the two are inconsistent, the test information will be saved as an error message to a specified location.

[0031] Thirdly, based on the above-mentioned server loop restart test method, the present invention also provides a server loop restart test system, including:

[0032] The standard save module is used by the BMC to collect operating system information and save it as initial information before performing a reboot.

[0033] The test startup module is used to send a test start command to the controller so that the server can cycle through restarting the test device and switching the power on and off state of the motherboard power circuit.

[0034] The information capture module is used to capture operating system information as test information each time the operating system enters the boot state. The test information is compared with the initial information for consistency and the difference information is saved. The operating system automatically boots up when powered on and runs a shutdown script to automatically shut down after booting up.

[0035] The test termination module is used to count the number of information captures and send a test end command to the controller when the number of information captures reaches a preset number.

[0036] Furthermore, before sending the test start command to the controller, the system also performs the following:

[0037] Set the waiting time based on the time required for the operating system's boot and shutdown processes;

[0038] The waiting time is sent to the server loop restart test device so that the server loop restart test device will be powered off when the power-on duration reaches the waiting time.

[0039] Furthermore, after sending the test start command to the controller, the system also performs the following:

[0040] Acquire the potential signal of the server cyclic restart test device. The potential signal includes a high level and a low level. A high level indicates that the server cyclic restart test device has entered the test state, and a low level indicates that the server cyclic restart test device has not entered the test state. In the test state, the server cyclic restart test device cyclically switches between power on and power off states.

[0041] If the potential signal of the server repeatedly restarts the test device is at a low level, a test error message will be generated.

[0042] Furthermore, the method for cyclically switching the power-on and power-off states of the server restart test device includes:

[0043] The controller enables the electronic fuse array to enter the energized state by controlling the level state of the current control device's enable port.

[0044] The controller times the duration of the power-on state, and when the duration reaches the waiting time, it turns the electronic fuse array into a power-off state by pulling up the level of the electronic fuse array enable port.

[0045] The controller collects the potential status signal of the status port of the current control device. If the potential status signal is high after the enable port level is pulled high, and low after the enable port level is pulled low, then the server cycle restart test device self-test is deemed to have passed.

[0046] Furthermore, the information capture module includes:

[0047] The information capture unit is used to capture operating system information as test information if the operating system is detected to be in place.

[0048] An information comparison unit is used to compare the test information with the initial information for consistency.

[0049] An overwrite storage unit is used to save the test information in a manner that overwrites the previous test information if the two are consistent.

[0050] A specific storage unit is used to save the test information as an exception to a designated location if the two are inconsistent.

[0051] Fourthly, a terminal is provided, comprising:

[0052] Processor, memory, among which,

[0053] This memory is used to store computer programs.

[0054] The processor is used to retrieve and run the computer program from memory, causing the terminal to perform the terminal method described above.

[0055] Fifthly, a computer storage medium is provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the methods described in the above aspects.

[0056] The beneficial effects of this invention are that the server cyclic restart testing device and method provided by this invention can control the on / off state of the power supply line, and the start and termination of the control can be controlled by the BMC of the server under test. This invention eliminates the need for a fatigue tester and complex network settings when performing cyclic restart tests on servers, and can effectively record the testing process and reproduce abnormal scenarios.

[0057] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a schematic diagram of the structure of a server loop restart test device according to an embodiment of this application.

[0060] Figure 2 This is a flowchart illustrating a server loop restart test method according to an embodiment of this application.

[0061] Figure 3 This is an exemplary flowchart of the server-side execution method of a server loop restart test method according to an embodiment of this application.

[0062] Figure 4 This is an exemplary flowchart of the power-on / off state control of a server cyclic restart test method according to an embodiment of this application.

[0063] Figure 5 This is an exemplary block diagram of a server loop restart test system according to an embodiment of this application.

[0064] Figure 6 This is a schematic diagram of the structure of a terminal according to an embodiment of this application. Detailed Implementation

[0065] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0066] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0067] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0069] The key terms used in this invention will be explained below.

[0070] BMC, short for Baseboard Management Controller, is a remote server management controller. It allows for operations such as firmware upgrades and device monitoring even when the machine is not powered on. Fully implementing IPMI functionality in a BMC requires a powerful 16-bit or 32-bit microcontroller, RAM for data storage, flash memory for non-volatile data storage, and firmware. It provides basic remote manageability for secure remote reboots, secure power-on, LAN alerts, and system health monitoring. In addition to basic IPMI and system monitoring functions, the mBMC can also enable fast BIOS component selection and protection by utilizing one of the two flash memories to store the previous BIOS. For example, if the system fails to boot after a remote BIOS upgrade, remote administrators can switch back to the previous BIOS image to boot the system. Once the BIOS is upgraded, the BIOS image can also be locked to effectively prevent virus attacks.

[0071] The I2C bus is a simple, bidirectional, two-wire synchronous serial bus developed by Philips. It requires only two wires to transmit information between devices connected to the bus. The master device initiates data transmission and generates a clock to enable transmission; any addressed device is considered a slave. The master-slave and send-receive relationships on the bus are not constant but depend on the direction of data transmission. If the master wants to send data to a slave device, it first addresses the slave device, then actively sends data to the slave device, and finally terminates the data transmission. If the master wants to receive data from a slave device, it first addresses the slave device, then receives the data sent by the slave device, and finally terminates the receiving process. In this case, the master is responsible for generating the timing clock and terminating the data transmission.

[0072] BIOS is an abbreviation for "Basic Input Output System." On IBM PC compatible systems, it's an industry-standard firmware interface. It's a set of programs embedded in a ROM chip on the computer's motherboard. It stores the computer's most important basic input / output programs, power-on self-test (POST) programs, and system startup programs. It can read and write specific system settings from the CMOS. Its main function is to provide the lowest-level, most direct hardware settings and control for the computer. In addition, the BIOS provides some system parameters to the operating system. Changes to system hardware are hidden by the BIOS; programs use BIOS functions rather than directly controlling the hardware. Modern operating systems often bypass the abstraction layer provided by the BIOS and directly control hardware components.

[0073] EFuse electronic fuses. A lineup of efficient, reliable, and compact eFuse solutions features multiple protection characteristics, precise control, and real-time diagnostics. They offer fast response, protect circuits from high inrush currents, voltage spikes, and heat dissipation, and ensure they always operate in the safe operating area (SOA).

[0074] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0075] like Figure 1 As shown, the server continuously restarts the test setup, including:

[0076] The current controller and the controller are connected to the enable port of the current controller. The current controller switches the power on / off state of the circuit between the server power supply and the motherboard based on the control signal of the controller. The controller communicates with the server BMC.

[0077] The current controller acts like a switch, using a controllable high-current component to ensure a complete and controllable power supply path. The current controller is connected in series between the server power supply and the motherboard. The controller connects to the enable port of the current controller, thereby controlling its on / off state. The controller can also connect to the BMC of the server under test, initiating or deactivating power control based on BMC commands.

[0078] The current control device includes an electronic fuse array, which comprises multiple electronic fuses connected in parallel. The input terminals of the electronic fuses are electrically connected to the server power supply, and the output terminals are electrically connected to the motherboard. Specifically, the power supply input and output of the fuses are designed according to the server PSU output voltage and current standard (commonly 12V for typical servers). The number of fuses used is determined based on the overall power consumption of the server and the current that a single fuse can handle to ensure the power supply current meets the standard. The enable signal EN and status signal PG (or alarm signal Alert) of the components are connected to the logic control chip to achieve controllable power supply and simultaneously monitor the operating status of the fuses.

[0079] The controller can use programmable logic elements (PLUs) such as MCUs and CLPDs to interact with the motherboard BMC and control power supply functions. Control or monitoring signals from the power supply elements are connected to the MCU / CPLD. Software programming logic is used to control signal switching and status recording under predetermined conditions. The motherboard BMC is connected to the MCU / CPLD via communication protocols such as I2C / UART / SPI (ensuring the motherboard connector signals remain unchanged; generally, the I2C link connecting to the PSU can be used) to achieve information transmission and command control. A separate AC debug open pin is added to determine whether AC power cycle operation is currently in progress. The control elements use a separate power supply. The controller is connected to the server power supply through an independent branch. The inherent state of this independent branch is a closed circuit, and an electronic fuse is connected in series on this branch to ensure that the power supply is always on and never loses power.

[0080] The current control device and the controller are both integrated on the board, and the board is fixedly installed inside the protective housing.

[0081] In this system, upon receiving a start command from the BMC via the I2C link, the controller cycles through power-on and power-off by raising or lowering the enable port potential of the current controller. The server, on the other hand, powers on after each power-on cycle and automatically shuts down after running a script. When the BMC issues a stop command, the controller ceases cycling through the enable port potential of the current controller. Therefore, this server-based cyclic restart testing device can function as a fatigue test machine, directly controlled by the BMC even without a network connection. The entire device has a simple structure, requires no additional power supply, significantly simplifies the installation environment requirements compared to a fatigue test machine, and is less expensive.

[0082] During testing, the specific software logic includes: the server continuously restarts the test device as an AC debug fixture board; the MCU / CPLD receives the AC Power cycle command from the motherboard BMC and enters the AC Power cycle environment; the MCU / CPLD controls the output of the AC debug Open pin (generally preset to be active high) and the change of its state is ineffective, indicating that AC Power cycle is in progress; at the same time, it controls the Efuse EN signal (generally active high) to be turned off and monitors the PG signal (generally active high) to determine that the Efuse is normally turned off; after a certain delay to ensure that the motherboard is completely powered down, it controls the Efuse EN signal to be turned on and monitors the PG signal to determine that the Efuse is normally turned on; when the motherboard BMC does not issue the AC Power cycle command, the MCU / CPLD does not enter the AC Power cycle environment, the AC debug Open pin remains in an inactive state, indicating that AC Power cycle has not been performed.

[0083] In addition, for the server cycle restart test device, the controller can also perform a status self-test. This involves the controller acquiring the potential status signal of the status port of the current control device. If the potential status signal is high when the enable port level is pulled high, and low when the enable port level is pulled low, then the server cycle restart test device is considered to have passed the self-test. If the self-test fails, the controller generates an abnormal signal, which can be reported to the BMC or an abnormal status LED indicator can be lit based on the abnormal signal.

[0084] The server loop restart test method provided in this embodiment of the invention is executed by a computer device, and correspondingly, the server loop restart test system runs on the computer device.

[0085] Figure 1 This is a schematic flowchart illustrating a method according to an embodiment of the present invention. Wherein, Figure 1 The executing entity can be a server that continuously restarts the test system. Depending on different requirements, the order of the steps in this flowchart can be changed, and some can be omitted.

[0086] like Figure 2 As shown, the method includes:

[0087] Step 210: Before performing the reboot, the BMC collects operating system information and saves it as initial information;

[0088] Step 220: Send a test start command to the controller so that the server cyclically restarts the test device and cyclically switches the power on and off state of the motherboard power circuit.

[0089] Step 230: Each time the operating system is detected to enter the boot state, the operating system information is captured as test information, the test information is compared with the initial information for consistency, and the difference information is saved. The operating system automatically boots up when powered on and runs a shutdown script to automatically shut down after booting up.

[0090] Step 240 counts the number of information captures and sends a test end command to the controller when the number of information captures reaches a preset number.

[0091] To facilitate understanding of the present invention, the following description further illustrates the server loop restart testing method provided by the present invention, based on the principle of the server loop restart testing method of the present invention and in conjunction with the process of performing loop restart testing on the server in the embodiments.

[0092] Specifically, the server loop restart test method includes:

[0093] S1. Before performing a reboot, the BMC collects operating system information and saves it as initial information.

[0094] After the test begins, BMC first fetches operating system information from the CPU and saves it as initial information. The fetched operating system information can be the operating system log or specified target parameters.

[0095] S2. Send a test start command to the controller so that the server will cycle through restarting the test device and switching the power on and off states of the motherboard power circuit.

[0096] A waiting time is set based on the time required for the operating system's boot and shutdown processes. This waiting time is sent to the server cyclic restart test device so that the device is powered off when the power-on duration reaches the specified waiting time. Specifically, after the operating system powers on, it boots up. During the boot process, the BIOS performs a self-test, and after the self-test is complete, it enters the operating system. Therefore, the boot process takes time t1. After booting, the operating system runs the shutdown script, during which the BMC captures system logs, requiring time t2. The shutdown script calls the shutdown command, and the operating system sequentially powers down and shuts down, requiring time t3. Therefore, the waiting time can be set as t = t1 + t2 + t3 + t0, where t0 is the set margin value.

[0097] The BMC sends a test start command to the controller of the server cycle restart test device, initiating the power-on / off operation of the test device. Specifically, the BMC checks if the AC debug fixture board is in place; if so, it notifies the controller to enter the AC power cycle via the I2C link.

[0098] After sending a test start command to the controller, the BMC acquires the potential signal of the server cyclic restart test device. This potential signal includes high and low levels. A high level indicates that the server cyclic restart test device has entered the test state, while a low level indicates that it has not. During the test state, the server cyclic restart test device cycles through power-on and power-off states. If the potential signal of the server cyclic restart test device is low, a test error message is generated. Specifically, after the BMC starts up, it checks the AC debug Open pin status of the debug fixture board. A high status indicates that an AC power cycle is in progress, and the BMC controls the system to boot and continue executing the script; a low status indicates that the AC power cycle is not in progress and no other operations are performed.

[0099] S3. Each time the operating system is detected to enter the boot state, the operating system information is captured as test information, the test information is compared with the initial information for consistency, and the difference information is saved. The operating system automatically boots up when powered on and runs a shutdown script to automatically shut down after booting up.

[0100] Each time the server powers on, the BMC monitors that the operating system is present and uses a script to capture operating system information (such as operating system logs). It then determines whether the currently captured test information is consistent with the initial information: if they are consistent, the test information is saved to overwrite the previous test information; if they are inconsistent, the test information is saved as exception information to a designated location.

[0101] In one embodiment of the present invention, after receiving a start command issued by the BMC, the server cyclic restart test device starts performing cyclic power-on and power-off operations simultaneously while sending a signal of receiving the command back to the BMC. The method for the server cyclic restart test device to cyclically switch between power-on and power-off states includes: the controller using the level state of the enable port of the current control device to put the electronic fuse array into a powered-on state; the controller timing the duration of the powered-on state, and when the duration reaches a waiting time, pulling up the level state of the enable port of the electronic fuse array to put the electronic fuse array into a powered-off state; the controller acquiring the potential status signal of the status port of the current control device; if the potential status signal is high after the enable port level state is pulled high, and low after the enable port level state is pulled low, then the server cyclic restart test device is determined to have passed self-test.

[0102] S4. Count the number of times information is captured, and send a test end command to the controller when the number of information captures reaches the preset number of times.

[0103] Each time the BMC captures operating system information, it records the number of times the information is captured. When the current number of captures reaches the test count set in the script, it sends a test end command to the controller. Upon receiving the end command, the controller stops performing power-on / off operations and simultaneously sends a signal to the BMC indicating that the test program has ended. After the test is complete, the exception information recorded by the BMC can be reviewed and analyzed to determine the cause of the server startup failure.

[0104] The above method is executed by a test script, and the specific steps of the test script are as follows:

[0105] Server-side steps are as follows: Figure 3 As shown, it includes:

[0106] 1) Run the AC Power cycle script under the OS system

[0107] 2) The script collects and saves information normally under the system. The script stores the information collected the first time as the initial version of the information separately, and overwrites the information from other collection attempts.

[0108] 3) Judgment: After collecting all the information, the script compares it with the initial version to determine if they match. If they do not match, an exception occurs, and the process jumps to step 1-4); if they match, the process is normal, and the process jumps to step 1-5.

[0109] 4) When an error occurs, record the error information. The script can be paused based on the configuration options, retaining the error message. If configured not to pause the script, the shutdown command will continue to run, entering the AC Power cycle.

[0110] 5) The system notifies the BMC to enter the AC Power cycle environment and shuts down.

[0111] 6) Judgment: BMC checks whether the AC debug fixture board is in place. If it is not in place, it executes the normal fatigue testing machine environment logic; if it is in place, it executes the fixture board logic and jumps to the execution flow 1-7).

[0112] 7) Execute fixture board logic: After the BMC determines that the system is powered off, it sends a command to notify the MCU / CPLD to enter AC Powercycle.

[0113] 8) After the AC power cycle, the motherboard is powered on again.

[0114] 9) Judgment: After the BMC starts up, it checks the status of the AC debug Open pin on the debug fixture board. A high status indicates that the AC power cycle is in progress, and the BMC controls the power-on to continue executing the script, jumping to process 1-2); a low status indicates that the AC power cycle is not in progress and no other operations are performed.

[0115] 10) Shutdown script terminated under OS system

[0116] 11) Judgment: At this time, the BMC has not received a system notification to enter the AC Power cycle. It monitors the AC debugOpen pin status. If it is high, it sends a command to the MCU / CPLD to shut down the AC Power cycle and jumps to the execution flow 1-12); if it is low, it indicates that the AC Power cycle is no longer in progress and no other operations are performed.

[0117] 12) After confirming power-off, the BMC sends a command to the MCU / CPLD to shut down the AC power cycle.

[0118] The server loop restart test device steps are as follows: Figure 4 As shown, it includes:

[0119] 1) Determine: When the MCU / CPLD receives the BMC command to enter the AC Power cycle, it pulls the AC debug Openpin high and jumps to process 2-2); when the MCU / CPLD receives the BMC command to close the AC Power cycle, it pulls the AC debug Open pin low and jumps to process 2-9.

[0120] 2) Pull the AC debug Open pin high on the MCU / CPLD and hold it (a status LED can be added for display).

[0121] 3) Judgment: Check if the Efuse PG signal is high. If it is high, it indicates that Efuse is working normally, and jump to the execution flow 2-5); if it is low, it indicates that Efuse is abnormal, and jump to the execution flow 2-4.

[0122] 4) If the issue is identified as a debug jig board malfunction, the board's fault indicator light will illuminate, requiring board repair or replacement.

[0123] 5) MCU / CPLD pulls the Efuse EN signal low.

[0124] 6) Judgment: Check if the Efuse PG signal is low. A high signal indicates an Efuse malfunction, and the process jumps to step 2-4); a low signal indicates that Efuse has closed normally, and the process jumps to step 2-7.

[0125] 7) After a 20-second delay, raise Efuse EN again.

[0126] 8) Judgment: Check if the Efuse PG signal is high. If it is high, it means that Efuse is working normally and no operation is performed; if it is low, it means that Efuse is abnormal and jumps to the execution flow 2-4).

[0127] 9) Pull the AC debug Open pin low on the MCU / CPLD and hold it (this can be used to add a status LED for display).

[0128] In some embodiments, the server loop restart test system 500 may include multiple functional modules composed of computer program segments. The computer programs of each program segment in the server loop restart test system 500 may be stored in the memory of a computer device and executed by at least one processor to perform (see details). Figure 1 (Description) Functionality for testing server cyclic restarts.

[0129] In this embodiment, the server loop restart test system 500 can be divided into multiple functional modules according to its functions, such as... Figure 5 As shown. The functional modules may include: a standard saving module 510, a test initiation module 520, an information capture module 530, and a test termination module 540. The module referred to in this invention is a series of computer program segments that can be executed by at least one processor and perform a fixed function, and are stored in memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0130] The standard save module is used by the BMC to collect operating system information and save it as initial information before performing a reboot.

[0131] The test startup module is used to send a test start command to the controller so that the server can cycle through restarting the test device and switching the power on and off state of the motherboard power circuit.

[0132] The information capture module is used to capture operating system information as test information each time the operating system enters the boot state. The test information is compared with the initial information for consistency and the difference information is saved. The operating system automatically boots up when powered on and runs a shutdown script to automatically shut down after booting up.

[0133] The test termination module is used to count the number of information captures and send a test end command to the controller when the number of information captures reaches a preset number.

[0134] Optionally, as an embodiment of the present invention, the system further performs the following before sending the test start command to the controller:

[0135] Set the waiting time based on the time required for the operating system's boot and shutdown processes;

[0136] The waiting time is sent to the server loop restart test device so that the server loop restart test device will be powered off when the power-on duration reaches the waiting time.

[0137] Optionally, as an embodiment of the present invention, after sending a test start command to the controller, the system further performs the following:

[0138] Acquire the potential signal of the server cyclic restart test device. The potential signal includes a high level and a low level. A high level indicates that the server cyclic restart test device has entered the test state, and a low level indicates that the server cyclic restart test device has not entered the test state. In the test state, the server cyclic restart test device cyclically switches between power on and power off states.

[0139] If the potential signal of the server repeatedly restarts the test device is at a low level, a test error message will be generated.

[0140] Optionally, as an embodiment of the present invention, the method for the server cyclic restart test device to cyclically switch between power-on and power-off states includes:

[0141] The controller enables the electronic fuse array to enter the energized state by controlling the level state of the current control device's enable port.

[0142] The controller times the duration of the power-on state, and when the duration reaches the waiting time, it turns the electronic fuse array into a power-off state by pulling up the level of the electronic fuse array enable port.

[0143] The controller collects the potential status signal of the status port of the current control device. If the potential status signal is high after the enable port level is pulled high, and low after the enable port level is pulled low, then the server cycle restart test device self-test is deemed to have passed.

[0144] Optionally, as an embodiment of the present invention, the information capture module includes:

[0145] The information capture unit is used to capture operating system information as test information if the operating system is detected to be in place.

[0146] An information comparison unit is used to compare the test information with the initial information for consistency.

[0147] An overwrite storage unit is used to save the test information in a manner that overwrites the previous test information if the two are consistent.

[0148] A specific storage unit is used to save the test information as an exception to a designated location if the two are inconsistent.

[0149] Figure 6 This is a schematic diagram of a terminal 600 provided in an embodiment of the present invention. The terminal 600 can be used to execute the server loop restart test method provided in the embodiment of the present invention.

[0150] The terminal 600 may include a processor 610, a memory 620, and a communication module 630. These components communicate via one or more buses. Those skilled in the art will understand that the server structure shown in the figures does not constitute a limitation of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0151] The memory 620 can be used to store the execution instructions of the processor 610. The memory 620 can be implemented using any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. When the execution instructions in the memory 620 are executed by the processor 610, the terminal 600 is able to perform some or all of the steps in the above method embodiments.

[0152] The processor 610 serves as the control center of the storage terminal, connecting various parts of the electronic terminal via various interfaces and lines. It executes software programs and / or modules stored in the memory 620, and calls data stored in the memory to perform various functions of the electronic terminal and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 610 may consist only of a central processing unit (CPU). In this embodiment of the invention, the CPU may have a single processing core or include multiple processing cores.

[0153] The communication module 630 is used to establish a communication channel, enabling the storage terminal to communicate with other terminals. It receives user data from other terminals or sends user data to other terminals.

[0154] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps provided in the embodiments of the present invention. The storage medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0155] Therefore, this invention can control the on / off state of the power supply line, and the start and termination of control can be controlled by the BMC of the server under test. This invention does not require a fatigue tester or complex network settings when performing cyclic restart tests on the server, and it can effectively record the test process and reproduce abnormal scenarios. The technical effects achieved by this embodiment can be found in the description above, and will not be repeated here.

[0156] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software and necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code. It includes several instructions to cause a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0157] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0158] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or modules may be electrical, mechanical, or other forms.

[0159] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0160] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0161] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.

Claims

1. A server loop restart testing device, characterized in that, include: A current control device and a controller, wherein the controller is connected to the enable port of the current control device, the current control device switches the power on / off state of the circuit between the server power supply and the motherboard based on the control signal of the controller, and the controller is communicatively connected to the server BMC; After receiving the start command sent by the BMC via the I2C link, the controller achieves cyclic power on / off by raising or lowering the enable port potential of the current controller. The current control device includes an electronic fuse array, which comprises multiple electronic fuses connected in parallel. The input terminals of the electronic fuses are electrically connected to the server power supply, and the output terminals of the electronic fuses are electrically connected to the motherboard. The controller is connected to the server power supply through an independent branch, which is inherently in a closed state, and an electronic fuse is connected in series on the independent branch. The controller collects the potential status signal of the status port of the current control device. If the potential status signal is high after the enable port level is pulled high, and low after the enable port level is pulled low, then the server cycle restart test device self-test is deemed to have passed. If the self-test fails, the controller generates an abnormal signal, which can be reported to the BMC. Based on the abnormal signal, the abnormal status LED indicator will be lit. Before performing a reboot, the BMC collects operating system information and saves it as initial information. Send a test start command to the controller to cause the server to cycle through restarting the test device and switching the power on and off states of the motherboard power circuit. Each time the operating system is detected to enter the boot state, the operating system information is captured as test information, the test information is compared with the initial information for consistency, and the difference information is saved. The operating system automatically boots up when powered on and runs a shutdown script to automatically shut down after booting up. The system counts the number of times information is captured and sends a test end command to the controller when the number of information captures reaches a preset number. During testing, the specific software logic includes: the server continuously restarts the test device as an AC debug fixture board; the MCU / CPLD receives the AC Power cycle command from the motherboard BMC and enters the AC Power cycle environment; the MCU / CPLD controls the AC debug Open pin to change its state, but the change is ineffective, indicating that the AC Power cycle is in progress; simultaneously, the Efuse EN signal is turned off, and the PG signal is monitored to determine that the Efuse is properly turned off; after a certain delay to ensure that the motherboard is completely powered off, the Efuse EN signal is turned on, and the PG signal is monitored to determine that the Efuse is properly turned on; when the motherboard BMC does not issue the AC Power cycle command, the MCU / CPLD does not enter the AC Power cycle environment, and the AC debug Open pin remains in an invalid state, indicating that the AC Power cycle has not been performed.

2. The server loop restart test device according to claim 1, characterized in that, The current control device and controller are both integrated on the board, and the board is fixedly installed inside the protective housing.

3. The server loop restart test device according to claim 1, characterized in that, Before sending the test start command to the controller, the following is also included: Set the waiting time based on the time required for the operating system's boot and shutdown processes; The waiting time is sent to the server loop restart test device so that the server loop restart test device will be powered off when the power-on duration reaches the waiting time.

4. The server loop restart test device according to claim 3, characterized in that, After sending the test start command to the controller, the following is also included: Acquire the potential signal of the server cyclic restart test device. The potential signal includes a high level and a low level. A high level indicates that the server cyclic restart test device has entered the test state, and a low level indicates that the server cyclic restart test device has not entered the test state. In the test state, the server cyclic restart test device cyclically switches between power on and power off states. If the potential signal of the server repeatedly restarts the test device is at a low level, a test error message will be generated.

5. The server loop restart test device according to claim 4, characterized in that, The server in test mode cycles through restarting the test device, switching between power-on and power-off states, including: The controller enables the electronic fuse array to enter the energized state by controlling the level state of the current control device's enable port. The controller times the duration of the power-on state, and when the duration reaches the waiting time, it turns the electronic fuse array into a power-off state by pulling up the level of the electronic fuse array enable port. The controller collects the potential status signal of the status port of the current control device. If the potential status signal is high after the enable port level is pulled high, and low after the enable port level is pulled low, then the server cycle restart test device self-test is deemed to have passed.

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