Test methods, computer devices, and computer-readable storage media

Abstract

The application relates to a test method, a computer device and a computer readable storage medium. The test method comprises the following steps: writing first data into a target storage unit; performing reverse writing on the target storage unit; reading second data stored in the target storage unit after reverse writing; judging whether the second data is the same as the first data; and when the second data is the same as the first data, judging that the write recovery time of the target storage unit is invalid. The application can effectively test the write recovery time invalidation.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory device manufacturing technology, and in particular to a testing method, computer equipment, and computer-readable storage medium. Background Technology

[0002] As the feature size of semiconductor integrated circuits continues to shrink, the critical dimensions of semiconductor memory devices are also becoming smaller, making the manufacturing process increasingly prone to defects and leading to various abnormal failures in memory cells. Among these, write recovery time failures have a significant impact on device performance; therefore, developing effective testing methods for them is a crucial aspect of memory device manufacturing. Summary of the Invention

[0003] Therefore, it is necessary to provide a test method, computer device, and computer-readable storage medium that can effectively test write recovery time failures in response to the above-mentioned technical problems.

[0004] A testing method includes: writing first data to a target storage unit; performing a reverse write to the target storage unit; reading second data stored in the reverse-written target storage unit; determining whether the second data is the same as the first data; and determining that the write recovery time of the target storage unit has failed when the second data is the same as the first data.

[0005] In one embodiment, after determining that the write recovery time of the target storage cell has failed when the second data is the same as the first data, the method further includes: detecting whether there is an isolation layer between the bit line and the bit line contact hole structure of the target storage cell.

[0006] In one embodiment, before reading the second data stored in the storage target unit after reverse writing, the method includes: setting a CSL start time, wherein the CSL start time is less than a preset time.

[0007] In one embodiment, the CSL start time is set before writing the first data to the target storage unit; after writing the first data to the target storage unit and before writing the target storage unit back, the method further includes: reading the first data stored in the target storage unit.

[0008] In one embodiment, after determining whether the second data is the same as the first data, the method further includes: when the second data is different from the first data, setting the CSL start time again to shorten the CSL start time until the second data is the same as the first data, and obtaining the CSL start time when the second data is the same as the first data.

[0009] In one embodiment, before writing the first data to the target storage unit, the process includes setting the power supply voltage of the target storage unit.

[0010] In one embodiment, while writing first data to the target storage cell, data opposite to the first data is written to other storage cells located around and adjacent to the target storage cell.

[0011] In one embodiment, the first data is "1", and the data opposite to the first data is "0".

[0012] In one embodiment, the X-fast method is used to write data to the target storage array, so as to write the first data to the target storage unit and write the opposite data to the other storage units in the target storage array.

[0013] In one embodiment, the storage device under test includes multiple storage banks, each storage bank including multiple storage arrays. Before writing data to the target storage array using the X-fast method, the method further includes: determining a target storage bank among the multiple storage banks; and determining a target storage array among the multiple storage arrays of the target storage bank.

[0014] In one embodiment, before writing data to the target storage array using the X-fast method, the process includes writing "0" to all storage cells of the storage device under test.

[0015] In one embodiment, after writing "0" to all memory cells of the storage device under test, the method further includes: refreshing all memory cells of the storage device under test.

[0016] In one embodiment, before writing "0" to all storage cells of the storage device under test, the method further includes: clearing residual information from all storage cells of the storage device under test and initializing the storage device under test.

[0017] A computer device includes a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of any of the methods described above.

[0018] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0019] The aforementioned test method, computer equipment, and computer-readable storage medium first write the first data "1" (or "0") to the target storage cell, and then perform a reverse write operation on the target storage cell. When the CSL (Continuous Storage Streaming) enable time is the standard reference time, during the CSL enable time, the capacitor discharge (or charging) process of the target storage cell is hindered, causing the voltage reversal speed of the corresponding bit line of the target storage cell to slow down. Consequently, after the CSL time ends during the reverse write recovery time, the relationship between the potential on the bit line and the potential on the complementary bit line does not reverse. During the write recovery time after the CSL time ends, under the action of the sensing amplifier between the bit line and the complementary bit line, the potential on the bit line returns to the supply voltage Vary (or the supply voltage Vss corresponding to the first data "1") under the action of the sensing amplifier between the bit line and the complementary bit line. At this time, the bit line with the supply voltage Vary (or supply voltage Vss) corresponding to the first data will write the first data again into the target storage cell because the word line is open, thus causing the reverse write operation on the target storage cell to fail. Therefore, by reading the second data stored in the target storage cell after it has been reversed and comparing whether the second data is the same as the first data, it is possible to effectively determine whether the target storage cell has failed due to charging obstruction when the CSL start time is the standard reference time. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating a testing method in one embodiment;

[0022] Figure 2a This is a signal timing diagram for writing the target memory cell backwards in one embodiment;

[0023] Figure 2b This is a timing diagram of the bit line and complementary bit line during write recovery time when the target memory cell is written backward in one embodiment;

[0024] Figures 3 to 6 This is a flowchart illustrating the testing method in other different embodiments;

[0025] Figure 7 This is a schematic diagram illustrating the data writing method of the target storage array in one embodiment;

[0026] Figure 8 This is a flowchart illustrating the testing method in yet another embodiment. Detailed Implementation

[0027] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0029] It is understood that the terms "first" and "second" used in this application are used to describe the data written, but the data values ​​are not limited by these terms. These terms are only used to distinguish the data written.

[0030] In one embodiment, see Figure 1 A testing method is provided, including:

[0031] Step S10: Write the first data to the target storage unit;

[0032] Step S30: Reverse write the target memory cell;

[0033] Step S40: Read the second data stored in the target storage unit after reverse writing;

[0034] Step S50: Determine whether the second data is the same as the first data;

[0035] Step S60: When the second data is the same as the first data, the write recovery time of the target storage unit is determined to be invalid.

[0036] In step S10, the "target memory cell" is a memory cell selected from among the memory cells of the memory device for testing write recovery time failure. There may be one or more target memory cells. The memory cell includes a switching transistor and a capacitor.

[0037] The first data written to the target storage unit can specifically be "1". Of course, it can also be "0", there is no restriction here.

[0038] Taking "1" as the first data value as an example, when the memory device receives a write instruction to write the first data to the target memory cell, during the write recovery time, it first activates the write driver and then provides the CSL control signal, thereby activating the control transistor between the bit line and the input terminal of the target memory cell, thus turning on the bit line and the input terminal. Simultaneously, the word line signal of the target memory cell is activated beforehand, turning on its switching transistor, thereby turning on the capacitor and bit line of the target memory cell. Therefore, during the CSL activation time, the input terminal is connected to the capacitor of the target memory cell, thus charging the capacitor of the target memory cell, and the signal on the bit line is pulled up.

[0039] After providing the CSL control signal for a certain period, it is disconnected. The signal on the bit line of the target memory cell is amplified by a sense amplifier to the supply voltage corresponding to the first data. When the first data is "1", its corresponding supply voltage is "Vary". At this time, the bit line charges the capacitor in the target memory cell, thereby writing data to the target memory cell. The word line signal is turned off after the write recovery time.

[0040] In step S30, taking the first data as "1" as an example, the reverse writing process of the target storage unit will be explained.

[0041] Please see Figure 2a During the data write operation, there is first a delay time (tRCD time) for transferring the memory row address to the column address, followed by a write recovery time (tWR). During tRCD, after the bit line equalization signal is turned off (BLEQOFF), the word line is turned on (WL ON), and the word line voltage rises from VKK to VPP, enabling charge sharing between memory cells, sharing the charge on their capacitors to the bit line BL. The potential on the bit line BL is pulled up to the supply voltage Vary through sensing amplification by the sense amplifier (SA sensing), while the potential on the complementary bit line / BL is pulled down to the supply voltage Vss through sensing amplification by the sense amplifier. At the start of tWR, the write driver is turned on (Write driveron), and during the CSL on time, the bit line BL is strobed (YS ON) to receive the input voltage. Then, the write driver is turned off (Write driver off). After tWR, the memory row address strobe pulse precharge time (tPR) begins. During the tPR time, the word line is turned off (WL OFF), the sense amplifier is turned off (SA OFF), and the bit line equalization signal is turned on (BLEQ ON), thereby pulling the bit line potential down to the intermediate potential (VBLE).

[0042] As shown in Figure 2, when the target memory cell containing the first data "1" is reversed, during the tRCD time, due to the charge sharing of the target memory cell and the amplification effect of the sensing amplifier, the potential on the bit line will be pulled up to Vary.

[0043] Then, during the write recovery time for writing "0" backwards, the write driver is first enabled. Then the CSL control signal is enabled. Simultaneously, the word line signal of the target memory cell has already been enabled during the tRCD time. Therefore, during the CSL enable time, the input terminal is connected to the capacitor of the target memory cell, causing the capacitor of the target memory cell to discharge, and the signal on the bit line is pulled down.

[0044] During reverse writing, if the CSL start time is the standard reference time ("standard reference time" is the reference time used to determine whether the storage unit meets the standard. This time can be set according to customer requirements or internal product requirements, etc.), for the ideal target storage unit, please refer to [link to relevant documentation]. Figure 2a During the CSL (Concurrent Segmentation Level) turn-on period, the capacitors within the memory cell discharge rapidly, causing the signals on the bit lines to be pulled down quickly. At this point, after the CSL turn-on period ends (i.e., after the CSL control signal is disconnected), the bit line BL voltage is less than the voltage of the complementary bit line / BL. Subsequently, the potential on the bit line of the memory cell is amplified by the sense amplifier and pulled down to Vss, causing the target memory cell to discharge completely and write "0" to it. Simultaneously, the potential on the complementary bit line is amplified by the sense amplifier and pulled up to Vary. After this, the sense amplifier and word lines are turned off, and the equalization circuit is turned on to make the bit line voltage and the complementary bit line voltage equal, i.e., both VCC / 2 (the midpoint between Vary and Vss).

[0045] Please see Figure 2b During the CSL enable time, when the capacitor discharge within the memory cell is hindered, the pull-down speed of the bit line voltage corresponding to the target memory cell is slow. At this time, after the CSL enable time ends (i.e., after the CSL control signal is disconnected), the bit line BL voltage is still greater than the complementary bit line voltage / BL. After the CSL enable time ends (i.e., after the CSL control signal is disconnected), the sense amplifier pulls the bit line voltage back up to Vary and charges the target memory cell, while the complementary bit line voltage is pulled down to Vss. Because the sense amplifier pulls the bit line voltage back up to Vary, recharging the target memory cell, the target memory cell is incorrectly written with a "1" before the sense amplifier and word line are turned off and before the equalization circuit is turned on.

[0046] In step S40, specifically, when the CSL start time during reverse writing is the standard reference time, the data reverse-written to the target storage cell is read. When the first data is "1", if the second data read is "0", it means that the target storage cell has not failed when the CSL start time is the standard reference time, thus meeting the standard requirements. If the second data read is "1", it means that the target storage cell has failed due to the obstruction of capacitor discharge when the CSL start time is the standard reference time, thus failing to meet the standard requirements.

[0047] In step S50, specifically, when the first data is "1", it is determined whether the second data read in step S40 is "1", so as to determine whether the write recovery time of the target storage unit has failed.

[0048] In step S60, when the first data is "1", as can be seen from the analysis of the aforementioned reverse writing process, when the second data is the same as the first data (both are "1"), it indicates that the target memory cell fails because its capacitor discharge is blocked when the CSL start time is the standard reference time.

[0049] The above explanation uses "1" as the first data as an example. When the first data is "0", the principle and process are similar to the above.

[0050] When the first data is "0", as can be seen from the aforementioned reverse writing process, when the second data is the same as the first data (both are "0"), it indicates that the target memory cell fails because its capacitor charging is blocked when the CSL start time is the standard reference time.

[0051] In this embodiment, the first data "1" (or "0") is written to the target memory cell, and then the target memory cell is written backwards. When the CSL (Continuous Storage Streaming) enable time is the standard reference time, during the CSL enable time, the capacitor discharge (or charging) process of the target memory cell is blocked, which slows down the voltage reversal speed of the corresponding bit line of the target memory cell. Consequently, after the CSL time ends during the write recovery time for the reverse write, the relationship between the potential on the bit line and the potential on the complementary bit line is not reversed. During the write recovery time after the CSL time ends, under the action of the sensing amplifier between the bit line and the complementary bit line, the potential on the bit line returns to the supply voltage Vary (or the supply voltage Vss corresponding to the first data "1") under the action of the sensing amplifier between the bit line and the complementary bit line. At this time, the bit line with the supply voltage Vary (or supply voltage Vss) corresponding to the first data will write the first data into the target memory cell again because the word line is open, thus causing the reverse write of the target memory cell to fail. Therefore, by reading the second data stored in the target storage cell after it has been reversed and comparing whether the second data is the same as the first data, it is possible to effectively determine whether the target storage cell has failed due to charging obstruction when the CSL start time is the standard reference time.

[0052] In one embodiment, see Figure 3 After step S60, the following steps are also included:

[0053] Step S70: Detect whether there is an isolation layer between the bit line and the bit line contact hole structure of the target memory cell.

[0054] When an isolation layer forms between the bit line and the bit line contact hole of the target memory cell due to by-product residues, the resistance between them increases. Therefore, when there is a defect of an isolation layer between the bit line and the bit line contact hole structure of the target memory cell, the charging of the memory cell will be hindered.

[0055] Therefore, in step S60, when it is determined that the target memory cell fails due to charging obstruction when the CSL turn-on time is the standard reference time, it may be due to the presence of an isolation layer between the bit line and the bit line contact hole of the target memory cell (of course, it may also be due to other reasons that cause the memory cell to be blocked from charging).

[0056] Therefore, the determination of the write recovery time failure of the target memory cell in step S60 can serve as the basis for determining whether there is an isolation layer between the bit line and the bit line contact hole structure.

[0057] In one embodiment, after step S10 and before step S30, the method further includes:

[0058] Step S01: Set the CSL start time, which is less than the preset time.

[0059] As an example, the "preset time" can be the maximum time specified by JEDEC, or it can be less than the maximum start time value specified by JEDEC.

[0060] If the target storage unit does not fail when the CSL (Continuous Storage Stream) is enabled for a period less than the preset time, it will generally not fail when the CSL is enabled for a period equal to the preset time. Therefore, this embodiment can make a more reliable failure judgment on visually inspected storage units by shortening the CSL enable time.

[0061] In one embodiment, see Figure 4 The steps following step S10 and before step S30 include:

[0062] Step S20: Read the first data stored in the target storage unit.

[0063] At this point, it can be confirmed whether the first data was successfully written to the target storage unit, thus ensuring the accuracy of the test results.

[0064] Specifically, when the first data is "1", during the reading of the target memory cell, in the charge sharing phase within the tRCD time, the charge corresponding to "1" is shared to the bit line, causing its voltage to be pulled up.

[0065] The increase in bit line voltage, through the action of the sense amplifier, causes the voltage on the complementary bit line to be pulled down and the voltage on the bit line to be pulled up further. This interaction gradually amplifies the potential difference between the bit line and the complementary bit line. Ultimately, the potential on the bit line is pulled up to Vary, and the potential on the complementary bit line is pulled down to Vss.

[0066] When writing the target memory cell backwards, the time tRCD also passes, and within the time tRCD, the potential on the bit line reverses from Vary to Vss.

[0067] In one embodiment, see Figure 5 After step S50, the following steps are also included:

[0068] Step S80: When the second data is different from the first data, the CSL start time is set again to shorten the CSL start time until the second data is the same as the first data, and the CSL start time when the second data is the same as the first data is obtained.

[0069] As an example, before the second data is the same as the first data, the CSL start time can be shortened by the same amount each time. Of course, this is not a limitation.

[0070] Meanwhile, when setting the CSL enable time for the target storage unit once or multiple times, the initial CSL enable time is used as the standard reference time. Subsequent CSL enable times are then shortened based on the standard reference time.

[0071] In this embodiment, by shortening the CSL enable time, the limit value of the CSL enable time for the target storage unit to maintain normal operation can be obtained, thereby obtaining the limit value of the write recovery time for the target storage unit to maintain normal operation.

[0072] In one embodiment, see Figure 6 Before step S10, the following are also included:

[0073] Step S02: Set the power supply voltage of the target storage unit.

[0074] Specifically, when the first data is "1", the power supply voltage Vary of the target storage unit can be set to be less than the first preset voltage.

[0075] At this point, the charge level of the target memory cell when writing the first data "1" can be reduced. Therefore, when writing "0" back to the target memory cell, the voltage difference between its capacitor and bit line is reduced. A larger voltage difference between the capacitor and bit line results in a stronger electric field, making it easier to form a conductive path and mitigating the problem of capacitor discharge obstruction caused by defects in the isolation layer. Therefore, if the target memory cell does not fail under these conditions, it will not fail under the first preset voltage. This also effectively improves test reliability.

[0076] When the first data is "0", the power supply voltage Vss of the target storage unit can be set to be greater than the second preset voltage.

[0077] At this point, the charge level of the target memory cell when writing the first data "0" can be increased. Therefore, when writing a "1" to the target memory cell in reverse, the voltage difference between the capacitor and the bit line decreases. A larger voltage difference between the capacitor and the bit line results in a stronger electric field, making it easier to form a conductive path. Therefore, if the target memory cell does not fail under this condition, it will not fail under the second preset voltage. This also effectively improves test reliability.

[0078] In one embodiment, in step S10, while writing the first data to the target storage cell, data opposite to the first data is also written to other storage cells located around and adjacent to the target storage cell.

[0079] As an example, the first data can be set to "1", and the opposite data can be set to "0". In this case, the target memory cell is written with "1", while all other memory cells surrounding and adjacent to the target memory cell are written with "0". Simultaneously, due to the electrical coupling between the target memory cell and its surrounding cells, charge in the target memory cell leaks to the surrounding cells, resulting in a relatively small amount of charge stored within it. This leads to a smaller voltage difference between the bit line voltage and the target memory cell voltage during subsequent reverse writing.

[0080] Alternatively, the first data can be set to "0", and the opposite data to the first data can be set to "1". In this case, the target memory cell is written with "0", while other memory cells surrounding and adjacent to the target memory cell are all written with "1". At the same time, due to the electrical coupling between the target memory cell and the surrounding memory cells, the positive charge of other memory cells around the target memory cell will be transferred to the target memory cell, thereby increasing the amount of charge stored in the target memory cell. This results in a smaller voltage difference between the bit line voltage and the voltage of the target memory cell during the subsequent reverse write process.

[0081] Therefore, if the target memory cell does not fail under this condition, it is even less likely to fail under other conditions where the voltage difference between the target memory cell and the bit line is greater. This can also effectively improve test reliability.

[0082] In one embodiment, step S10 uses the X-fast method to write data to the target storage array, so as to write first data to the target storage cell and write data opposite to the first data to other storage cells in the target storage array.

[0083] Specifically, the target storage array comprises multiple storage cells, and these storage cells include several target storage cells. Please refer to [link / reference]. Figure 7 The left side of the dashed line illustrates a schematic diagram when the X-fast method is used to write data "1" to the target storage array, while writing data "0" (the opposite of "1") to all other storage cells in the target storage array; the right side of the dashed line illustrates a schematic diagram when the X-fast method is used to write data "0" to the target storage array, while writing data "1" (the opposite of "0") to all other storage cells in the target storage array.

[0084] The X-fast method involves sequentially writing the burst length of each word line in the target memory array, and then starting from the beginning after writing the required number of bits for the burst length. Although X-FAST has a slower write speed, it offers better write quality, thereby improving the reliability of test results.

[0085] In one embodiment, the storage device under test includes multiple memory banks, and each memory bank includes multiple memory arrays.

[0086] Step S10, before writing data to the target storage array using the X-fast method, also includes:

[0087] Step S03: Determine the target memory bank among multiple memory banks;

[0088] Step S04: Determine the target storage array among the multiple storage arrays of the target storage.

[0089] In this embodiment, for the target memory, after all target memory cells in its target memory array have determined whether a target memory cell is faulty based on whether the second data is the same as the first data, the target memory array can be changed among multiple memory arrays of the target memory until all target memory cells in all memory arrays of the target memory have determined whether a target memory cell is faulty based on whether the second data is the same as the first data. Afterwards, the target memory can be changed until all target memory cells in all memory cells of the storage device under test have determined whether a target memory cell is faulty based on whether the second data is the same as the first data, thereby completing the testing of the entire storage device under test.

[0090] In one embodiment, before writing data to the target storage array using the X-fast method in step S10, the following steps are included:

[0091] Step S05: Write "0" to all memory cells of the storage device under test.

[0092] This allows all memory cells to be in the same state and eliminates the influence of voltage noise.

[0093] As an example, the Y-fast method can be used to write the data "0" to all memory cells. The Y-fast method writes a word line completely before writing the next word line. The Y-fast method offers a faster write speed, thus effectively improving testing efficiency.

[0094] Of course, other writing methods (such as X-fast) can also be used to write "0" to all memory cells of the storage device under test; there are no restrictions on this.

[0095] In one embodiment, after step S05, the method further includes:

[0096] Step S06: Refresh all memory cells of the storage device under test.

[0097] At this point, it can be further ensured that all memory cells are in the same state and the effects of voltage noise can be eliminated.

[0098] Here, if steps S03 and S04 are included before step S10 uses the X-fast method to write data to the target storage array, step S03 can be set after step S06. In this case, when performing cyclic testing on each storage cell and each storage array, it is not necessary to repeat the previous operations, thereby improving testing efficiency.

[0099] In one embodiment, before step S05, the method further includes:

[0100] Step S07: Clear residual information from all storage cells of the storage device under test and initialize the storage device under test.

[0101] At this time, interference from external factors can be effectively avoided during testing.

[0102] Specifically, residual information in the memory cells is cleared, even if they are in an intermediate state between "0" and "1". Initializing the memory device under test involves clearing residual information from registers, etc.

[0103] In one embodiment, see Figure 8 A testing method is provided, including:

[0104] Step S1: Set the power supply voltage Vary of the target storage cell to be less than the first preset voltage;

[0105] Step S2: Write "0" to all memory cells of the storage device under test;

[0106] Step S3: Refresh all memory cells of the storage device under test;

[0107] Step S4: Determine the target memory bank among multiple memory banks;

[0108] Step S5: Determine the target storage array among the multiple storage arrays of the target storage;

[0109] Step S6: Use the X-fast method to write data to the target storage array, write "1" to the target storage cell and write "0" to all other storage cells in the target storage array.

[0110] Step S7: Read the "1" stored in the target storage unit;

[0111] Step S8: Set the CSL start time, which is less than the preset time;

[0112] Step S9: Reverse write the target storage unit;

[0113] Step S10: Read the second data stored in the target storage unit after reverse writing;

[0114] Step S11: Check if the second data is the same as "1";

[0115] Step S12: When the second data is the same as "1", the write recovery time of the target storage unit is determined to be invalid.

[0116] Step S13: When the second data is different from "1", the CSL start time is set again to shorten the CSL start time until the second data is the same as "1" and the CSL start time when the second data is the same as "1" is obtained.

[0117] Next, the target storage array in the target storage unit can be replaced, and steps S6 to S13 above can be repeated until all storage arrays in the target storage unit have been tested. Then, the target storage unit can be replaced until all storage units have been tested.

[0118] In this embodiment, the limit value of the CSL enable time for each target memory cell in the storage device under test to remain normal and without failure can be obtained, thereby obtaining the limit value of the write recovery time for each target memory cell in the storage device under test to remain normal.

[0119] It should be understood that although the steps in each flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in each flowchart may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0120] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described above.

[0121] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the above methods.

[0122] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0123] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0124] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A testing method, characterized in that, include: Write the first data to the target storage unit; The target storage unit is reverse-written; Read the second data stored in the target storage unit after it has been reverse-written; Determine whether the second data is the same as the first data; When the second data is the same as the first data, the write recovery time of the target storage unit is determined to be invalid. After writing the first data to the target storage unit and before writing the target storage unit back, the process includes: Set the CSL start time, where the CSL start time is less than a preset time; After determining whether the second data is the same as the first data, the method further includes: When the second data is different from the first data, the CSL start time is set again to shorten the CSL start time until the second data is the same as the first data, and the CSL start time when the second data is the same as the first data is obtained.

2. The test method according to claim 1, characterized in that, After determining that the write recovery time of the target storage unit has failed when the second data is the same as the first data, the method further includes: Detect whether there is an isolation layer between the bit lines and bit line contact hole structures of the target memory cell.

3. The test method according to claim 1, characterized in that, After writing the first data to the target storage unit and before writing the target storage unit back, the method further includes: Read the first data stored in the target storage unit.

4. The test method according to any one of claims 1, characterized in that, Before writing the first data to the target storage unit, the following steps are included: Set the power supply voltage for the target storage unit.

5. The test method according to claim 1, characterized in that, While writing the first data to the target storage unit, data opposite to the first data is written to other storage units located around and adjacent to the target storage unit.

6. The test method according to claim 5, characterized in that, The first data is "1", and the data opposite to the first data is "0".

7. The test method according to claim 5, characterized in that, The X-fast method is used to write data to the target storage array, so as to write the first data to the target storage cell and write the opposite data to the other storage cells in the target storage array.

8. The test method according to claim 7, characterized in that, The storage device under test includes multiple memory cells, and each memory cell includes multiple memory arrays. Before writing data to the target storage array using the X-fast method, the process also includes: Among the plurality of storage entities, the target storage entity is determined; Among the multiple storage arrays of the target storage, the target storage array is determined.

9. The test method according to claim 7 or 8, characterized in that, Before writing data to the target storage array using the X-fast method, the following steps are included: Write "0" to all memory cells of the storage device under test.

10. The test method according to claim 9, characterized in that, After writing "0" to all memory cells of the storage device under test, the process further includes: Refresh all memory cells of the storage device under test.

11. The test method according to claim 9, characterized in that, Before writing "0" to all memory cells of the storage device under test, the method further includes: Residual information is cleared from all storage cells of the storage device under test, and the storage device under test is initialized.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 11.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

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