Avs3 mode decision circuit, method, device and storage medium
By designing a flexible instruction cache module and a programmable computing module, the adaptability of the AVS3 mode decision circuit in different application scenarios is improved, solving the problem of poor adaptability after hardware solidification and meeting the diverse requirements of coding performance and real-time performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PENG CHENG LAB
- Filing Date
- 2023-06-12
- Publication Date
- 2026-05-29
AI Technical Summary
Once the existing AVS3 mode decision circuit is fixed in hardware, the algorithm pruning method cannot be changed, resulting in poor adaptability as it cannot meet the different requirements for coding performance, power consumption, and real-time performance in different application scenarios.
Design an AVS3 mode decision circuit, including an instruction cache module, a data cache module, and an arithmetic module. It achieves hardware resource scheduling through flexible circuit control instructions, supports different coding requirements, and adopts programmable units and parallel design to achieve differentiated configuration.
This improves the adaptability of the AVS3 mode decision circuit in different application scenarios, meeting the diverse requirements of coding performance, power consumption, and real-time performance.
Smart Images
Figure CN116723317B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of video processing technology, and in particular to an AVS3 mode decision circuit, method, device and storage medium. Background Technology
[0002] AVS3 (Audio Video Coding Standard) refers to the third-generation audio and video codec standard. The mode decision algorithm in this standard utilizes intra-frame prediction and inter-frame prediction techniques to remove spatial and temporal redundancy in video information, achieving video compression. The purpose of intra-frame and inter-frame prediction techniques is to obtain the optimal block partitioning method for each maximum coding unit (LCU) and the optimal prediction mode for each sub-block. The numerous block partitioning methods and candidate prediction modes in the AVS3 standard make the mode decision algorithm the most complex part of the coding algorithm.
[0003] In existing encoder hardware circuit designs for newer standards, algorithmic pruning is required to reduce the complexity of the mode decision circuit, i.e., removing some block partitioning paths and candidate prediction modes that have little impact on performance. However, the drawback of this approach is that once the hardware implementation is fixed, the algorithmic pruning method cannot be changed, making it unable to meet the different requirements for coding performance, power consumption, and real-time performance in different application scenarios, resulting in poor adaptability of the AVS3 mode decision circuit. Summary of the Invention
[0004] The main objective of this application is to provide an AVS3 mode decision circuit, method, device, and storage medium, aiming to solve the technical problem of poor adaptability of existing AVS3 mode decision circuits.
[0005] To achieve the above objectives, this application provides an AVS3 mode decision circuit, which includes:
[0006] An instruction cache module stores circuit control instructions for instructing the reading of data from the data cache module to the arithmetic module for algorithmic computation, and for instructing the storage of the computation results from the arithmetic module to the data cache module. The circuit control instructions can be modified to meet different encoding requirements.
[0007] A data caching module is used to store the encoded data generated by the computing module;
[0008] The arithmetic module, which consists of programmable units, is used to read corresponding data from the data cache module according to the received circuit control instructions, perform algorithm calculations, and store the calculation results in the data cache module.
[0009] Optionally, the computing module adopts a programmable design, including a programmable data reading unit LOAD, a programmable data storage unit STORE, a computing unit PU, and a bypass unit BYPASS.
[0010] Optionally, the LOAD, STORE, and PU are designed in parallel, wherein the LOAD and STORE read and write data to multiple PUs in parallel, the execution between PUs is completely parallel, and the LOAD, STORE, and PUs operate in a data-dependent pipeline.
[0011] Optionally, the arithmetic module employs a prefetch mechanism for control instructions, wherein the prefetch mechanism provides each unit under the arithmetic module with an independent instruction buffer, and the instruction buffer is configured to read multiple control instructions in the same clock cycle.
[0012] Optionally, the data caching module adopts a sharding and grouping method, wherein the data cache is divided into multiple shards with the same structure, each shard is grouped by the LCU data structure, and each group contains the data space required for different sizes in the LCU data structure; each PU shares the shards and groups of cached data; LOAD or STORE can access data of various different sizes in the same shard and / or the same group in parallel.
[0013] Optionally, the circuit control instructions in the instruction cache module include a group index, which is determined based on the instruction pointer value and the group status register. The group status register includes a waiting synchronization status register and a trigger synchronization status register, which are used to reflect the current status information of each unit.
[0014] This application also provides an AVS3 mode decision-making method applied to an AVS3 mode decision-making circuit, wherein the AVS3 mode decision-making circuit includes an instruction cache module, a data cache module, and a computation module, and the AVS3 mode decision-making method includes:
[0015] Obtain the circuit control instructions from the instruction cache module;
[0016] The circuit control command is sent to the computing module. Based on the computing module and the circuit control command, the corresponding data to be predicted in the data cache module is read, and the prediction operation is performed on the data to be predicted to obtain the pattern decision result.
[0017] The pattern decision results are stored in the data cache module.
[0018] Optionally, the step of reading the corresponding data to be predicted from the data cache module based on the computing module and the circuit control instructions, and performing prediction operations on the data to be predicted to obtain the pattern decision result includes:
[0019] Based on the aforementioned arithmetic module, the index address in the circuit control instruction is determined;
[0020] Based on the index address, the corresponding data to be predicted in the data cache module is read, and a prediction operation is performed on the data to be predicted to obtain coded data, wherein the coded data includes a cost value;
[0021] The encoded data corresponding to the minimum cost value is determined as the pattern decision result.
[0022] This application also provides an AVS3 mode decision-making device, which includes: a memory, a processor, and a program stored in the memory for implementing the AVS3 mode decision-making method.
[0023] The memory is used to store the program that implements the AVS3 mode decision method;
[0024] The processor is used to execute a program that implements the AVS3 mode decision method, so as to implement the steps of the AVS3 mode decision method.
[0025] This application also provides a storage medium storing a program for implementing the AVS3 mode decision method, wherein the program for implementing the AVS3 mode decision method is executed by a processor to implement the steps of the AVS3 mode decision method.
[0026] This application provides an AVS3 mode decision circuit, method, device, and storage medium. Compared to related technologies that require algorithm pruning to reduce the complexity of the mode decision circuit in encoder hardware circuit design for newer standards (i.e., deleting some block partitioning paths and candidate prediction modes with minimal performance impact), this approach suffers from the drawback that the pruning method cannot be changed once the hardware implementation is fixed. This makes it difficult to meet the different requirements for encoding performance, power consumption, and real-time performance in various application scenarios, resulting in poor adaptability of the AVS3 mode decision circuit. In contrast, this application's AVS3 mode decision circuit includes: an instruction cache module storing circuit control instructions for instructing data to be read from a data cache module and fed into a computation module for algorithmic computation, and for instructing the computation results to be stored in the data cache module. The circuit control instructions can be modified to meet different encoding requirements. A data cache module stores the encoded data generated by the computation module. A computation module, composed of programmable units, reads corresponding data from the data cache module according to the received circuit control instructions, performs algorithmic computation, and stores the computation results in the data cache module. In this application, flexible hardware resource scheduling is achieved based on the circuit control instructions in the instruction cache module, thereby enabling differentiated configuration of the video encoder hardware circuit in different application scenarios to improve the adaptability of the AVS3 mode decision circuit. Attached Figure Description
[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.
[0028] Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of this application;
[0029] Figure 2 This is a flowchart illustrating the first embodiment of the AVS3 mode decision-making method of this application;
[0030] Figure 3 This is a schematic diagram of the AVS3 mode decision circuit of this application;
[0031] Figure 4 This is the scheduling process of the quadtree partitioning algorithm for encoding units in the first embodiment of the AVS3 mode decision method of this application.
[0032] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0033] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0034] like Figure 1 As shown, Figure 1 This is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiments of this application.
[0035] The terminal in this application embodiment can be a PC, or a smartphone, tablet computer, e-book reader, MP3 (Moving Picture Experts Group Audio Layer III) player, MP4 (Moving Picture Experts Group Audio Layer IV) player, portable computer, or other portable terminal devices with display functions.
[0036] like Figure 1 As shown, the terminal may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a memory 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard. Optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
[0037] Optionally, the terminal may also include a camera, RF (Radio Frequency) circuitry, sensors, audio circuitry, a WiFi module, and so on. Sensors may include light sensors, motion sensors, and other sensors. Specifically, light sensors may include ambient light sensors and proximity sensors. The ambient light sensor can adjust the display brightness according to the ambient light level, while the proximity sensor can turn off the display and / or backlight when the mobile terminal is moved to the ear. As a type of motion sensor, a gravity accelerometer can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity, and can be used for applications that identify the mobile terminal's posture (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition functions (such as pedometers, taps), etc. Of course, the mobile terminal may also be equipped with other sensors such as gyroscopes, barometers, hygrometers, thermometers, and infrared sensors, which will not be elaborated here.
[0038] Those skilled in the art will understand that Figure 1 The terminal structure shown does not constitute a limitation on the terminal and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0039] like Figure 1 As shown, the memory 1005, which serves as a computer storage medium, may include an operating device, a network communication module, a user interface module, and an AVS3 mode decision program.
[0040] exist Figure 1 In the terminal shown, the network interface 1004 is mainly used to connect to the backend server and communicate with the backend server; the user interface 1003 is mainly used to connect to the client (user terminal) and communicate with the client; and the processor 1001 can be used to call the AVS3 mode decision program stored in the memory 1005.
[0041] Reference Figure 2 This application provides an AVS3 mode decision-making method, which includes:
[0042] Step S100: Obtain circuit control instructions from the instruction cache module;
[0043] Step S200: Send the circuit control command to the computing module; based on the computing module and the circuit control command, read the corresponding data to be predicted in the data cache module, and perform prediction calculation on the data to be predicted to obtain the pattern decision result.
[0044] Step S300: Store the pattern decision result in the data cache module.
[0045] In this embodiment, the application scenario is:
[0046] As an example, the scenario for AVS3 mode decision-making can be based on AVS3, using intra-frame prediction and inter-frame prediction techniques to remove spatial and temporal redundancy in video information, respectively, to achieve video compression. In existing encoder hardware circuit designs for newer standards, algorithm pruning is required to reduce the complexity of the mode decision circuit, i.e., deleting some block partitioning paths and reducing the number of candidate prediction modes that have little impact on performance. However, the drawback of this approach is that once the hardware implementation is fixed, the algorithm pruning method cannot be changed, failing to meet the different requirements for encoding performance, power consumption, and real-time performance in different application scenarios, resulting in poor adaptability of the AVS3 mode decision circuit. To address this, the AVS3 mode decision-making method in this embodiment achieves flexible hardware resource scheduling based on circuit control instructions in the instruction cache module, thereby enabling differentiated configuration of the video encoder hardware circuit in different application scenarios to improve the adaptability of the AVS3 mode decision circuit.
[0047] This embodiment aims to improve the adaptability of the AVS3 mode decision circuit.
[0048] In this embodiment, the AVS3 mode decision method is applied to the AVS3 mode decision circuit scheduling system.
[0049] The specific steps are as follows:
[0050] Step S100: Obtain circuit control instructions from the instruction cache module;
[0051] In this embodiment, the AVS3 mode decision circuit includes an instruction cache module, a data cache module, and a computation module. The instruction cache module stores circuit control instructions to instruct the computation module to read data from the data cache module and execute algorithm operations. The scheduling system changes the circuit control instructions to meet different encoding requirements. Specifically, the circuit control instructions are designed / generated according to the different requirements for encoding performance, power consumption, and real-time performance in different application scenarios. Since the algorithm pruning method cannot be changed after the hardware implementation is fixed in related technologies, this application can achieve flexible hardware resource scheduling based on the circuit control instructions in the instruction cache module, thereby enabling differentiated configuration of the video encoder hardware circuit in different application scenarios to improve the adaptability of the AVS3 mode decision circuit.
[0052] In this embodiment, the circuit control instructions in the instruction cache module include a group index, which is determined based on the instruction pointer value and the group status register. The group status register includes a waiting synchronization status register and a trigger synchronization status register, which are used to reflect the current status information of each unit. Specifically, the control instructions have two special synchronization flag bits, which mark the waiting synchronization status register and the trigger synchronization status register respectively, so as to flexibly describe the serial-parallel scheduling relationship between instruction sets.
[0053] In this embodiment, this application provides a circuit control instruction set design in the instruction cache module, including a data space mode, instruction set format, and serial-parallel programming model. Specifically, the data space mode adopts a fragmented shared space, and addressing is divided into [fragment, group, intra-group address], all three parts being positive integers. The group index is determined by the instruction directly specifying the value and the group status register, improving efficiency. The instruction operators consist of LOAD, PU, STORE, and BYPASS. The LOAD and STORE instructions can transmit data to multiple PUs simultaneously, and the PU index is encoded in the instruction. The instruction set execution model supports two modes: a distributed execution model, where instructions corresponding to different modules are distributed and executed in their respective modules; and a centralized execution model, where instructions corresponding to different modules are executed in a unified value-decoding module. The same instruction supports both execution modes.
[0054] Step S200: The circuit control command is sent to the arithmetic module. Based on the arithmetic module and the circuit control command, the corresponding data to be predicted in the data cache module is read, and the prediction operation is performed on the data to be predicted to obtain the pattern decision result.
[0055] In this embodiment, the system sends the circuit control command to the arithmetic module. Based on the arithmetic module and the circuit control command, it reads the corresponding data to be predicted from the data cache module and performs prediction calculations on the data to be predicted to obtain a pattern decision result. The arithmetic module is composed of programmable units. Specifically, the arithmetic module adopts a programmable design and includes a programmable data reading unit (LOAD), a programmable data storage unit (STORE), an arithmetic unit (PU), and a bypass unit (BYPASS). The arithmetic module is used to read the corresponding data from the data cache module and perform algorithm calculations according to the received circuit control command. The arithmetic module reads the corresponding data to be predicted from the data cache module through the programmable data reading unit (LOAD), the programmable data storage unit (STORE), and the circuit control command, and performs prediction calculations on the data to be predicted to obtain a pattern decision result. The PU (Programmable Logic Unit) is responsible for calculating the optimal prediction mode for coding units of corresponding sizes using intra-frame and inter-frame prediction techniques, and generating the corresponding reconstructed pixels and coding costs. When determining the optimal block partitioning method for upper-layer coding units, since the encoded data of lower-layer coded units can be directly read from the data buffer without requiring repeated calculations by the PU, the BYPASS writes the read data back to the designated location in the data buffer via the STORE. The LOAD (Loading and Loading) reads data from the data buffer according to the corresponding instructions in the instruction buffer and sends it to the PU or BYPASS. The STORE writes the data generated by the PU or BYPASS into the data buffer according to the corresponding instructions in the instruction buffer. The LOAD and STORE are crucial for the programmable scheduling of the video coding mode decision circuit. To reduce the complexity of circuit implementation, the LOAD and STORE are integrated into a single circuit, which includes corresponding functional modules for each size.
[0056] In this embodiment, the data cache is used to store the encoded data generated by each size computing module. The data cache adopts a multi-channel sharding design to ensure that the encoded data generated by different block partitioning paths do not interfere with each other. The specific number of channels is related to the enabled block partitioning paths. Each channel is further divided into multiple data groups, and each group can store the data structure of one LCU. The grouping design allows computing modules that do not have data dependencies to work in parallel.
[0057] In this embodiment, the instruction cache is used to store control instructions for the programmable modules written by the host computer. These instructions include instructing the data reading unit (LOAD) to read data from a specified numbered data cache and send it to a corresponding size arithmetic unit (PU) or bypass unit (BYPASS), and instructing the data storage unit (STORE) to write the output data of the arithmetic unit (PU) or bypass unit (BYPASS) into a specified numbered data cache. The specific cached instructions and their order need to be determined by the host computer based on the enabled block path. LOAD and STORE have independent instruction buffers. Through the prefetching mechanism of the instruction cache and the parallel access of the data cache, parallel execution of various arithmetic modules without data dependencies can be achieved, reducing coding time. The prefetching mechanism of the instruction cache refers to reading a portion of the instructions stored in the instruction cache in advance and simultaneously sending each instruction to the idle module pointed to by the instruction, achieving parallel execution. The parallel access of the data cache is implemented through the block design of the data cache and the sizing design of the data reading module.
[0058] Specifically, step S200 includes the following steps S210-S230:
[0059] Step S210: Based on the arithmetic module, determine the index address in the circuit control instruction;
[0060] Step S220: Based on the index address, read the corresponding data to be predicted in the data cache module, and perform prediction operation on the data to be predicted to obtain encoded data, wherein the encoded data includes a cost value;
[0061] Step S230: The encoded data corresponding to the minimum cost value is determined as the pattern decision result.
[0062] In this embodiment, the circuit control instruction includes an index address indicating LOAD and / or STORE to read data. The system determines the index address in the circuit control instruction according to the circuit control instruction. That is, the arithmetic module reads the corresponding data to be predicted in the data cache module according to the index address in the circuit control instruction, and performs prediction operation on the data to be predicted to obtain encoded data. The encoded data includes a cost value. The encoded data corresponding to the minimum cost value is determined as the pattern decision result.
[0063] In this embodiment, refer to Figure 4Taking the 32*32 LCU mode decision-making process as an example, this paper illustrates a scheduling process of the AVS3 mode decision-making circuit structure when completing the task of partitioning four blocks: no partitioning (NS), horizontal binary tree (BTH), vertical binary tree (BTV), and quadtree (QT). Specifically, BTH partitioning corresponds to rows 1 to 4 in the diagram; BTV partitioning corresponds to rows 5 to 8; QT partitioning corresponds to rows 9 to 12; and NS corresponds to row 13. The scheduling process is as follows: modules in the same row are executed sequentially from left to right; modules in different rows are executed in parallel; and modules spanning multiple rows must wait for all modules to their left to complete their processing before execution. Figure 4 The modules marked MxN in the middle are computational units, that is... Figure 3 The system includes prediction computation modules of varying sizes. Furthermore, after comparing the cost of each block's partitioned path, the data storage unit writes the encoded data corresponding to the optimal cost into the data cache. The programmability of the pattern decision circuit is reflected in its ability to flexibly combine different processing flows by changing the rows corresponding to different rows in the instruction switch diagram.
[0064] For different LCU sizes (64*64, 128*128) and different block partitioning paths (NS, QT, BTH, BTV, EQTH, EQTV), the hardware module scheduling process still follows the same rules. Figure 2 The heterogeneous modes shown are (LOAD, PU / BYPASS, STORE). The difference lies in the number of hardware modules required (i.e., Figure 2 The number of rows in the code is different, and the instructions for different circuits are also different.
[0065] by Figure 4 This example illustrates how changing the instructions can alter the mode decision circuit. Figure 4 The diagram illustrates the scheduling process of a 32x32 LCU calculating four partitioning paths: NS, BTH, BTV, and QT. Row 13 in the diagram corresponds to the 13 required circuit groups, representing the maximum number of circuits required for partitioning decisions. In a particular application scenario, if it's necessary to reduce the encoder chip's power consumption, the control instructions for the four circuit groups corresponding to the first four rows can be deleted from the instruction cache, putting them into an idle state. This effectively shuts down the BTH calculation path of the 32x32 LCU, thus reducing power consumption.
[0066] Step S300: Store the pattern decision result in the data cache module.
[0067] This application provides an AVS3 mode decision method. Compared to related technologies that require algorithmic pruning to reduce the complexity of the mode decision circuit in encoder hardware circuit design for newer standards (i.e., deleting some block partitioning paths and reducing the number of candidate prediction modes with minimal performance impact), this method suffers from the drawback that the pruning method cannot be changed once the hardware implementation is fixed. This makes it difficult to meet the different requirements for encoding performance, power consumption, and real-time performance in various application scenarios, resulting in poor adaptability of the AVS3 mode decision circuit. In contrast, this application's AVS3 mode decision circuit includes: an instruction cache module storing circuit control instructions for instructing data to be read from a data cache module and fed into a computation module for algorithmic computation, and for instructing the computation results to be stored in the data cache module. The circuit control instructions can be modified to meet different encoding requirements. A data cache module stores the encoded data generated by the computation module. A computation module, composed of programmable units, reads corresponding data from the data cache module according to the received circuit control instructions, performs algorithmic computation, and stores the computation results in the data cache module. In this application, flexible hardware resource scheduling is achieved based on the circuit control instructions in the instruction cache module, thereby enabling differentiated configuration of the video encoder hardware circuit in different application scenarios to improve the adaptability of the AVS3 mode decision circuit.
[0068] This application also provides an AVS3 mode decision circuit, the AVS3 mode decision circuit comprising:
[0069] An instruction cache module stores circuit control instructions for instructing the reading of data from the data cache module to the arithmetic module for algorithmic computation, and for instructing the storage of the computation results from the arithmetic module to the data cache module. The circuit control instructions can be modified to meet different encoding requirements.
[0070] A data caching module is used to store the encoded data generated by the computing module;
[0071] The arithmetic module, which consists of programmable units, is used to read corresponding data from the data cache module according to the received circuit control instructions, perform algorithm calculations, and store the calculation results in the data cache module.
[0072] In this embodiment, refer to Figure 3 ,like Figure 1 As shown, the AVS3 mode decision circuit comprises three main parts: instruction cache, data cache, and arithmetic module. The arithmetic module further includes a programmable data read unit (LOAD), a programmable data store unit (STORE), an arithmetic unit (PU), and a bypass unit (BYPASS).
[0073] In this embodiment, the AVS3 mode decision circuit includes programmable parallel read, programmable parallel storage, parallel processing units and parallel bypass units, pipelines and synchronization control mechanisms, etc. Its characteristics are: First, different sized circuit modules are unified into their respective circuits according to various functions. For example, data reading of different sizes is integrated into one circuit structure, and data writing of different sizes is integrated into the same circuit. For example, for... Figure 4 The first three rows of circuit modules, with dimensions of 16*16, 16*8, and 8*16 respectively, are designed to calculate the cost of dividing the current 16*16 brightness CU into three block partitioning methods: NS, BTH, and BTV. The partitioning method with the lowest cost is selected as the block partitioning method for this 16*16 brightness CU. Since the input data of the three circuits is the same, and the optimal output data is selected as the final output, the three sets of data reading and writing can be merged to reduce the number of circuits. Second, the reading, writing, operation, and bypass modules are programmable. By dynamically or statically changing the instructions, the selection of the encoding mode, the order of execution, and the complexity of mode calculation can be controlled and changed. Third, control synchronization between the same execution unit and different execution units is achieved through the synchronization domain of the instructions and the synchronization status register. These features are all independent protection points, including some features appearing alone or in combination.
[0074] In this embodiment, the AVS3 mode decision circuit is used for the instruction set design of programmable mode decision scheduling, including data space mode, instruction set format, serial-parallel programming model, etc., and its features are: First, the data space mode adopts a fragmented shared space, and the addressing is divided into [fragment, group, intra-group address], all three parts are represented by positive integers; Second, the group index is determined by the instruction directly specifying the value and the group status register, which improves efficiency; Third, the instruction operators consist of data fetch (LOAD), calculation (PU), write back (STORE), bypass (BYPASS), etc.; Fourth, LOAD and STORE instructions can transmit data for multiple PUs simultaneously, and the PU index is encoded in the instruction; Fifth, the instruction set execution model supports two types: the distributed execution model distributes the instructions corresponding to different modules in their respective modules for execution, and the centralized execution model executes the instructions corresponding to different modules in a unified value fetching and decoding module. The same instruction supports both execution methods; Sixth, there are two special synchronization flags in the instruction, which respectively mark the waiting synchronization status register and the trigger synchronization status register, so as to flexibly describe the serial-parallel scheduling relationship between instruction sets;
[0075] In this embodiment, the parallel design of LOAD, STORE, and PU in the operation module of the AVS3 mode decision circuit allows LOAD and STORE to read and write data from multiple PUs in parallel, and the execution between PUs is completely parallel. LOAD, STORE, and PU operate in a data-dependent pipeline.
[0076] In this embodiment, the data cache of the AVS3 mode decision circuit is designed with segmentation and grouping. The features are as follows: First, the data cache is divided into multiple segments with the same structure. Each segment is grouped based on the LCU data structure, and each group contains data space required for different sizes within the LCU data structure. Second, all segments and groups are shared by all PUs, and access to shared data is performed through the LOAD and STORE modules. Third, LOAD (or STORE) can access data of various sizes within the same segment and group in parallel, with a data access parallelism reaching (but not limited to) 64 data / clock cycles. Fourth, segment and group addressing can be performed through direct instruction specification and accumulation via the LOAD (or STORE) module. Fifth, LOAD and STORE can access different segments simultaneously. These features are all independent protection points, including some features appearing alone or in combination.
[0077] In this embodiment, the instruction cache prefetching mechanism of the AVS3 mode decision circuit is characterized by: first, each programmable module has an independent instruction buffer; second, the instruction cache has a bypass mode to directly access instructions in external memory; third, the instruction cache can read multiple instructions in the same clock cycle; and fourth, the instruction cache can simultaneously trigger data transfer to multiple PUs.
[0078] This application provides an AVS3 mode decision circuit. Similar to related technologies that design encoder hardware circuits for newer standards, which require algorithmic pruning to reduce the complexity of the mode decision circuit—that is, removing some block partitioning paths and candidate prediction modes with minimal performance impact—this approach suffers from drawbacks. Once the hardware implementation is fixed, the algorithmic pruning method cannot be changed, failing to meet the varying requirements for encoding performance, power consumption, and real-time performance in different application scenarios, resulting in poor adaptability of the AVS3 mode decision circuit. In contrast, this application's AVS3 mode decision circuit includes: an instruction cache module storing circuit control instructions for instructing data to be read from a data cache module and fed into a computation module for algorithmic computation. The circuit control instructions can be modified to meet different encoding requirements; a data cache module storing encoded data generated by the computation module; and a computation module composed of programmable units for reading corresponding data from the data cache module and performing algorithmic computation based on received circuit control instructions. In this application, flexible hardware resource scheduling is achieved based on the circuit control instructions in the instruction cache module, thereby enabling differentiated configuration of the video encoder hardware circuit in different application scenarios to improve the adaptability of the AVS3 mode decision circuit.
[0079] Reference Figure 1 , Figure 1 This is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiments of this application.
[0080] like Figure 1 As shown, the terminal may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a memory 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard. Optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
[0081] Optionally, the AVS3 mode decision-making device may also include a rectangular user interface, a network interface, a camera, RF (Radio Frequency) circuitry, sensors, audio circuitry, a WiFi module, etc. The rectangular user interface may include a display screen and an input submodule such as a keyboard. Optionally, the rectangular user interface may also include a standard wired interface or a wireless interface. The network interface may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).
[0082] Those skilled in the art will understand that Figure 1 The AVS3 mode decision device structure shown does not constitute a limitation on the AVS3 mode decision device. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0083] like Figure 1 As shown, the memory 1005, serving as a storage medium, may include an operating system, a network communication module, and an AVS3 mode decision-making program. The operating system is a program that manages and controls the hardware and software resources of the AVS3 mode decision-making device, supporting the operation of the AVS3 mode decision-making program and other software and / or programs. The network communication module is used to enable communication between the various components within the memory 1005, as well as communication with other hardware and software in the AVS3 mode decision-making system.
[0084] exist Figure 1 In the AVS3 mode decision-making device shown, the processor 1001 is used to execute the AVS3 mode decision-making program stored in the memory 1005 to implement the steps of the AVS3 mode decision-making method described above.
[0085] The specific implementation of the AVS3 mode decision device in this application is basically the same as the embodiments of the AVS3 mode decision method described above, and will not be repeated here.
[0086] This application also provides a storage medium storing a program implementing the AVS3 mode decision method, wherein the program implementing the AVS3 mode decision method is executed by a processor to implement the AVS3 mode decision method as follows:
[0087] Obtain the circuit control instructions from the instruction cache module;
[0088] The circuit control command is sent to the computing module. Based on the computing module and the circuit control command, the corresponding data to be predicted in the data cache module is read, and the prediction operation is performed on the data to be predicted to obtain the pattern decision result.
[0089] Optionally, the step of reading the corresponding data to be predicted from the data cache module based on the computing module and the circuit control instructions, and performing prediction operations on the data to be predicted to obtain the pattern decision result includes:
[0090] Based on the aforementioned arithmetic module, the index address in the circuit control instruction is determined;
[0091] Based on the index address, the corresponding data to be predicted is read from the data cache module, and a prediction operation is performed on the data to be predicted to obtain the pattern decision result.
[0092] The specific implementation of the storage medium in this application is basically the same as the embodiments of the AVS3 mode decision method described above, and will not be repeated here.
[0093] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the AVS3 mode decision method described above.
[0094] The specific implementation of the computer program product in this application is basically the same as the embodiments of the AVS3 mode decision method described above, and will not be repeated here.
[0095] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0096] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0098] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. An AVS3 mode decision circuit, characterized in that, The AVS3 mode decision circuit includes: An instruction cache module stores circuit control instructions for instructing the reading of data from the data cache module to the arithmetic module for algorithmic computation, and for instructing the storage of the computation results from the arithmetic module to the data cache module. The circuit control instructions can be modified to meet different encoding requirements. A data caching module is used to store the encoded data generated by the computing module; The arithmetic module is composed of programmable units and is used to read corresponding data from the data cache module according to the received circuit control instructions, perform algorithm calculations, and store the calculation results in the data cache module. The arithmetic module adopts a programmable design and includes a programmable data reading unit LOAD, a programmable data storage unit STORE, an arithmetic unit PU, and a bypass unit BYPASS. The data caching module adopts a sharding and grouping method. The data cache is divided into multiple shards with the same structure. Each shard is grouped by the LCU data structure. Each group contains the data space required for different sizes in the LCU data structure. Each PU shares the shards and groups of cached data. LOAD or STORE can access data of various sizes in the same shard and / or the same group in parallel.
2. The AVS3 mode decision circuit as described in claim 1, characterized in that, The LOAD, STORE, and PU are designed to run in parallel. The LOAD and STORE read and write data to multiple PUs in parallel, and the execution of PUs is completely parallel. The LOAD, STORE, and PUs run in a data-dependent pipeline.
3. The AVS3 mode decision circuit as described in claim 1, characterized in that, The arithmetic module employs a prefetch mechanism for control instructions. The prefetch mechanism involves each unit under the arithmetic module having an independent instruction buffer, and the instruction buffer is configured to read multiple control instructions in the same clock cycle.
4. The AVS3 mode decision circuit as described in claim 1, characterized in that, The circuit control instructions in the instruction cache module include a group index, which is determined based on the instruction pointer value and the group status register. The group status register includes a waiting synchronization status register and a trigger synchronization status register, which are used to reflect the current status information of each unit.
5. An AVS3 model decision-making method, characterized in that, An AVS3 mode decision-making circuit is applied, the AVS3 mode decision-making circuit including an instruction cache module, a data cache module, and an arithmetic module, and the AVS3 mode decision-making method includes: Obtain the circuit control instructions from the instruction cache module; The circuit control command is sent to the computing module. Based on the computing module and the circuit control command, the corresponding data to be predicted in the data cache module is read, and the data to be predicted is predicted to be calculated to obtain the pattern decision result. The computing module adopts a programmable design and includes a programmable data reading unit LOAD, a programmable data storage unit STORE, a computing unit PU, and a bypass unit BYPASS. The pattern decision results are stored in the data cache module. The data cache module adopts a sharding and grouping method. The data cache is divided into multiple shards with the same structure. Each shard is grouped by the LCU data structure. Each group contains the data space required for different sizes in the LCU data structure. Each PU shares the shards and groups of cached data. LOAD or STORE can access data of various sizes in the same shard and / or the same group in parallel.
6. The AVS3 mode decision method as described in claim 5, characterized in that, The step of reading the corresponding data to be predicted from the data cache module based on the computing module and the circuit control instructions, and performing prediction operations on the data to be predicted to obtain the pattern decision result includes: Based on the aforementioned arithmetic module, the index address in the circuit control instruction is determined; Based on the index address, the corresponding data to be predicted in the data cache module is read, and a prediction operation is performed on the data to be predicted to obtain coded data, wherein the coded data includes a cost value; The encoded data corresponding to the minimum cost value is determined as the pattern decision result.
7. An AVS3 mode decision-making device, characterized in that, The AVS3 mode decision device includes: a memory, a processor, and a program stored in the memory for implementing the AVS3 mode decision method. The memory is used to store the program that implements the AVS3 mode decision method; The processor is configured to execute a program that implements the AVS3 mode decision method to perform the steps of the AVS3 mode decision method as described in any one of claims 5 to 6.
8. A storage medium, characterized in that, The storage medium stores a program that implements the AVS3 mode decision method, which is executed by a processor to implement the steps of the AVS3 mode decision method as described in any one of claims 5 to 6.