Method for calibrating digital i / o channels of semiconductor test equipment

Abstract

This invention discloses a method for calibrating digital I / O channels of a semiconductor test equipment. The steps include: S1, grouping the digital I / O channels of the semiconductor test equipment into groups of at least three, and then using a first calibration board to test and solve the signal transmission and reception delays between the digital I / O channels in each group; S2, regrouping the digital I / O channels using an offset "1" method, and then using a second calibration board to test and solve the signal transmission and reception delays between the digital I / O channels in each newly grouped group; S3, constructing and solving the delay calculation expressions for each digital I / O channel in the transmission and reception directions; S4, using the delay values ​​obtained in step S3 as the basis for compensation to perform delay compensation on the corresponding digital I / O channels, thereby achieving calibration and alignment of each digital I / O channel. This invention solves the problem of signal asynchrony between digital I / O channels of the test equipment without increasing the design difficulty and manufacturing cost of the calibration board.

Description

Technical Field

[0001] This invention relates to the field of I / O channel calibration technology, and more specifically to a method for calibrating digital I / O channels of semiconductor test equipment. Background Technology

[0002] In the field of semiconductor testing, for digital chips such as ASICs (Application Specific Integrated Circuits) and memory chips, test equipment connects to the pins under test (DUT) of the chip via digital I / O channels. It provides timing-compliant stimulus signals or receives signals from the DUT to test the chip's functionality and timing parameters. Test equipment typically provides multiple digital I / O channels. During testing, the delays of signals sent from these I / O channels to the DUT or received from the DUT must be equal or have a fixed difference to ensure synchronized transmission and reception of test signals. This is especially important for testing parallel interfaces, such as DDR chips, where precise timing control between signals is crucial. Therefore, to achieve equal or fixed delays between I / O channels, the I / O channels need to be calibrated before the test equipment leaves the factory. This involves measuring the delays of sending signals to the DUT or receiving signals from the DUT and compensating for these delays in the signal transmission or reception circuitry to achieve synchronized signal transmission and reception between channels.

[0003] A common existing method for calibrating I / O channels is to design two calibration boards, such as... Figure 1 As shown, calibration board 1 is used to measure the signal delay in the transmission direction of the digital I / O channel. A TDC (Time-to-Digital Converter, a commonly used electronic circuit for measuring time intervals; common high-precision time measurement chips include TDC-GP2) chip is used on calibration board 1 to test different I / O channels. Figure 1 The numbers "1" and "2" in the test represent the signal delay between I / O channel 1 and I / O channel 2 on the test equipment, respectively. Calibration board 2 is used to measure the signal delay in the receiving direction of the digital I / O channels. A phase-aligned synchronization signal is emitted on calibration board 2 using a synchronization signal generator, and the signal delay in the receiving direction is measured by a TG (Timing Generator, typically implemented using an FPGA chip). Finally, delay compensation is performed based on the measured signal delays in both the transmitting and receiving directions between the I / O channels to achieve signal synchronization.

[0004] However, the existing I / O channel calibration methods described above have the following two technical problems:

[0005] 1. The calibration board design is complex. The number of TDC chips and synchronization signal generators on the calibration board is limited, and the number of channels on a single TDC chip and synchronization signal generator is also limited, typically 4, 8, or 16. Therefore, when there are many I / O channels, more TDC chips and synchronization signal generators need to be placed on the calibration board, increasing the design difficulty and manufacturing cost of the calibration board.

[0006] 2. Signal synchronization is also required between multiple TDC chips or multiple synchronization signal generators on the calibration board. This synchronization requires a unified reference source REF_CLK and requires one or more synchronization signal generators to distribute the signals to the TDC chips used to measure the delay or to the generators that generate the synchronization signals. Although the signals generated by each synchronization signal generator have relatively high synchronization, there is still a certain synchronization error. This error is amplified after being accumulated through multiple stages, affecting the calibration accuracy of the calibration board. Summary of the Invention

[0007] This invention provides a digital I / O channel calibration method for semiconductor testing equipment, aiming to solve the problem of signal asynchrony between I / O channels of testing equipment without increasing the design difficulty and manufacturing cost of the calibration board.

[0008] To achieve this objective, the present invention adopts the following technical solution:

[0009] A method for calibrating the digital I / O channels of a semiconductor test device is provided, comprising the following steps:

[0010] S1, group the digital I / O channels of the semiconductor test equipment into groups of at least 3, and then use the first calibration board to test and solve the signal transmission and reception delay between each digital I / O channel in each group;

[0011] S2, regroup each of the digital I / O channels in an "off" manner to establish a delay calculation relationship between the groups obtained in step S1, and then use the second calibration board to test and solve the signal transmission and reception delay between each of the digital I / O channels in each regrouped group.

[0012] S3, specify the signal delay of any of the digital I / O channels in the transmitting or receiving direction as the common variable in the delay calculation expression, construct the delay calculation expression for each of the digital I / O channels in the transmitting and receiving directions respectively, and solve it;

[0013] S4. Using the delay value obtained in step S3 as the compensation basis, delay compensation is performed on the corresponding digital I / O channel to achieve calibration and alignment of each digital I / O channel.

[0014] As a preferred embodiment of the present invention, in step S1, the digital I / O channels on the test device are divided into multiple groups of three.

[0015] As a preferred embodiment of the present invention, each of the digital I / O channels in each group obtained in step S1 has the same wiring length between the semiconductor test equipment and the first calibration board.

[0016] As a preferred embodiment of the present invention, the method for testing and solving the signal transmission and reception delay between each digital I / O channel in each group using the first calibration board or the second calibration board is expressed by the following formula (1):

[0017] D trij =Ti+Rj+2m formula (1)

[0018] In formula (1), D trij This indicates the signal reception delay from digital I / O channel i to digital I / O channel j within the same group;

[0019] Ti represents the delay of the digital I / O channel i in the signal transmission direction;

[0020] Rj represents the delay of the digital I / O channel j in the signal receiving direction;

[0021] m is the delay of the test signal from the connector to the PCB trace connection point on the first calibration board or the second calibration board.

[0022] As a preferred embodiment of the present invention, in step S2, the method for regrouping the groups obtained in step S1 using an error "1" method is as follows:

[0023] S21, Sort each group obtained in step S1;

[0024] S22, After completing the grouping and sorting, sort the digital I / O channels in each group to form an ordered sequence;

[0025] S23, starting from the second digital I / O channel in the sequence, the digital I / O channels of the semiconductor test equipment are regrouped into several groups.

[0026] As a preferred embodiment of the present invention, in step S23, starting from the second-ordered digital I / O channel in the sequence, each of the digital I / O channels of the semiconductor test device is regrouped into several groups using the same grouping unit as in step S1.

[0027] As a preferred embodiment of the present invention, in step S2, each of the digital I / O channels in each group obtained in an "off" manner has the same wiring length between the semiconductor test equipment and the second calibration board.

[0028] As a preferred embodiment of the present invention, in step S2, the digital I / O channels on the test device are regrouped into groups of three.

[0029] As a preferred embodiment of the present invention, the wiring length of the digital I / O channel between the semiconductor test equipment and the first calibration board includes the wiring length from the I / O interface of the semiconductor test equipment to the connector and the wiring length from the connector to the PCB trace connection point on the first calibration board.

[0030] Each of the I / O interfaces has the same wiring length to the connector, and each wire leading from the connector to the PCB trace connection point on the first calibration board has the same length.

[0031] As a preferred embodiment of the present invention, the wiring length of the digital I / O channel between the semiconductor test equipment and the second calibration board includes the wiring length from the I / O interface of the semiconductor test equipment to the connector and the wiring length from the connector to the PCB trace connection point on the second calibration board.

[0032] The wiring length from each I / O interface to the connector is the same, and the length of each wiring leading from the connector to the PCB trace connection point on the second calibration board is the same.

[0033] The digital I / O channel calibration method for semiconductor testing equipment provided by this invention is simple. Without increasing the design difficulty and manufacturing cost of the calibration board, it solves the problem of signal asynchrony between digital I / O channels of the testing equipment, and the calibration results are accurate and reliable. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0035] Figure 1 This is a schematic diagram illustrating the principle of existing methods for calibrating digital I / O channels;

[0036] Figure 2 This is a diagram illustrating the implementation steps of a digital I / O channel calibration method for a semiconductor testing device according to an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of the method of testing signal transmission and reception delay between digital I / O channels within a group and between digital I / O channels of different groups using two calibration boards according to the present invention;

[0038] Figure 4 This is a schematic diagram illustrating the method for testing signal transmission and reception delays between digital I / O channels within a test group. Detailed Implementation

[0039] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0040] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual images. They should not be construed as limiting the scope of this patent. To better illustrate the embodiments of the present invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0041] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0042] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" or similar designation indicating a connection between components should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0043] The implementation principle of the digital I / O channel calibration method for semiconductor test equipment provided in this embodiment of the invention is as follows: the digital I / O channels of the semiconductor test equipment (hereinafter referred to as the test equipment) are grouped into groups of at least three (preferably three), and two calibration boards (i.e., attached) are designed for testing the delay of the digital I / O channels. Figure 3The test setup includes calibration boards 1 and 2. Calibration board 1 is used to test the signal transmission and reception delays (delay between signal transmission and reception) between digital I / O channels within each group; calibration board 2 is used to test the signal transmission and reception delays between digital I / O channels in different groups. Then, the delay values ​​of all digital I / O channels in the signal transmission and reception directions are calculated using the signal transmission and reception delays measured by the two calibration boards. Finally, the calculated delay values ​​are used as the basis for compensation to perform delay compensation on the transmission and reception signals of each digital I / O channel, thereby achieving the purpose of calibrating and aligning the digital I / O channels.

[0044] Specifically, the digital I / O channel calibration method for semiconductor test equipment provided in this embodiment of the invention is as follows: Figure 2 As shown, it includes:

[0045] Step S1, place the semiconductor testing equipment (i.e., the attached...) Figure 3 The digital I / O channels of the “bidirectional I / O channel test resource board” (represented in the text) are grouped into groups of at least three, and then the first calibration board is used to test and solve the signal transmission and reception delay between each digital I / O channel in each group.

[0046] Grouping digital I / O channels into units of at least three facilitates subsequent calculations of delays in both the transmitting and receiving directions. As a preferred grouping method, all digital I / O channels of the test equipment are divided into several groups of three. Within each group, the three digital I / O channels are interconnected, for example, as shown in the attached diagram. Figure 3 The three digital I / O channels, channel 1, channel 2, and channel 3, represented by the numbers "1", "2", and "3", are interconnected. Similarly, the three digital I / O channels, channel 4, channel 5, and channel 6, represented by the numbers "4", "5", and "6", are also interconnected. Signals can be transmitted and received between the digital I / O channels within each group.

[0047] The difference in wiring length between the I / O interface of the test equipment and the calibration board can cause additional asynchrony in signal transmission and reception between channels. Therefore, to avoid this additional asynchrony, the wiring length between the test equipment and the calibration board for each digital I / O channel in each group should be equal. Figure 4 As shown, the wiring length of each digital I / O channel between the test equipment and the calibration board includes the wiring length from the I / O interface of the test equipment to the connector, and the wiring length from the connector to the PCB trace connection point on the calibration board. For more accurate signal synchronization, more preferably, the wiring length from each I / O interface on the test equipment to the connector is the same, and the length of each wire leading from the connector to the PCB trace connection point on the calibration board is also the same.

[0048] The specific method for testing and solving the signal transmission and reception delay between each digital I / O channel within each group using the first calibration board is as follows:

[0049] With attachment Figure 4 Taking digital I / O channels 1, 2, and 3 as an example, T1 represents the delay of channel 1 in the signal transmission direction. This delay does not include the delay of the signal from the connector to the PCB trace connection point on calibration board 1 (the same applies to R1, T2, R2, T3, and R3 below). R1 ​​is the delay of channel 1 in the signal reception direction; T2 is the delay of channel 2 in the signal transmission direction, and R2 is the delay of channel 2 in the signal reception direction; T3 is the delay of channel 3 in the signal transmission direction, and R3 is the delay of channel 2 in the signal reception direction; 'a' is the delay of the signal from the connector to the PCB trace connection point on calibration board 1. Since the wiring length from the connector to the PCB trace connection point on calibration board 1 is equal for the three digital I / O channels in the same group, the delay value 'a' of the three digital I / O channels in the same group is the same, and this fixed delay value 'a' can be obtained by measurement.

[0050] After measuring the delays T1, T2, and T3 of channels 1, 2, and 3 in the signal transmission direction, and the delays R1, R2, and R3 in the signal reception direction, and after setting a fixed delay value a, the signal transmission and reception delays between any two digital I / O channels within the same group are calculated using the following formula (1):

[0051] D trij =Ti+Rj+2a formula (1)

[0052] In formula (1), D trij This indicates the signal reception delay from channel i to channel j;

[0053] Ti represents the delay of channel i in the signal transmission direction;

[0054] Rj represents the delay of channel j in the signal receiving direction;

[0055] 'a' represents the delay of the signal from the connector to the PCB trace connection point on calibration board 1.

[0056] With attachment Figure 4 For example, the test signal is sent from channel 1 and received from channel 2. The signal transmission and reception delay D measured on the TG is... tr12 =T1+R2+2a;

[0057] The test signal is sent from channel 1 and received from channel 3. The signal transmission and reception delay D measured on the TG is... tr13 =T1 + R3 + 2a;

[0058] The test signal is sent from channel 2 and received from channel 1. The signal transmission and reception delay D measured on the TG is... tr21 =T2+R1+2a;

[0059] The test signal is sent from channel 2 and received from channel 3. The signal transmission and reception delay D measured on the TG is... tr23 =T2+R3+2a;

[0060] The test signal is sent from channel 3 and received from channel 1. The signal transmission and reception delay D measured on the TG is... tr31 =T3+R1+2a;

[0061] The test signal is sent from channel 3 and received from channel 2. The signal transmission and reception delay D measured on the TG is... tr32 =T3+R2+2a.

[0062] Then, according to D tr12 D tr13 D tr21 D tr23 D tr31 D tr32 This command specifies a common variable in the delay calculation expression for the signal delay of any digital I / O channel in either the transmitting or receiving direction, constructing delay calculation expressions for each digital I / O channel in both the transmitting and receiving directions. For example, specifying the delay R2 of channel 2 in the signal receiving direction as a common variable in the expression, the delay calculation expression for channel 1 in the signal transmitting direction is constructed as follows:

[0063] T1 = D tr12 -R2-2a;

[0064] The expression for calculating the delay of channel 2 in the signal transmission direction is constructed as follows:

[0065] T2 = D tr21 -(D tr31 -D tr32 +R2)-2a;

[0066] The expression for calculating the delay of channel 3 in the signal transmission direction is constructed as follows:

[0067] T3 = D tr32 -R2-2a;

[0068] The expression for calculating the delay of channel 1 in the signal receiving direction is as follows:

[0069] R1 = D tr31 -D tr32 +R2;

[0070] The expression for calculating the delay of channel 3 in the signal receiving direction is as follows:

[0071] R3=D tr13 -D tr12 +R2.

[0072] This gives us the delay values ​​of all three channels (channels 1, 2, and 3) in both the signal transmission and reception directions, with the signal delay R2 of channel 2 in the receiving direction as a common variable.

[0073] In order to establish the connection between the groups obtained in step S1 for delay calculation, such as Figure 2 As shown, the digital I / O channel calibration method for semiconductor test equipment provided in this embodiment further includes:

[0074] Step S2: Regroup each digital I / O channel in an "1" error manner to establish a delay calculation relationship between the groups obtained in step S1. Then, use the second calibration board to test and solve the signal transmission and reception delay between each digital I / O channel in each regrouped group.

[0075] Step S3: Specify the signal delay of any digital I / O channel in the transmitting or receiving direction as the common variable in the delay calculation expression, construct the delay calculation expression for each digital I / O channel in the transmitting and receiving directions respectively, and solve it;

[0076] Step S4: Using the delay value obtained in step S3 as the basis for compensation, delay compensation is performed on the corresponding digital I / O channel to achieve calibration and alignment of each digital I / O channel.

[0077] The following combination Figure 4 The method of regrouping using the incorrect "1" method is explained in detail below:

[0078] Figure 4 In the left diagram, interconnected channels 1, 2, and 3 form the first group obtained in step S1, and interconnected channels 4, 5, and 6 form the second group obtained in step S1. Assume that the delay calculation expressions for all three channels in the first group in both the signal transmission and reception directions use the signal delay R2 of channel 2 in the reception direction as a common variable, and the delay calculation expressions for all three channels in the second group use the signal delay R5 of channel 5 in the reception direction as a common variable. Since the signal transmission and reception delay calculation expressions for the digital I / O channels in the first and second groups use different common variables, it is impossible to directly solve for the signal transmission and reception delay between the digital I / O channels in the first and second groups. Therefore, to solve this problem, we establish a delay calculation relationship between the groups obtained in step S1 to achieve direct calculation of the signal delay between digital I / O channels in different groups.

[0079] To establish delay calculation connections between groups, we regrouped the groups obtained in step S1 using an error "1" method. The following is combined with... Figure 3 Explanation of the grouping method for incorrect "1":

[0080] First, sort each group obtained in step S1. For example, assuming there are 9 digital I / O channels on the test device, step S1 divides these 9 channels into 3 groups of 3, namely the first group, the second group, and the third group. We can sort the first group first, sort the second group after the first group, and sort the third group after the second group.

[0081] After grouping and sorting, sort the digital I / O channels in each group. For example, assign sort numbers 1, 2, and 3 to the three digital I / O channels in the first group, 4, 5, and 6 to the three digital I / O channels in the second group, and 7, 8, and 9 to the three digital I / O channels in the third group, forming the sorted sequence {1, 2, 3, 4, 5, 6, 7, 8, 9}.

[0082] Then, starting with the second-ranked digital I / O channel in the sequence, the digital I / O channels of the semiconductor test equipment are regrouped. For example, channels 2 and 3 in the first group and channel 4 in the second group are regrouped; channels 5 and 6 in the second group and channel 7 in the third group are regrouped; and channels 8 and 9 in the third group and channel 1 in the first group are regrouped.

[0083] After regrouping all digital I / O channels of the test equipment using this "wrong 1" method, a delay calculation relationship is established between the groups obtained in step S1.

[0084] After establishing the delay calculation connection between the groups obtained in step S1, the signal transmission and reception delay between each digital I / O channel in each reassigned group is tested and solved using the second calibration board. The solution method is consistent with the principle of the method for solving the signal transmission and reception delay between each digital I / O channel in each group obtained in step S1 using the first calibration board.

[0085] The following is in conjunction with the appendix Figure 3 A brief explanation of the method for testing and calculating the signal transmission and reception delays between digital I / O channels within each reassigned group using the second calibration board:

[0086] For example, attached Figure 3 The test signal transmitted by channel 3 shown is received by channel 2, and the delay D between transmission and reception is measured on TG. tr32 ′=T3+R2+2b, b represents the distance from the connector to the second calibration board (i.e. Figure 3 The delay of the PCB trace connection point on the calibration board 2). From step S1, we have already obtained: T3 = D tr32 -R²-2a, from which we can calculate 2b=D tr32 ′-D tr32 +2a.

[0087] If channel 4 sends a test signal and channel 2 receives it, the delay D between transmission and reception is measured on the TG. tr42 =T4 + R2 + 2b, since the formula for calculating 2b is known, we can calculate T4 = D. tr42 -(D tr32 ′-D tr32 +2a)-R2.

[0088] Through the above calculations, the connection between channels 1, 2, and 3 and channels 4, 5, and 6 is established. Based on the results obtained in step S1, the calculation expressions for the transmission delay and reception delay of channels 1-6 can be represented by the reception delay R2 of channel 2 as a common variable.

[0089] By continuing to test other groups and so on, expressions for calculating the delay of all channels in both the transmitting and receiving directions, with R2 as a common variable, can be obtained. Finally, solving each expression yields the delay value for each channel, and these calculated delay values ​​are used as the basis for delay compensation in inter-channel communication, thereby aligning the signals between channels in both the transmitting and receiving directions.

[0090] In summary, this embodiment designs a calibration board for digital I / O channels using a three-wire interconnection. By constructing and solving a delay calculation expression with common variables for each digital I / O channel, it not only reduces the design difficulty and manufacturing cost of the calibration board but also improves the calibration accuracy of the digital I / O channels.

[0091] It should be stated that the above-described specific embodiments are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art should understand that various modifications, equivalent substitutions, and variations can be made to the present invention. However, such variations, as long as they do not depart from the spirit of the present invention, should be within the scope of protection of the present invention. Furthermore, some terminology used in this specification and claims is not limiting, but merely for ease of description.

Claims

1. A method for calibrating digital I / O channels of a semiconductor test device, characterized in that the steps include... include: S1, group the digital I / O channels of the semiconductor test equipment into groups of at least 3, and then use the first calibration board to test and solve the signal transmission and reception delay between each digital I / O channel in each group; S2, regroup each of the digital I / O channels in an "1" error manner to establish a delay calculation relationship between the groups obtained in step S1, and then use the second calibration board to test and solve the signal transmission and reception delay between each of the digital I / O channels in each regrouped group; S3, specify the signal delay of any of the digital I / O channels in the transmitting or receiving direction as the common variable in the delay calculation expression, construct the delay calculation expression for each of the digital I / O channels in the transmitting and receiving directions respectively, and solve it; S4, using the delay value obtained in step S3 as the compensation basis, delay compensation is performed on the corresponding digital I / O channel to achieve calibration and alignment of each digital I / O channel; The method for testing and solving the signal transmission and reception delay between each digital I / O channel in each group using the first calibration board or the second calibration board is expressed by the following formula (1): In formula (1), Indicates the digital I / O channels within the same group Send to digital I / O channel Signal reception delay; Indicates the digital I / O channel Delay in the direction of signal transmission; Indicates the digital I / O channel Delay in the direction of signal reception; To test the delay of the signal from the connector to the PCB trace connection point on the first or second calibration board; In step S2, the method for regrouping the groups obtained in step S1 using the "1" error method is as follows: S21, Sort each group obtained in step S1; S22, After completing the grouping and sorting, sort the digital I / O channels in each group to form an ordered sequence; S23, starting from the second digital I / O channel in the sequence, the digital I / O channels of the semiconductor test equipment are regrouped into several groups; In step S2, each of the digital I / O channels in each group, which are assigned in an "off" manner, has the same wiring length between the semiconductor test equipment and the second calibration board.

2. The digital I / O channel calibration method for semiconductor testing equipment according to claim 1, characterized in that, In step S1, the digital I / O channels on the test device are divided into multiple groups of three.

3. The digital I / O channel calibration method for semiconductor testing equipment according to claim 1, characterized in that, In step S1, each of the digital I / O channels in each group has the same wiring length between the semiconductor test equipment and the first calibration board.

4. The digital I / O channel calibration method for semiconductor testing equipment according to claim 1, characterized in that, In step S23, starting with the second-ordered digital I / O channel in the sequence, the digital I / O channels of the semiconductor test device are regrouped into several groups using the same grouping unit as in step S1.

5. The digital I / O channel calibration method for semiconductor testing equipment according to claim 1, characterized in that, In step S2, the digital I / O channels on the test device are regrouped into groups of three.

6. The digital I / O channel calibration method for semiconductor testing equipment according to claim 3, characterized in that, The wiring length of the digital I / O channel between the semiconductor test equipment and the first calibration board includes the wiring length from the I / O interface of the semiconductor test equipment to the connector and the wiring length from the connector to the PCB trace connection point on the first calibration board. Each of the I / O interfaces has the same wiring length to the connector, and each wire leading from the connector to the PCB trace connection point on the first calibration board has the same length.

7. The digital I / O channel calibration method for semiconductor testing equipment according to claim 1, characterized in that, The wiring length of the digital I / O channel between the semiconductor test equipment and the second calibration board includes the wiring length from the I / O interface of the semiconductor test equipment to the connector and the wiring length from the connector to the PCB trace connection point on the second calibration board. The wiring length from each I / O interface to the connector is the same, and the length of each wiring leading from the connector to the PCB trace connection point on the second calibration board is the same.

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