A method for SPI device clock correction

Abstract

This invention proposes a method for clock calibration of an SPI device, comprising the following steps: Step 1: When the master device in the SPI device performs a write operation, the master device pulls the CSN signal low and provides 48 consecutive SCK clock signals; after the slave device detects that the CSN signal is low, it starts counting from the rising edge of the first SCK clock signal, and the counter starts counting from 0; the counting frequency is the high-frequency clock f inside the slave device. HSI When the slave device detects the 48th SCK clock signal, the counter stops counting and stores the count value CNT in the slave device's register; Step 2: The master device reads the count value CNT held in the slave device's counter register; Step 3: Calculate the slave device's system clock f based on the count value. HSI Step 4: The master device writes the correction compensation value, i.e., the correction frequency mentioned in step 3, into the corresponding address of the slave device's register to complete the clock correction.

Description

Technical Field

[0001] This invention relates to a clock calibration method, and more particularly to a clock calibration method for an SPI device. Background Technology

[0002] In chips without crystal oscillators, the system clock is usually provided by an internal RC oscillator circuit. However, the internal RC has low accuracy and large deviation with temperature changes. If it is not corrected in time, it will affect the operation. For example, if the baud rate of UART (Universal Asynchronous Receiver / Transmitter) is inaccurate, it will be unable to send or receive data.

[0003] High-speed internal clock signals (HSI) start up faster than high-speed external clock signals (HSE) crystal oscillators, but their accuracy, even after calibration, is still lower than that of external crystal oscillators or ceramic resonators. HSI also deviates significantly with temperature changes; therefore, HSI is generally used as a backup clock in integrated circuit design.

[0004] In chips without crystal oscillators, the HSI (Hardware Self-Device) is used as the master clock. This solution proposes a method to calibrate the HSI clock, enabling the chip to function properly.

[0005] In existing technologies, the internal high-frequency RC (HSI) is generally used as a backup clock, while the chip uses an external high-frequency crystal oscillator as the master clock, and the HSI is also corrected using the external high-frequency clock. However, for chips used in crystal-free applications, since no external high-frequency crystal oscillator is provided, it is impossible to use an external high-frequency crystal oscillator to correct the internal HSI. Summary of the Invention

[0006] Purpose of the invention: The technical problem to be solved by the present invention is to provide a method for clock correction of SPI devices, which addresses the shortcomings of the prior art.

[0007] To address the aforementioned technical problems, this invention discloses a method for clock calibration of an SPI device, comprising the following steps:

[0008] Step 1: When the master device in the SPI device performs a write operation, the master device pulls the CSN signal low and provides 48 consecutive SCK clock signals;

[0009] After the device detects that the CSN signal is low, the counter starts counting from the rising edge of the first SCK clock signal, starting from 0; the counting frequency is the internal high-frequency clock f of the device. HSI;

[0010] When the slave device detects the 48th SCK clock signal, the counter stops counting and stores the count value CNT in the slave device's register;

[0011] Step 2: The master device reads the count value CNT held in the slave device's count register;

[0012] Step 3: Calculate the slave device system clock f based on the count value. HSI The specific method is as follows:

[0013]

[0014] Among them, f SCK This represents the frequency of the SCK clock signal; given that the design value of the high-speed internal clock signal HSI of the slave device is 6.5536MHz, the calculation method for the correction frequency Δf is as follows:

[0015] Δf=f HSI -6553600

[0016] Step 4: The master device writes the correction compensation value, i.e., the correction frequency Δf mentioned in step 3, into the corresponding address of the slave device's register to complete the clock correction.

[0017] Beneficial effects:

[0018] The proposed solution can calibrate the internal HSI via SPI communication without the need for an external high-frequency crystal oscillator. Attached Figure Description

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0020] Figure 1 This is a schematic diagram of the signal timing in this invention.

[0021] Figure 2 A schematic diagram of the communication protocol for SPI write operations.

[0022] Figure 3 This is a schematic diagram of the SPI read operation communication protocol.

[0023] Figure 4 This is a diagram showing the connection of an SPI device. Detailed Implementation

[0024] A method for clock calibration of an SPI device, characterized by comprising the following steps:

[0025] Step 1: When the master device in the SPI (Serial Peripheral Interface) device performs a write operation, the master device pulls the CSN signal low and provides 48 consecutive SCK clock signals; the signal timing is as follows. Figure 1 As shown;

[0026] After the device detects that the CSN signal is low, the counter starts counting from the rising edge of the first SCK clock signal, starting from 0; the counting frequency is the internal high-frequency clock f of the device. HSI ;

[0027] When the slave device detects the 48th SCK clock signal, the counter stops counting and stores the count value CNT in the slave device's register;

[0028] Step 2: The master device reads the count value CNT held in the slave device's count register;

[0029] Step 3: Calculate the slave device system clock f based on the count value. HSI The specific method is as follows:

[0030]

[0031] Among them, f SCK This represents the frequency of the SCK clock signal; given that the design value of the high-speed internal clock signal HSI of the slave device is 6.5536MHz, the calculation method for the correction frequency Δf is as follows:

[0032] Δf=f HSI -6553600

[0033] Step 4: The master device writes the correction compensation value, i.e., the correction frequency Δf mentioned in step 3, into the corresponding address of the slave device's register to complete the clock correction.

[0034] The SPI device includes a master device and a slave device. Both the master and slave devices have four pins for signal transmission. The device connections are as follows: Figure 4 As shown, where:

[0035] MISO pin: Master input or slave output pin; this pin is used to send data in the slave device and receive data in the master device.

[0036] MOSI pin: Master output or slave input pin; this pin sends data in the master device and receives data in the slave device.

[0037] SCK pin: Serial clock, used as the output of the master device and the input of the slave device;

[0038] CSN pin: Select from device.

[0039] The device includes registers for storing the count value CNT and the correction compensation value Δf.

[0040] In step 1, when the master device in the SPI device performs a write operation, if the slave device receives the sixth byte (checksum) and the checksum fails, frequency correction is not performed.

[0041] In step 3, when calculating the correction frequency, the main equipment determines the deviation range of the correction compensation value and does not compensate for deviations greater than the set threshold.

[0042] The threshold set in step 3 is 4% of 6553600.

[0043] When writing to the corresponding address of the slave device's register as described in step 4, the highest bit in the corresponding address of the register represents the positive or negative sign bit.

[0044] When the master device wants to write to the device's registers, the communication protocol is as follows: Figure 2 As shown, the master device continuously sends 6 bytes of data. The first byte is the slave device's target register address, the second to fifth bytes are the target register data, and the sixth byte is the checksum of the sent data.

[0045] When the master device reads from the slave device's register, the communication protocol is as follows: Figure 3 As shown, the master device sends the target address of the slave device register to be read. After receiving the read instruction, the slave device sends 4 bytes of data and 1 byte of checksum.

[0046] When the master device performs a read or write operation to the slave device's register, it transmits communication signals through the MOSI pin.

[0047] Example:

[0048] This solution designs a proprietary protocol that allows the master device to read and write the slave device's registers, thereby correcting the slave device's internal RC oscillator parameters.

[0049] When the master device performs a write operation to the slave device's register, it uses the SPI write operation communication protocol, such as... Figure 2 As shown: The master device continuously sends 6 bytes of data through the MOSI pin. The first byte is the slave device's target register address, the second to fifth bytes are the target register data, and the sixth byte is the checksum of the sent data.

[0050] The bytes specified in the write operation communication protocol (only the data bits B7:B0 of each byte are listed) are shown in Table 1:

[0051] Table 1 Master Device Write Data Frame Structure Table

[0052]

[0053] When the master device performs a read operation on the slave device's register, it uses the SPI read operation communication protocol, such as... Figure 3 As shown: First, the master device sends the address of the slave device's target register to be read via MOSI. After receiving the read instruction, the slave device sends 4 bytes of data and 1 byte of checksum via MISO.

[0054] When performing the above read operation, design the command frame structure sent by the master device to the slave device (only the data bits B7:B0 of each byte are listed). The data frame structure on the MOSI signal line during the master device read operation is shown in Table 2:

[0055] Table 2. MOSI Signal Line Command Data Frame Structure Table

[0056]

[0057] When performing a read operation, design the response frame structure sent from the slave device to the master device (only the data bits B7:B0 of each byte are listed). When the master device performs a read operation, the response data frame structure on the MISO signal line is shown in Table 3:

[0058] Table 2. Structure of MOSI Signal Line Response Data Frame

[0059]

[0060] like Figure 4 As shown, SPI devices typically connect to external devices via 4 pins:

[0061] MISO: Master Input / Slave Output pin. This pin sends data in slave mode and receives data in master mode.

[0062] MOSI: Master Output / Slave Input pin. This pin sends data in master mode and receives data in slave mode.

[0063] SCK: Serial clock, used as the output of the master device and the input of the slave device.

[0064] CSN: Select from the device.

[0065] Calibration process:

[0066] 1. For each master device write operation, the master device pulls the CSN signal low and provides 48 SCK clock signals, with the signal timing as follows: Figure 1 As shown.

[0067] After the device detects that the CSN signal is low, counting begins on the first rising edge of the SCK signal, with the counter starting from 0. The counting frequency is the device's internal high-frequency clock frequency f. HSI .

[0068] When the 48th SCK clock cycle is detected, the counter stops counting and stores the count value CNT in the register.

[0069] 2. The master device reads the slave device counter register;

[0070] 3. Calculate the slave device system clock based on the count value.

[0071]

[0072] Given that the HSI design value of the device is 6.5536MHz, the correction frequency is Δf = f HSI -6556600

[0073] 4. The master device writes the correction compensation value to the corresponding register address of the slave device, where the highest bit represents the positive or negative sign bit.

[0074] Frequency correction will not be performed if the sixth byte checksum received from the device is incorrect.

[0075] In addition, the main equipment determines the deviation range of the compensation value, and will not compensate for deviations greater than 4%.

[0076] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the invention's content regarding an SPI device clock correction method and some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0077] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MUU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0078] This invention provides a method for clock correction of SPI devices. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A method of SPI device clock correction, the method comprising: Includes the following steps: Step 1: When the master device in the SPI device performs a write operation, the master device pulls the CSN signal low and provides 48 consecutive SCK clock signals; After the device detects that the CSN signal is low, it starts counting from the rising edge of the first SCK clock signal, and the counter starts counting from 0. The count frequency is from the device system clock ; When the slave device detects the 48th SCK clock signal, the counter stops counting and stores the count value CNT in the slave device's register; Step 2: The master device reads the count value CNT held in the slave device's count register; Step 3. Calculate the slave system clock from the count value The specific method is as follows: ； Wherein, represents the frequency of the SCK clock signal; it is known that the high-speed internal clock signal HSI frequency design value of the slave device is 6.5536 MHz, so the correction frequency The calculation method is: ； Step 4, the master device writes the correction compensation value, i.e. the correction frequency described in step 3, into the corresponding address of the register of the slave device, completing the clock correction described. , writes the correction compensation value, i.e. the correction frequency described in step 3, into the corresponding address of the register of the slave device, completing the clock correction described.

2. The method of SPI device clock correction according to claim 1, wherein, The SPI device includes a master device and a slave device. Both the master and slave devices have four pins for signal transmission, wherein: MISO pin: Master input or slave output pin; this pin is used to send data in the slave device and receive data in the master device. MOSI pin: Master output or slave input pin; this pin sends data in the master device and receives data in the slave device. SCK pin: Serial clock, used as the output of the master device and the input of the slave device; CSN pin: Select from device.

3. The method of SPI device clock correction according to claim 2, wherein, The device includes a register for storing the count value CNT and the correction frequency. .

4. The method of SPI device clock correction according to claim 3, wherein, In step 1, when the master device in the SPI device performs a write operation, if the slave device receives the sixth byte (checksum) and the checksum fails, frequency correction is not performed.

5. The method of SPI device clock correction according to claim 4, wherein, In step 3, when calculating the correction frequency, the main equipment determines the deviation range of the correction compensation value and does not compensate for deviations greater than the set threshold.

6. The method of SPI device clock correction according to claim 5, wherein, The set threshold value is 4%.

7. The method of SPI device clock correction according to claim 6, wherein, When writing to the corresponding address of the slave device's register as described in step 4, the highest bit in the corresponding address of the register represents the positive or negative sign bit.

8. The method of SPI device clock correction according to claim 7, wherein, When the master device wants to write to the slave device's register, the master device sends 6 bytes of data consecutively. The first byte is the slave device's target register address, the second to fifth bytes are the target register data, and the sixth byte is the checksum of the sent data.

9. A method for clock correction of an SPI device according to claim 8, characterized in that, When the master device performs a read operation on the slave device's register, the master device sends the target address of the slave device's register to be read. After receiving the read instruction, the slave device sends 4 bytes of data and 1 byte of checksum.

10. The method of SPI device clock correction according to claim 9, wherein, When the master device performs a read or write operation to the slave device's register, it transmits communication signals through the MOSI pin.

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