Semiconductor memory device

Abstract

Embodiments of the present invention provide a semiconductor memory device capable of stably outputting read data. The sequencer (41) of the semiconductor memory device (2) of the present invention sends irregular data (different from the data requested by the memory controller (1) as data corresponding to each read signal initially received a specified number of times from the second storage unit (520) to the output unit, and sends the data requested by the memory controller (1), i.e., regular data, as data corresponding to subsequently received read signals, from the second storage unit (520) to the output unit. The sequencer (41) sends irregular data from the second storage unit (520) by pre-adjusting the read pointer (Rptr) according to the specified number of times, the read pointer (Rptr) indicating the storage position of the data to be sent to the output unit next among the multiple data stored in the second storage unit (520).

Description

[0001] [Related Applications]

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-043340 (filed on March 18, 2022). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] For example, semiconductor memory devices such as NAND (Not And) flash memory output read data based on signals sent from the memory controller. Summary of the Invention

[0005] According to the disclosed embodiments, a semiconductor storage device capable of stably outputting read data is provided.

[0006] The semiconductor memory device of the embodiment includes: a memory cell array for storing data; a storage unit for temporarily storing a plurality of data read from the memory cell array; an output unit for outputting data repeatedly sent from the storage unit to an external memory controller; a receiving unit for repeatedly receiving read signals from the memory controller to read data; and a control unit for sending data from the storage unit to the output unit in response to each read signal. The control unit sends irregular data, which differs from the data requested by the memory controller, as data corresponding to each read signal initially received by the receiving unit a specified number of times, from the storage unit to the output unit. It also sends regular data, which is the data requested by the memory controller, as data corresponding to read signals subsequently received by the receiving unit, from the storage unit to the output unit. The control unit sends irregular data from the storage unit by pre-adjusting a read pointer according to a specified number of times, the read pointer indicating the storage position of the data to be sent to the output unit next among the plurality of data stored in the storage unit. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a storage system in an implementation method.

[0008] Figure 2 This is a block diagram illustrating an example of the configuration of a storage system in an implementation method.

[0009] Figure 3 This is a block diagram illustrating the configuration of a semiconductor memory device according to an implementation method.

[0010] Figure 4 It is an equivalent circuit diagram representing the structure of a memory cell array.

[0011] Figure 5 It is a cross-sectional view showing the structure of a storage cell array.

[0012] Figure 6 This is a diagram showing the circuit configuration of the sensing amplification unit.

[0013] Figure 7 This is a diagram illustrating an example of the threshold distribution of a memory cell transistor.

[0014] Figure 8 It is a graph showing the potential changes of each wiring during a write operation.

[0015] Figure 9 It is a graph showing the potential changes of each wiring during the readout operation.

[0016] Figure 10 This is a diagram illustrating an example of the time variation of signals transmitted and received between the semiconductor memory device and the memory controller in the comparative example.

[0017] Figure 11 This is a diagram illustrating an example of the time variation of signals transmitted and received between a semiconductor memory device and a memory controller in another comparative example.

[0018] Figure 12 This is a diagram illustrating an example of the time variation of signals transmitted and received between the semiconductor memory device and the memory controller in an embodiment.

[0019] Figure 13 This is a diagram illustrating the configuration of a circuit used to output data from a memory cell array to a memory controller in a storage system according to an implementation method.

[0020] Figure 14 This is a diagram showing the structure of the storage unit.

[0021] Figure 15 (A) Figure 15 (B) in the diagram is used to illustrate the adjustment of the read pointer.

[0022] Figure 16 This is a diagram illustrating an example of the time variation of signals transmitted and received between the semiconductor memory device and the memory controller in an embodiment.

[0023] Figure 17 This is a diagram showing the configuration of the circuit used to output data from the memory cell array to the memory controller in a comparative example memory system.

[0024] Figure 18 This is a graph showing the relationship between the data stored in the trigger circuit of the second storage unit and the data output from the second storage unit during the delay period.

[0025] Figure 19This is a graph showing the relationship between the data stored in the trigger circuit of the second storage unit and the data output from the second storage unit during the data output period after the delay period ends.

[0026] Figure 20 This is a graph showing the relationship between the data stored in the trigger circuit of the second storage unit and the data output from the second storage unit during the data output period after the delay period ends.

[0027] Figure 21 This is a diagram illustrating the configuration of a circuit used to output data from a memory cell array to a memory controller in a storage system of a variation example. Detailed Implementation

[0028] Hereinafter, this embodiment will be described with reference to the accompanying drawings. To facilitate understanding, the same symbols will be used to label the same components in each drawing as much as possible, and repeated descriptions will be omitted.

[0029] The semiconductor memory device 2 in this embodiment is a non-volatile memory device configured as a NAND flash memory. Figure 1 The diagram below shows an example of a memory system configuration including a semiconductor memory device 2. The memory system includes a memory controller 1 and a semiconductor memory device 2.

[0030] Furthermore, in practical storage systems, such as Figure 2 As shown, a memory controller 1 is provided with multiple semiconductor memory devices 2. Figure 1 The diagram shows only one of the multiple semiconductor memory devices 2. The specific configuration of the semiconductor memory device 2 will be described below.

[0031] This storage system can be connected to a host device (not shown). The host device could be an electronic device such as a personal computer or a mobile terminal. The memory controller 1 controls the writing of data to the semiconductor storage device 2 according to write requests from the host. Additionally, the memory controller 1 controls the reading of data from the semiconductor storage device 2 according to read requests from the host.

[0032] The memory controller 1 and the semiconductor storage device 2 transmit and receive various signals, including chip enable signal / CE, ready-busy signal R / B, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protection signal / WP, data signal DQ<7:0>, data strobe signal DQS, and / DQS.

[0033] The chip enable signal / CE is used to enable semiconductor memory device 2. The ready-busy signal R / B is used to indicate whether semiconductor memory device 2 is in a ready or busy state. A "ready state" means it can accept commands from external sources. A "busy state" means it cannot accept commands from external sources.

[0034] like Figure 2 As shown, a chip enable signal / CE is sent individually to each of the multiple semiconductor memory devices 2. Figure 2 In order to distinguish the enable signals / CE of each chip from one another, a number is marked at the end, such as " / CE0".

[0035] Similarly, a ready-to-work signal R / B is sent individually from each of the multiple semiconductor memory devices 2. Figure 2 In order to distinguish the various ready and busy signals R / B from each other, a number is marked at the end, such as "R / B0".

[0036] Signals other than the chip enable signal / CE and the ready / busy signal R / B (such as the instruction latch enable signal CLE) are transmitted and received between the memory controller 1 and the semiconductor memory devices 2 via a common signal line shared by multiple semiconductor memory devices 2. The memory controller 1 uses an individual chip enable signal / CE to identify the semiconductor memory device 2 as the communication target.

[0037] The instruction latch enable signal CLE indicates that the signals DQ<7:0> represent instructions. The address latch enable signal ALE indicates that the signals DQ<7:0> represent addresses. The write enable signal / WE is used to fetch received signals to the semiconductor memory device 2. Whenever an instruction, address, or data is received, the memory controller 1 asserts it. The memory controller 1 instructs the semiconductor memory device 2 to fetch the signals DQ<7:0> during the period when the signal / WE is at the "L" level.

[0038] The read enable signal / RE is used to enable the memory controller 1 to read data from the semiconductor memory device 2. Signal RE is the complementary signal to signal / RE. They are used, for example, to control the timing of the operation of the semiconductor memory device 2 when outputting signals DQ<7:0>. The write protect signal / WP is used to instruct the semiconductor memory device 2 to prohibit data writing and deletion. Signals DQ<7:0> are the entities of data transmitted and received between the semiconductor memory device 2 and the memory controller 1, including instructions, addresses, and data. The data strobe signal DQS is used to control the input / output timing of signals DQ<7:0>. Signal / DQS is the complementary signal to signal DQS.

[0039] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0040] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Additionally, the host interface 13 sends user data read from the semiconductor storage device 2, responses from the processor 12, etc., to the host.

[0041] The memory interface 15 controls, based on instructions from the processor 12, processes such as writing user data to the semiconductor storage device 2 and reading user data from the semiconductor storage device 2.

[0042] Processor 12 provides overall control of memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Upon receiving a request from the host via host interface 13, processor 12 performs control according to that request. For example, processor 12, upon receiving a request from the host, instructs memory interface 15 to write user data and parity check codes to semiconductor storage device 2. Additionally, processor 12, upon receiving a request from the host, instructs memory interface 15 to read user data and parity check codes from semiconductor storage device 2.

[0043] Processor 12 determines the storage area (storage area) on semiconductor memory device 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the storage area for data in page units (page data) as write units. User data stored in one page of semiconductor memory device 2 is hereinafter also referred to as "cell data". Cell data is generally encoded and stored in semiconductor memory device 2 in codeword form. In this embodiment, encoding is not mandatory. Memory controller 1 may also store cell data in semiconductor memory device 2 without encoding, but... Figure 1 The example shown is an encoding configuration. When the memory controller 1 does not perform encoding, the page data and the cell data are identical. Furthermore, a codeword can be generated based on a single cell data unit, or based on segmented data formed by dividing the cell data. Additionally, a codeword can be generated using multiple cell data units.

[0044] Processor 12 determines the storage region of semiconductor memory device 2 as the write destination on a unit-by-unit basis. The storage regions of semiconductor memory device 2 are assigned physical addresses. Processor 12 uses physical addresses to manage the storage regions as write destinations for unit-by-unit data. Processor 12 specifies the determined storage region (physical address) and instructs memory interface 15 to write user data to semiconductor memory device 2. Processor 12 manages the correspondence between the logical address (the logical address managed by the host) of user data and its physical address. Upon receiving a read request containing a logical address from the host, processor 12 specifies the physical address corresponding to the logical address and instructs memory interface 15 to read the user data.

[0045] The ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Additionally, the ECC circuit 14 decodes the codewords read from the semiconductor memory device 2. The ECC circuit 14 uses, for example, a checksum assigned to the user data to detect and correct errors in the data.

[0046] RAM11 temporarily stores user data received from the host until it needs to be stored in the semiconductor memory device 2, or temporarily stores data read from the semiconductor memory device 2 until it needs to be sent to the host. RAM11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0047] Figure 1 The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can be integrated into the semiconductor memory device 2. Figure 1 The specific composition and configuration of the elements shown are not particularly limited.

[0048] In the event that a write request is received from the host Figure 1 The storage system operates as follows: Processor 12 temporarily stores the data to be written into RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it into ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword into memory interface 15. Memory interface 15 writes the input codeword into semiconductor memory device 2.

[0049] In the event that a read request is received from the host Figure 1The storage system operates as follows: The memory interface 15 inputs the codewords read from the semiconductor storage device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codewords and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0050] The configuration of semiconductor memory device 2 will be described. For example... Figure 3 As shown, the semiconductor memory device 2 includes two memory planes PL1 and PL2, an input / output circuit 21, a logic control circuit 22, a sequencer 41, a register 42, a voltage generation circuit 43, an input / output pad group 31, a logic control pad group 32, and a power input terminal group 33.

[0051] The memory surface PL1 includes a memory cell array 110, a sense amplifier 120, and a row decoder 130. The memory surface PL2 includes a memory cell array 210, a sense amplifier 220, and a row decoder 230. The configurations of memory surface PL1 and memory surface PL2 are identical. That is, the configurations of memory cell array 110 and 210 are identical, the configurations of sense amplifier 120 and 220 are identical, and the configurations of row decoder 130 and 230 are identical. The number of memory surfaces provided in the semiconductor memory device 2 can be two, one, or three or more, as shown in this embodiment.

[0052] Memory cell arrays 110 and 210 are the data storage portions. Each of memory cell arrays 110 and 210 contains multiple memory cell transistors associated with word lines and bit lines. Their specific configuration will be described below.

[0053] The input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with the memory controller 1. The input / output circuit 21 transmits the instructions and address contained in the signals DQ<7:0> to the register 42. Additionally, the input / output circuit 21 transmits and receives write data and read data with the sense amplifier 120 or sense amplifier 220. The input / output circuit 21 has two functions: receiving instructions from the memory controller 1 as an "input circuit" and outputting data to the memory controller 1 as an "output circuit." Alternatively, different circuit configurations for the input and output circuits can be used instead of the configuration described above.

[0054] The logic control circuit 22 receives the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protect signal / WP from the memory controller 1. Additionally, the logic control circuit 22 transmits the ready-busy signal R / B to the memory controller 1, thus notifying the outside world of the status of the semiconductor memory device 2.

[0055] Both the input / output circuit 21 and the logic control circuit 22 are configured as circuits that can input and output signals with the memory controller 1. In other words, both the input / output circuit 21 and the logic control circuit 22 are provided as interface circuits for the semiconductor memory device 2.

[0056] The sequencer 41 controls the operation of various components, such as memory surfaces PL1 and PL2 and voltage generation circuit 43, based on control signals input from memory controller 1 to semiconductor memory device 2. The sequencer 41 controls the operation of memory cell arrays 110 and 210, and is equivalent to the "control unit" of semiconductor memory device 2. The sequencer 41 and logic control circuit 22 can also be considered as the "control unit".

[0057] Register 42 is the part that temporarily stores instructions and addresses. Register 42 also stores status information indicating the respective states of memory planes PL1 and PL2. The status information is output as a status signal from input / output circuit 21 to memory controller 1 upon request from memory controller 1.

[0058] The voltage generation circuit 43 generates the voltages required for write, read, and delete operations of data in the memory cell arrays 110 and 210, based on instructions from the sequencer 41. These voltages include, for example, the voltages VPGM, VPASS_PGM, and VPASS_READ applied to the word line WL, and the voltage applied to the bit line BL. The voltage generation circuit 43 can individually apply voltages to each word line WL and bit line BL, enabling memory surfaces PL1 and PL2 to operate in parallel.

[0059] The input / output pad group 31 is a part that has multiple terminals (pads) for transmitting and receiving signals between the memory controller 1 and the input / output circuit 21. Each terminal is individually configured to correspond to the signal DQ<7:0> and the data strobe signals DQS and / DQS respectively.

[0060] The logic control pad group 32 is a portion provided with multiple terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 22. Each terminal is individually configured to correspond to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protect signal / WP, and ready-busy signal R / B, respectively.

[0061] The power input terminal group 33 is a portion provided with multiple terminals for receiving the applied voltages required for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltages Vcc, VccQ, Vpp, and the ground voltage Vss.

[0062] The power supply voltage Vcc is the circuit power supply voltage provided externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is the voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0063] Writing or deleting data to or from memory cell arrays 110 and 210 requires a voltage of approximately 20V (VPGM). In this case, boosting the approximately 12V power supply voltage Vpp via the boost circuit of voltage generation circuit 43, compared to boosting the approximately 3.3V power supply voltage Vcc, allows for faster and lower power consumption to generate the desired voltage. On the other hand, if the semiconductor memory device 2 is used in an environment where a high voltage cannot be supplied, then a voltage supply to the power supply voltage Vpp may not be required. Even without a power supply voltage Vpp, the semiconductor memory device 2 can perform various operations as long as it is supplied with the power supply voltage Vcc. In other words, the power supply voltage Vcc is the standard power supply required to be supplied to the semiconductor memory device 2, while the power supply voltage Vpp is an additional, arbitrary power supply supplied depending on, for example, the operating environment.

[0064] The configurations of memory planes PL1 and PL2 will be explained. Furthermore, as mentioned above, the configurations of memory plane PL1 and PL2 are identical. Therefore, only the configuration of memory plane PL1 will be explained below; illustrations and explanations regarding the configuration of memory plane PL2 will be omitted.

[0065] Figure 4 The equivalent circuit diagram shows the configuration of the memory cell array 110 disposed on the memory plane PL1. The memory cell array 110 contains multiple blocks BLK, but... Figure 4 The diagram only shows one block BLK. The other block BLKs in the storage cell array 110 are configured similarly to... Figure 4 The structures shown are the same.

[0066] like Figure 4 As shown, a block BLK contains, for example, four string units SU (SU0 to SU3). Each string unit SU contains multiple NAND strings NS. Each NAND string NS contains, for example, eight memory cell transistors MT (MT0 to MT7), and select transistors ST1 and ST2.

[0067] Furthermore, the number of memory cell transistors MT is not limited to 8; for example, it can also be 32, 48, 64, or 96. For instance, to improve cut-off characteristics, selection transistors ST1 and ST2 can each be composed of multiple transistors instead of a single transistor. Moreover, dummy cell transistors can also be placed between the memory cell transistor MT and the selection transistors ST1 and ST2.

[0068] The memory cell transistor MT is connected in series between the select transistor ST1 and the select transistor ST2. The memory cell transistor MT7 on one side is connected to the source of the select transistor ST1, and the memory cell transistor MT0 on the other side is connected to the drain of the select transistor ST2.

[0069] The gates of the select transistor ST1 for each of the serial cells SU0 to SU3 are all connected to the selectable gate lines SGD0 to SGD3. The gates of the select transistor ST2 are all connected to the same selectable gate line SGS among multiple serial cells SU located in the same BLK. The gates of the memory cell transistors MT0 to MT7 located in the same BLK are all connected to the word lines WL0 to WL7. That is to say, the word lines WL0 to WL7 and the selectable gate line SGS are common among multiple serial cells SU0 to SU3 in the same BLK, while the selectable gate line SGD is set individually for each of the serial cells SU0 to SU3, even within the same BLK.

[0070] The memory cell array 110 has m bit lines BL (BL0, BL1, ..., BL(m-1)). "m" is an integer representing the number of NAND strings NS contained in one string cell SU. In each NAND string NS, the drain of the select transistor ST1 is connected to the corresponding bit line BL. The source of the select transistor ST2 is connected to the source line SL. The source line SL is a common connection relative to the sources of the multiple select transistors ST2 in the block BLK.

[0071] Data stored in multiple memory cell transistors MT located within the same BLK is deleted all at once. On the other hand, data reading and writing are performed simultaneously on multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU. Each memory cell can store 3 bits of data consisting of the upper bit, the middle bit, and the lower bit.

[0072] In other words, the semiconductor memory device 2 of this embodiment uses a TLC (Triple Level Cell) method, which stores 3 bits of data in one memory cell transistor MT, as the method for writing data to the memory cell transistor MT. Alternatively, a MLC (Multi Level Cell) method, which stores 2 bits of data in one memory cell transistor MT, can also be used to write data to the memory cell transistor MT, thus replacing the state described above. The number of bits of data stored in one memory cell transistor MT is not particularly limited.

[0073] Furthermore, in the following explanation, the collection of 1-bit data stored by multiple memory cell transistors MT connected to a word line WL and belonging to a string unit SU is called a "page". Figure 4 In the text, one of the sets consisting of multiple memory cell transistors MT as described above is labeled with the symbol "MG".

[0074] As shown in this embodiment, when 3 bits of data are stored in one memory cell transistor MT, a set of multiple memory cell transistors MT connected to a common word line WL within one string cell SU can store 3 pages of data. The page consisting of the set of lower-order bits is also called the "lower page," and the data of the lower page is also called the "lower page data." Similarly, the page consisting of the set of middle-order bits is also called the "middle page," and the data of the middle page is also called the "middle page data." The page consisting of the set of upper-order bits is also called the "upper page," and the data of the upper page is also called the "upper page data."

[0075] Figure 5 The diagram shows the configuration of the memory cell array 110 and its surroundings in a schematic cross-sectional view. As shown, multiple NAND strings NS are formed on the conductor layer 320 within the memory cell array 110. The conductor layer 320, also known as the embedded source line (BSL), is equivalent to... Figure 4 The source line SL.

[0076] Above the conductor layer 320, the stacked layer includes multiple wiring layers 333 that function as optional gate lines (SGS), multiple wiring layers 332 that function as word lines (WL), and multiple wiring layers 331 that function as optional gate lines (SGD). An insulating layer (not shown) is disposed between the wiring layers 333, 332, and 331 of the stacked layer.

[0077] Multiple storage vias 334 are formed in the storage cell array 110. Each storage via 334 is a hole that penetrates the wiring layers 333, 332, and 331 and the insulating layer (not shown) located between them in the vertical direction, reaching the conductor layer 320. A bulk insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side of each storage via 334, and a conductive pillar 338 is embedded inside it. The conductive pillar 338 is formed, for example, of polysilicon, and functions as a channel forming area when the storage cell transistors MT and select transistors ST1 and ST2 in the NAND string NS are activated. Thus, a pillar-shaped structure composed of the bulk insulating film 335, the charge storage layer 336, the gate insulating film 337, and the conductive pillar 338 is formed inside the storage via 334.

[0078] In the columnar structure formed inside the storage via 334, the portions intersecting with the stacked wiring layers 333, 332, and 331 function as transistors. Among these transistors, the portion intersecting with wiring layer 331 functions as selection transistor ST1. Among these transistors, the portion intersecting with wiring layer 332 functions as storage cell transistors MT (MT0 to MT7). Among these transistors, the portion intersecting with wiring layer 333 functions as selection transistor ST2. With this configuration, each columnar structure formed inside the storage via 334 serves as a reference. Figure 4 The NAND string NS described herein functions as follows. The conductive pillar 338 located inside the pillar body functions as a channel for the memory cell transistor MT and the selection transistors ST1 and ST2.

[0079] A wiring layer, functioning as a bit line BL, is formed at a position above the conductor post 338. A contact plug 339, connecting the conductor post 338 to the bit line BL, is formed at the upper end of the conductor post 338.

[0080] Along Figure 5 The depth direction of the paper has multiple [symbols / parallels]. Figure 5 The configuration shown is the same. Along Figure 5 A collection of multiple NAND strings NS arranged in a row along the depth direction of the paper forms a single string unit SU.

[0081] In the semiconductor memory device 2 of this embodiment, a peripheral circuit PER is provided on the lower side of the memory cell array 110, that is, at the position between the memory cell array 110 and the semiconductor substrate 300. The peripheral circuit PER is a circuit provided to realize the writing, reading and deleting operations of data in the memory cell array 110. Figure 3 The sense amplifier 120, line decoder 130, and voltage generation circuit 43 shown are part of the peripheral circuitry (PER). The PER includes various transistors and RC (resistance-capacitance) circuits. Figure 5 In the example shown, the transistor TR formed on the semiconductor substrate 300 is electrically connected to the bit line BL located on the upper side of the memory cell array 110 via a connector 924.

[0082] Alternatively, the configuration in which the memory cell array 110 is directly disposed on the semiconductor substrate 300 can be used, replacing the configuration described above. In this case, the p-type well region of the semiconductor substrate 300 functions as the source line SL. Furthermore, the peripheral circuitry PER is disposed along the surface of the semiconductor substrate 300 adjacent to the memory cell array 110.

[0083] return Figure 3 To continue the explanation. As mentioned above, in addition to the memory cell array 110, the memory plane PL1 also includes a sense amplifier 120 and a line decoder 130.

[0084] The sense amplifier 120 is a circuit used to adjust the voltage applied to the bit line BL, or to read the voltage of the bit line BL and convert it into data. When reading data, the sense amplifier 120 acquires the read data read from the memory cell transistor MT to the bit line BL and transmits the acquired read data to the input / output circuit 21. When writing data, the sense amplifier 120 transmits the write data written via the bit line BL to the memory cell transistor MT.

[0085] The line decoder 130 is a circuit configured as a group of switches (not shown) to apply voltages to word lines WL. The line decoder 130 receives the block address and the line address from register 42, selects the corresponding block BLK based on the block address, and selects the corresponding word line WL based on the line address. The line decoder 130 toggles the switch group on and off to apply voltage from the voltage generation circuit 43 to the selected word line WL.

[0086] Figure 6 An example configuration of a sense amplifier 120 is shown. The sense amplifier 120 includes a plurality of sense amplification units (SAUs) associated with a plurality of bit lines BL, respectively. Figure 6The detailed circuit configuration of one of the sensing amplification units, SAU, is extracted and illustrated.

[0087] like Figure 6 As shown, the sensing amplification unit SAU includes a sensing amplification section SA, latching circuits SDL, ADL, BDL, CDL, and XDL. The sensing amplification section SA, latching circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS to transmit and receive data with each other.

[0088] The sensing amplification unit SA, for example, senses the data read from the corresponding bit line BL during the readout operation and determines whether the read data is "0" or "1". The sensing amplification unit SA includes, for example, a transistor TR1 which is a p-channel MOS (Metal Oxide Semiconductor) transistor, transistors TR2 to TR9 which are n-channel MOS transistors, and a capacitor C10.

[0089] Transistor TR1 is connected to the power supply line at one end and to transistor TR2 at the other end. The gate of transistor TR1 is connected to node INV within the latch circuit SDL. Transistor TR2 is connected to transistor TR1 at one end and to node COM at the other end. The gate of transistor TR2 is connected to the input signal BLX. Transistor TR3 is connected to node COM at one end and to transistor TR4 at the other end. The gate of transistor TR3 is connected to the input signal BLC. Transistor TR4 is a high-voltage MOS transistor. Transistor TR4 is connected to transistor TR3 at one end and to the corresponding bit line BL at the other end. The gate of transistor TR4 is connected to the input signal BLS.

[0090] Transistor TR5 is connected at one end to node COM and at the other end to node SRC. Its gate is connected to node INV. Transistor TR6 is connected at one end between transistors TR1 and TR2 and at the other end to node SEN. Its gate is connected to the input signal HLL. Transistor TR7 is connected at one end to node SEN and at the other end to node COM. Its gate is connected to the input signal XXL.

[0091] One end of transistor TR8 is grounded, and the other end is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end is connected to the bus LBUS. The gate of transistor TR9 is fed by the input signal STB. One end of capacitor C10 is connected to node SEN. The other end of capacitor C10 is fed by the input clock CLK.

[0092] Signals BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by sequencer 41. Additionally, a voltage Vdd, for example, the internal power supply voltage of the semiconductor memory device 2, is applied to the power line connected to one end of transistor TR1, and a voltage Vss, for example, the ground voltage of the semiconductor memory device 2, is applied to node SRC.

[0093] Latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store the read data. Latch circuit XDL is connected to input / output circuit 21 and is used for data input / output between sensing amplifier unit SAU and input / output circuit 21. The read data, stored in latch circuit XDL, becomes output from input / output circuit 21 to memory controller 1. For example, data read from sensing amplifier unit SAU is stored in any of latch circuits ADL, BDL, or CDL, then transferred to latch circuit XDL, and then output from latch circuit XDL to input / output circuit 21. Alternatively, data input from memory controller 1 to input / output circuit 21 is transferred from input / output circuit 21 to latch circuit XDL, and then from latch circuit XDL to any of latch circuits ADL, BDL, or CDL.

[0094] The latch circuit SDL includes, for example, inverters IV11 and IV12, and transistors TR13 and TR14, which are n-channel MOS transistors. The input node of inverter IV11 is connected to node LAT. The output node of inverter IV11 is connected to node INV. The input node of inverter IV12 is connected to node INV. The output node of inverter IV12 is connected to node LAT. One end of transistor TR13 is connected to node INV, and the other end of transistor TR13 is connected to the bus LBUS. The gate of transistor TR13 is fed by the input signal STI. One end of transistor TR13 is connected to node LAT, and the other end of transistor TR14 is connected to the bus LBUS. The gate of transistor TR14 is fed by the input signal STL. For example, the data stored in node LAT is equivalent to the data stored in the latch circuit SDL. Furthermore, the data stored in node INV is equivalent to the inverted data stored in node LAT. The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are, for example, the same as the circuit configuration of latch circuit SDL, and therefore are omitted from the description.

[0095] Figure 7 This is a schematic diagram illustrating the threshold distribution, etc., of the memory cell transistor MT. Located in... Figure 7 The middle section of the graph shows the relationship between the threshold voltage of the memory cell transistor MT (horizontal axis) and the number of memory cell transistors MT (vertical axis).

[0096] As shown in this embodiment, when using the TLC method, multiple memory cell transistors MT are as follows: Figure 7 As shown in the middle section, eight threshold distributions are formed. These eight threshold distributions (write levels) are named in ascending order of threshold voltage as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level.

[0097] lie in Figure 7 The table above shows examples of data assigned to each of the threshold voltage levels. As shown in the table, the "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level are assigned, for example, different 3-bit data as follows: "ER" level: "111" ("lower bit / middle bit / higher bit"); "A" level: "011"; "B" level: "001"; "C" level: "000"; "D" level: "010"; "E" level: "110"; "F" level: "100"; "G" level: "101".

[0098] Thus, in this embodiment, the threshold voltage of the memory cell transistor MT can be selected from 8 pre-set candidate levels, and data is allocated according to each candidate level as described above.

[0099] The verification voltage used in the write operation is set between each pair of adjacent threshold distributions. Specifically, verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0100] The verification voltage VfyA is set between the maximum threshold voltage of the "ER" level and the minimum threshold voltage of the "A" level. If the verification voltage VfyA is applied to the word line WL, the memory cell transistors MT connected to the word line WL will be in the ON state if their threshold voltage is within the "ER" level, and in the OFF state if their threshold voltage is within the threshold distribution of the "A" level or higher.

[0101] The other verification voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same way as the verification voltage VfyA. Verification voltage VfyB is set between the "A" and "B" levels, verification voltage VfyC is set between the "B" and "C" levels, verification voltage VfyD is set between the "C" and "D" levels, verification voltage VfyE is set between the "D" and "E" levels, verification voltage VfyF is set between the "E" and "F" levels, and verification voltage VfyG is set between the "F" and "G" levels.

[0102] For example, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG can be set to 0.8V, 1.6V, 2.4V, 3.1V, 3.8V, 4.6V, and 5.6V, respectively. However, this is not a limitation; the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG can also be set in appropriate stages within the range of 0V to 7.0V.

[0103] Furthermore, the read voltage used in the read operation is set between adjacent threshold distributions. The "read voltage" refers to the voltage applied to the word line WL (select word line) connected to the memory cell transistor MT to be read during the read operation. During the read operation, data is determined based on whether the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage.

[0104] like Figure 7 As illustrated in the diagram below, specifically, the threshold voltage VrA for determining whether the memory cell transistor MT is within the "ER" level or within the "A" level is set between the maximum threshold voltage of the "ER" level and the minimum threshold voltage of the "A" level.

[0105] Other readout voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same way as readout voltage VrA. Readout voltage VrB is set between "A" and "B" levels, readout voltage VrC is set between "B" and "C" levels, readout voltage VrD is set between "C" and "D" levels, readout voltage VrE is set between "D" and "E" levels, readout voltage VrF is set between "E" and "F" levels, and readout voltage VrG is set between "F" and "G" levels.

[0106] Furthermore, the read-through voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., "G" level). The memory cell transistor MT, with the read-through voltage VPASS_READ applied to its gate, becomes ON regardless of the stored data.

[0107] Furthermore, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are, for example, set to be higher than the readout voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG, respectively. In other words, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set to be near the lower edge of the threshold distributions for "A," "B," "C," "D," "E," "F," and "G" levels, respectively.

[0108] When the data allocation described above is applied, during the read operation, one page of data for the lower bit (lower page data) can be determined using the read results of read voltages VrA and VrE. One page of data for the middle bit (middle page data) can be determined using the read results of read voltages VrB, VrD, and VrF. One page of data for the upper bit (upper page data) can be determined using the read results of read voltages VrC and VrG. Thus, the lower page data, middle page data, and upper page data are determined through 2, 3, and 2 read operations respectively. Therefore, the data allocation described above is called a "2-3-2 code".

[0109] Furthermore, the data allocation described above is merely an example, and actual data allocation is not limited to this. For example, 2 bits or more of data can be stored in a single memory cell transistor MT. Additionally, the number of threshold distributions of the allocated data (i.e., the number of "candidate levels") can be 7 or less, or 9 or more. For example, "1-3-3 code" or "1-2-4 code" can be used instead of "2-3-2 code". Furthermore, the allocation of lower bit / middle bit / upper bit can be changed, for example. More specifically, for example, in "2-3-2 code", data can be allocated by determining the lower page data using the read results of read voltages VrC and VrB, determining the middle page data using the read results of read voltages VrB, VrD, and VrF, and determining the upper page data using the read results of read voltages VrA and VrE. That is, for example, the allocation of lower bits and upper bits can be interchanged. In this case, the data is allocated according to the following description, corresponding to each level of the threshold voltage: "ER" level: "111" ("lower bit / middle bit / higher bit"); "A" level: "110"; "B" level: "100"; "C" level: "000"; "D" level: "010"; "E" level: "011"; "F" level: "001"; "G" level: "101".

[0110] The write operation performed in the semiconductor memory device 2 will be described. The write operation includes a programming operation and a verification operation. The "programming operation" refers to the operation of changing the threshold voltage of a memory cell transistor MT by injecting electrons into the charge storage layer 336 of a portion of the memory cell transistor MT. The "verification operation" refers to the operation of reading data after the programming operation to determine and verify whether the threshold voltage of the memory cell transistor MT has reached the target level. A memory cell transistor MT whose threshold voltage has reached the target level will then be prevented from being written to. The "target level" here refers to a specific candidate level selected from the eight candidate levels described above and set as the target level.

[0111] During the write operation, the programming and verification actions described above are repeatedly executed. As a result, the threshold voltage of the memory cell transistor MT rises to the target level.

[0112] Of the multiple word lines WL, the word line WL connected to the memory cell transistor MT that is the object of a write operation (i.e., the object whose threshold voltage changes) is also called the "select word line". Additionally, the word line WL connected to the memory cell transistor MT that is not the object of a write operation is also called the "non-select word line". The memory cell transistor MT that is the object of a write operation is also called the "select memory transistor".

[0113] Among multiple string units SU, the string unit SU that becomes the target of the write operation is also referred to as the "selected string unit". In addition, the string unit SU that does not become the target of the write operation is also referred to as the "non-selected string unit".

[0114] The conductive pillars 338 of each NAND string NS contained in the select string unit, i.e., each channel in the select string unit, are also referred to as "select channels". Similarly, the conductive pillars 338 of each NAND string NS contained in the non-select string unit, i.e., each channel in the non-select string unit, are also referred to as "non-select channels".

[0115] Of the multiple bit lines BL, the bit lines BL and below that connected to the select memory transistor are also called "select bit lines". In addition, the bit lines BL and below that are not connected to the select memory transistor are also called "non-select bit lines".

[0116] The programming actions will be explained below. The following example illustrates the programming action when the object is memory plane PL1, but the same applies to memory plane PL2. Figure 8 This indicates the potential change of each line during the programming operation. During programming, the sense amplifier 120 causes the potential of each bit line BL to change according to the programming data. For example, a ground voltage Vss (0V) is applied as an "L" level to the bit line BL connected to the memory cell transistor MT, which is the object to be programmed (and should raise the threshold voltage). For example, 2.5V is applied as an "H" level to the bit line BL connected to the memory cell transistor MT, which is not the object to be programmed (and should maintain the threshold voltage). The former bit line BL... Figure 8 The middle part is marked as "BL(0)". The bit line BL mentioned later is in Figure 8 The Chinese character is marked as "BL(1)".

[0117] The line decoder 130 selects any block of BLK as the write target, and then selects any string cell SU. More specifically, the voltage generation circuit 43 applies, for example, 5V to the selectable gate line SGD (selectable gate line SGDsel) in the selected string cell SU via the line decoder 130. This turns on the selection transistor ST1. On the other hand, the voltage generation circuit 43 applies, for example, a voltage Vss to the selectable gate line SGS via the line decoder 130. This turns off the selection transistor ST2.

[0118] Additionally, a voltage of, for example, 5V is applied from the voltage generation circuit 43 to the selectable gate line SGD (non-selectable selectable gate line SGDusel) of the non-selectable string unit SU in the selection block BLK via the line decoder 130. This turns on the selection transistor ST1. Furthermore, the selectable gate line SGS is common to all string units SU contained in each BLK. Therefore, in the non-selectable string unit SU, the selection transistor ST2 is also turned off.

[0119] Furthermore, voltage Vss is applied, for example, to the selectable gate line SGD and selectable gate line SGS in the non-selectable block BLK via the voltage generation circuit 43 and the line decoder 130. As a result, select transistors ST1 and ST2 are turned off.

[0120] The source line SL becomes a higher potential than the optional gate line SGS. This potential is, for example, 1V.

[0121] Then, the potential of the selectable gate line SGDsel in the select block BLK is set to, for example, 2.5V. This potential is the voltage that turns on the select transistor ST1 corresponding to the bit line BL(0), which is given 0V in the example, and turns off the select transistor ST1 corresponding to the bit line BL(1), which is given 2.5V. Thus, in the select string unit SU, the select transistor ST1 corresponding to the bit line BL(0) is turned on, and the select transistor ST1 corresponding to the bit line BL(1), which is given 2.5V, is turned off. On the other hand, the potential of the non-selectable gate line SGDusel is set to, for example, voltage Vss. Thus, in the non-select string unit SU, the select transistor ST1 is turned off regardless of the potentials of the bit lines BL(0) and BL(1).

[0122] Then, the line decoder 130 selects any word line WL as the write target in the selection block BLK. A voltage, for example, VPGM is applied from the voltage generation circuit 43 to the word line WL (selected word line WLsel) that is the write target via the line decoder 130. On the other hand, a voltage, for example, VPASS_PGM is applied from the voltage generation circuit 43 to other word lines WL (non-selected word lines WLusel) via the line decoder 130. The voltage VPGM is a high voltage used to inject electrons into the charge storage layer 336 through tunneling. The voltage VPASS_PGM is a voltage that turns on the memory cell transistor MT connected to the word line WL, but does not change the threshold voltage. VPGM is a voltage higher than VPASS_PGM.

[0123] In the NAND string NS corresponding to the bit line BL(0) which is being programmed, the select transistor ST1 is turned on. Therefore, the channel potential of the memory cell transistor MT connected to the select word line WLsel becomes 0V. The potential difference between the control gate and the channel increases, resulting in electron injection into the charge storage layer 336, thus raising the threshold voltage of the memory cell transistor MT.

[0124] In the NAND string NS corresponding to the bit line BL(1) of the non-programmed object, the selection transistor ST1 is turned off. Therefore, the channel voltage of the memory cell transistor MT connected to the selection word line WLsel floats, and through capacitive coupling with word lines WL, the channel potential rises to near the voltage VPGM. The potential difference between the control gate and the channel decreases, resulting in no electron injection into the charge storage layer 336, thus the threshold voltage of the memory cell transistor MT remains unchanged. More precisely, the threshold voltage does not change as if the threshold distribution level were shifting to a higher distribution.

[0125] The read operation will be explained below. The following example describes the read operation when the object is memory plane PL1, but the same applies to memory plane PL2. The verification operation performed after the programming operation is the same as the read operation described below. Figure 9 This indicates the potential changes of each wiring during a read operation. During a read operation, the NAND string NS containing the memory cell transistor MT that is the target of the read operation is selected. Alternatively, the string cell SU containing the page that is the target of the read operation is selected.

[0126] First, a voltage of, for example, 5V is applied from the voltage generation circuit 43 to the selectable gate line SGDsel, the non-selectable gate line SGDusel, and the selectable gate line SGS via the row decoder 130. This turns on the select transistors ST1 and ST2 contained in the select block BLK. Next, a read pass voltage, VPASS_READ, is applied from the voltage generation circuit 43 to the select word line WLsel and the non-selectable word line via the row decoder 130. The read pass voltage VPASS_READ is a voltage that turns on the memory cell transistor MT regardless of its threshold voltage and does not cause a change in the threshold voltage. Therefore, current is conducted in all NAND strings NS contained in the select block BLK, whether it is the select string cell SU or the non-selectable string cell SU.

[0127] Next, a read voltage Vr, such as VrA, is applied from the voltage generation circuit 43 to the word line WL (select word line WLsel) connected to the memory cell transistor MT that is the target of the read operation, via the line decoder 130. A read pass voltage VPASS_READ is applied to the other word lines (non-select word lines WLusel).

[0128] Additionally, while maintaining the voltage applied to the selectable gate line SGDsel and the selectable gate line SGS, a voltage, for example Vss, is applied from the voltage generation circuit 43 to the non-selectable gate line SGDusel via the line decoder 130. As a result, the select transistor ST1 contained in the select string unit SU remains on, while the select transistor ST1 contained in the non-selectable string unit SU becomes off. Furthermore, in both the select string unit SU and the non-selectable string unit SU, the select transistor ST2 contained in the select block BLK becomes on.

[0129] Therefore, in the NAND string NS contained in the non-selection string cell SU, at least the selection transistor ST1 is in the off state, and thus no current path is formed. On the other hand, the NAND string NS contained in the selection string cell SU forms or does not form a current path depending on the relationship between the read voltage Vr applied to the selection word line WLsel and the threshold voltage of the memory cell transistor MT.

[0130] The sense amplifier 120 applies a voltage to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifier 120 reads data based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT, which is the target of the read operation, is higher than the read voltage applied to the memory cell transistor MT. Alternatively, data readout may be based on the time-varying potential in the bit line BL, rather than on the value of the current flowing through the bit line BL. In the latter case, the bit line BL is pre-charged to a pre-specified potential.

[0131] The verification operation described above is performed in the same way as the read operation described above. In the verification operation, a verification voltage, such as VfyA, is applied from the voltage generation circuit 43 to the word line WL connected to the memory cell transistor MT that is being verified, via the line decoder 130.

[0132] Furthermore, the action of applying a 5V voltage to the selectable gate line SGDsel and the non-selectable gate line SGDusel in the initial stage of the programming operation described above is sometimes omitted. Similarly, the action of applying a 5V voltage to the non-selectable gate line SGDusel and applying the read pass voltage VPASS_READ to the select word line WLsel in the initial stage of the read operation (verification operation) described above is sometimes omitted.

[0133] The specific signal flow between the semiconductor storage device 2 and the memory controller 1 during the read operation will be explained. The following explanation uses the example of the read operation being performed on memory surface PL1, but the situation is the same for memory surface PL2.

[0134] First, a comparative example of this embodiment will be described. Figure 10 Examples of various signals transmitted and received between the semiconductor memory device 2 and the memory controller 1 are shown in the configuration of the comparative example.

[0135] During a read operation, the memory controller 1 sequentially inputs a signal containing "05h", multiple "ADD" signals, and "E0h" as the signal DQ<7:0> to the semiconductor storage device 2. "05h" is an instruction used to execute the read operation of data from the memory cell array 110. "ADD" is a signal specifying the address that becomes the data read source. "E0h" is an instruction used to start the read operation.

[0136] exist Figure 10 In this diagram, the timing marker for the input of "E0h" to the semiconductor memory device 2 is designated as time t0. At time t1, after a specified period elapsed from time t0, the memory controller 1 toggles the read enable signal / RE. As described above, the read enable signal / RE is a signal used by the memory controller 1 to read data from the semiconductor memory device 2, and is input to the input / output pad group 31 of the semiconductor memory device 2. After time t1, the read enable signal / RE alternately switches between H and L levels (tug-of-war). These alternately switched read enable signals / RE are used as "read signals" for reading data. The input / output pad group 31 corresponds to a "receiving unit" that repeatedly receives "read signals" from the memory controller 1.

[0137] Whenever the read enable signal / RE is switched (i.e., whenever each read signal is input), the semiconductor memory device 2 outputs data as the signal DQ<7:0>, and switches the data strobe signal DQS between H level and L level. Figure 10In this diagram, the data output as signals DQ<7:0> is labeled "D". Furthermore, the timing of outputting the initial data and switching the data strobe signal DQS is labeled as time t2. The correspondence between the switching of the read enable signal / RE input from memory controller 1 and the switching of the data strobe signal DQS output from semiconductor memory device 2 is as follows: Figure 10 As shown by the dashed arrow in the image.

[0138] Furthermore, the data readout from the semiconductor memory device 2 is performed by dividing a single data into even data consisting of an even number of bits and odd data consisting of an odd number of bits, and then outputting the two alternately. Figure 10 Data marked "D" will be output as either even or odd numbers.

[0139] However, during the read operation, multiple transistors containing the memory cell transistor MT in the memory interface PL1 need to be turned on and off. At this time, the current output from the voltage generation circuit 43 to each part increases, thus temporarily reducing the power supply voltage. More specifically, when the power supply voltage is controlled by feedback control, the current output from the voltage generation circuit 43 to each part increases, thereby temporarily reducing the power supply voltage. Figure 10 The top paragraph illustrates an example of such a change in power supply voltage. In this example, the power supply voltage begins to decrease from the moment t0 when the read enable signal / RE begins to trigger, or around moment t0, and also briefly falls below the target voltage after moment t2. If such a decrease in power supply voltage occurs, the I / O output characteristics in semiconductor memory device 2 deteriorate, and there is a risk that the output of read data becomes unstable.

[0140] As a measure to address the drop in power supply voltage, for example, the semiconductor memory device 2 could be made to... Figure 11 The actions shown. Figure 11 The text shows the relationship with... Figure 10 Examples of different comparative examples, such as various signals being transmitted and received.

[0141] Figure 11 In the comparative example, semiconductor memory device 2 is in comparison with Figure 10In the same timing sequence as the comparative example (time t2), the data strobe signal DQS begins to trigger. However, after the data strobe signal DQS begins to trigger, the semiconductor memory device 2 does not output data to the memory controller 1 for a short period of time. Data output from the semiconductor memory device 2 begins at time t3, which is later than time t2. In this example, the length of the period from time t2 to time t3 is the length of the period during which a total of 4 even or odd data points can be output (in other words, the length of the period during which 2 even data points and 2 odd data points can be output). The period from the start of the triggering of the data strobe signal DQS until the start of outputting the data requested by the memory controller 1 is also referred to as the "delay period".

[0142] If so Figure 11 In a comparative example, if a delay period is typically set, the data output timing is later than time t2, thus suppressing the phenomenon of a temporary drop in power supply voltage at the start of data output. In other words, if... Figure 11 By setting a typical delay period, data output can begin while the phenomenon of a temporary drop in power supply voltage caused by the thixotropic induction of the data strobe signal DQS is suppressed. However, if data output begins at time t3, this will result in an increase in current. In other words, even if... Figure 11 In comparison, the data output usually starts later than the thixotropic start of the data strobe signal DQS, and it is still impossible to avoid the effect of the current increase caused by the start of data request, which temporarily reduces the power supply voltage.

[0143] Therefore, in the semiconductor memory device 2 of this embodiment, the read operation is performed as described below. Figure 12 China through and Figure 10 and Figure 11 Examples of various signals transmitted and received in the semiconductor memory device 2 of this embodiment are shown using the same method.

[0144] In this embodiment, a similar feature is also provided. Figure 11 In the same delay period as the previous example, the output of data requested by memory controller 1 begins at time t3. However, in this embodiment, data is also output from semiconductor memory device 2 to memory controller 1 during the delay period. The data output at this time is dummy data, different from the data requested by memory controller 1. This dummy data is hereinafter referred to as "non-regular data". Furthermore, the read data requested by memory controller 1 is hereinafter referred to as "regular data" to distinguish it from non-regular data. Figure 12 In, with Figure 10 Similarly, for the data output as the signal DQ<7:0>, regular data is labeled "D" and non-regular data is labeled "d". Furthermore, data labeled "d" refers to data output as either even or odd numbers.

[0145] In the semiconductor memory device 2 of this embodiment, the output current from the voltage generation circuit 43 increases at the beginning of the delay period, i.e., time t2, but does not increase at the end of the delay period, i.e., time t3. Therefore, as Figure 12 As shown, although the power supply voltage drops significantly after time t2, it recovers to some extent at a time point earlier than time t3. In the semiconductor memory device 2 of this embodiment, as shown in FIG12, after the power supply voltage stabilizes, regular data is sent from the semiconductor memory device 2 to the memory controller 1, thus solving the problem of deteriorated I / O output characteristics. Furthermore, in the memory controller 1, as long as it is pre-agreed to ignore irregular data input during the delay period (e.g., discarded after reception), irregular data will not adversely affect the read operation.

[0146] Main reference Figure 13 The specific configuration of the semiconductor memory device 2 used to transmit irregular data (d) during the delay period is described in the figure. The configuration of the data flow path along the path from the memory cell array 110 to the input / output pad group 31 is schematically shown in the figure.

[0147] The sensing amplifier 120 includes multiple sensing amplification units (SAUs), multiple latch circuits (XDLs), and a multiplexer 121, as described above. Data read from the memory cell array 110 is sent from the sensing amplification units (SAUs) to the latch circuits (XDLs) and temporarily stored, then transmitted to the first storage unit 510 via the multiplexer 121. The multiplexer 121 and the first storage unit 510 are connected, for example, via a first data bus 501 containing 128 wires. However, the number of wires in the first data bus 501 is not limited to 128. The number of wires in the first data bus 501 is less than the number of wires connecting the multiple latch circuits (XDLs) to the multiplexer 121. The multiplexer 121 sequentially transmits each piece of data sent from the multiple latch circuits (XDLs) to the subsequent first storage unit 510 via the first data bus 501.

[0148] The first storage unit 510 stores multiple data read from the memory cell array 110, constituting a storage device that performs a so-called "First In First Out" (FIFO) operation. The first storage unit 510 temporarily stores multiple data transmitted from the multiplexer 121 and outputs these data sequentially to the input / output circuit 21, starting with the first input data. The first storage unit 510 and the input / output circuit 21 are connected, for example, via a second data bus 502 containing 16 signal lines. However, the number of wires included in the second data bus 502 is not limited to 16. After the data input from the first storage unit 510 to the input / output circuit 21 is temporarily stored in the second storage unit 520 (described below), it is output externally as the signal DQ<7:0> from the input / output pad group 31.

[0149] The input / output circuit 21 includes a second storage unit 520, a write pointer generation circuit 541, a read pointer generation circuit 542, a multiplexer 531, and a driver 532. The circuit formed by these components is individually provided, corresponding to the eight pads of the input / output pad group 31, that is, the eight pads corresponding to DQ<7:0>. In other words, the input / output circuit 21 has eight units each of the second storage unit 520 and the multiplexer 531. Figure 13 Only the pads connected to DQ<0> are shown in the diagram; the others are omitted.

[0150] The second storage unit 520 is an element that receives data sent from the first storage unit 510 and stores a plurality of such data. In this embodiment, the second storage unit 520 is divided into a part for storing even-numbered data and a part for storing odd-numbered data. The former will also be referred to as "second storage unit 521" below. The latter will also be referred to as "second storage unit 522" below.

[0151] Like the first storage unit 510 described above, the second storage unit 520 is configured to perform a so-called "First In First Out" (FIFO) operation. After temporarily receiving data input from the first storage unit 510 as described above, the second storage unit 520 outputs the data sequentially to the pads of DQ<0>, starting from the input data. This data output is performed alternately from the second storage unit 521 and the second storage unit 522 via the multiplexer 531 and the driver 532, respectively.

[0152] The write pointer generation circuit 541 is a circuit that generates the write pointer Wptr. The "write pointer Wptr" refers to the pointer that indicates the storage position (i.e., the write position) when data sent from the first storage unit 510 is stored in the second storage unit 520.

[0153] The read pointer generation circuit 542 is a circuit that generates the read pointer Rptr. The "read pointer Rptr" refers to the pointer that indicates the storage position (i.e., the read position) of the data in the second storage unit 520 when data is sent from the second storage unit 520 to the driver 532.

[0154] The pair of circuits consisting of the write pointer generation circuit 541 and the read pointer generation circuit 542 are respectively provided for the second storage unit 521 and the second storage unit 522. However Figure 13 Only the write pointer generation circuit 541 and the read pointer generation circuit 542 provided for the second storage unit 522 are shown in the figure, and the illustrations of the write pointer generation circuit 541 and the read pointer generation circuit 542 provided for the second storage unit 521 are omitted.

[0155] The data transmission from the first storage unit 510 to the second storage unit 520 and the data transmission from the second storage unit 520 to the multiplexer 531 are controlled by the sequencer 41.

[0156] The structure of the second storage unit 520 and the functions of the write pointer generation circuit 541 and the read pointer generation circuit 542 will be explained. Figure 14 The configuration of the second storage unit 522 is schematically shown in the diagram. Furthermore, the configuration of the second storage unit 521 is the same as that of the second storage unit 522, therefore its description is omitted.

[0157] like Figure 14 As shown, the second storage unit 522 includes a multiplexer M1, multiple flip-flops FF, and a multiplexer M2. Furthermore, although multiple flip-flops FF are provided in the second storage unit 522, Figure 14 Only three of them are drawn and labeled as "FF1", "FF2", and "FF3".

[0158] The multiplexer M1 selects any flip-flop FF as the data writing target based on the write pointer Wptr input from the write pointer generation circuit 541, and sends data to that flip-flop FF.

[0159] Each flip-flop (FF) functions as a 1-bit data storage location in the second storage unit 522. When the input clock signal CLK1 rises from the L level to the H level, the flip-flop (FF) outputs the previously stored data to the multiplexer M2 side and stores the new data input from the multiplexer M1 side.

[0160] The clock signal CLK1 is a signal that specifies the timing of data input to each flip-flop (FF). The clock signal CLK1 is generated by the sequencer 41. The clock signal CLK1 is input from the sequencer 41 to each flip-flop (FF) via the delay circuit 410 and the write pointer generation circuit 541.

[0161] The write pointer generation circuit 541 generates a write pointer Wptr based on the input clock signal CLK1. The write pointer Wptr is incremented by the write pointer generation circuit 541 when the clock signal CLK1 rises from level L to level H. The write pointer Wptr is a signal that specifies which flip-flop FF should be loaded with the data input from the first storage unit 510. The flip-flops FF that are the data to be written to are switched sequentially by the carry-over of the write pointer Wptr.

[0162] Multiplexer M2 selects any flip-flop FF as the data read target based on the read pointer Rptr input from the read pointer generation circuit 542, and receives data from that flip-flop FF. Multiplexer M2 outputs the data to multiplexer 531 when the read pointer Rptr carries over.

[0163] The read pointer Rptr is a signal that specifies which flip-flop (FF) from which data should be output to the multiplexer 531 and specifies the timing of the data output. The read pointer Rptr is generated by the read pointer generation circuit 542 and input to the multiplexer M2 from the read pointer generation circuit 542.

[0164] The read pointer generation circuit 542 generates a read pointer Rptr based on the input clock signal CLK2. The read pointer Rptr carries over through the read pointer generation circuit 542 when the clock signal CLK2 rises from level L to level H, and is input to the multiplexer M2. The carry over the read pointer Rptr causes the flip-flops (FFs) that are the data read targets to switch sequentially. The switching order of the flip-flops that are the data read targets is the same as the switching order of the flip-flops that are the data write targets. Thus, the second storage unit 522 enables a "first-in, first-out" (FIFO) operation.

[0165] As described above, the clock signal CLK2 is the source signal for the read pointer Rptr. The clock signal CLK2 is generated by the sequencer 41 based on the read enable signal / RE input from the memory controller 1. Figure 13 As shown, the clock signal CLK2 is input from the sequencer 41 to the read pointer generation circuit 542, and also to the multiplexer 531.

[0166] The multiplexer 531 is an element that alternately receives even data input from the second storage unit 521 and odd data input from the second storage unit 522, and outputs them to the driver 532.

[0167] Alternatively, multiple triggers FF can be arranged in multiple segments from multiplexer M1 to multiplexer M2. Furthermore, the first storage unit 510 described above can also adopt the same configuration as the second storage unit 522 described above.

[0168] The second storage unit 520, which performs the "first-in, first-out" operation, can be understood as an element with multiple data storage locations arranged in a specified order. Figure 15 The structure of this second storage unit 520 is schematically drawn in the figure. Figure 15 The rectangles drawn horizontally in a row represent the data storage locations (specifically, triggers FF). Each storage location is determined according to the data writing order (and reading order). Figure 15 The text is drawn in a row from left to right. The write pointer Wptr and read pointer Rptr are respectively drawn along the arrows... Figure 15 Carry-over to the right.

[0169] Figure 15 (A) shows the state of the second storage unit 520 at the point in time when a read command for data is input from the memory controller 1 and data output preparation is completed in the semiconductor storage device 2, without a set delay period (when the length of the delay period is 0). Figure 12 In the example, the state is before time t1. In the semiconductor memory device 2, by performing a prefetch operation (read-ahead operation), a state is formed in which a portion of a series of data that should be output is stored in the second storage unit 520.

[0170] exist Figure 15 In example (A), an example is shown where regular data D0, D1, D2, D3... are output according to the request of memory controller 1.

[0171] Figure 15 (B) shows the state of the second storage unit 520 at the point in time when a read instruction for data is input from the memory controller 1 and the data output preparation is completed in the semiconductor storage device 2, under the condition of a set delay period. In this case, before outputting regular data D0, D1, D2, D3..., irregular data... d3, d2, d1, d0 are output according to the length of the delay period. More specifically, when the length of the delay period is 8, before outputting regular data D0, D1, D2, D3... (D0o, D1o, D2o, D3o...) from the second storage unit 522 corresponding to odd-numbered data, irregular data d3, d2, d1, d0 (d3o, d2o, d1o, d0o) are output. Similarly, before outputting regular data D0, D1, D2, D3... (D0e, D1e, D2e, D3e...) from the second storage unit 521 corresponding to even data, non-regular data d3, d2, d1, d0 (d3e, d2e, d1e, d0e) will also be output.

[0172] If no delay period is set (if the length of the delay period is 0), such as Figure 15As shown in (A), the read pointer Rptr indicates the storage location of the initially output D0. However, in this embodiment, when a delay period is set, the read pointer Rptr is pre-adjusted according to its length so that it points to the negative side ( Figure 15 The position (left side) is used to initially output data different from D0. This process is performed, for example, by controlling the sequencer 41.

[0173] For example, such as Figure 15 As in example (B), when a delay period of 8 is set, the read pointer Rptr is adjusted in the second storage unit 522 corresponding to odd-numbered data and the second storage unit 521 corresponding to even-numbered data, so that it changes from the initial storage position of normal data (D0) to the position reached by moving 4 times towards the negative side. By adjusting the read pointer Rptr to the negative side in this way, before outputting D0e, D0o, D1e, D1o, D2o, D2e, D3o, D3e... as normal data to the memory controller 1, d3e, d3o, d2e, d2o, d1e, d1o, d0e, d0o as non-normal data in sequence.

[0174] Figure 16 As shown in Figure 15 The example in (B) shows the signal when outputting data after adjusting the read pointer Rptr. In this diagram, "d3e" represents the d3 data output from the second storage unit 521 as even-numbered data, and "d3o" represents the d3 data output from the second storage unit 522 as odd-numbered data. The same applies to other data such as "d2e", "d2o", "d1e", "d1o", "d0e", "d0o", and "D0e", "D0o", "D1e", "D1o", "D2e", "D2o", "D3e", and "D3o".

[0175] Figure 18 The diagram shows the relationship between the data stored in the trigger circuits FF1, FF2, and FF3 of the second storage unit 520 during the delay period and the data output from the second storage unit 520.

[0176] After the delay period ends, the second storage unit 520 begins to output regular data. Figure 19 and Figure 20 The diagram shows the relationship between the data stored in the trigger circuits FF1, FF2, and FF3 of the second storage unit 520 during the data output period after the delay period ends and the data output from the second storage unit 520.

[0177] In this example, the length of the delay period from time t2 to time t3 is set to the length of the period during which a total of 8 even or odd data points can be output (in other words, the length of the period during which 4 even data points and 4 odd data points can be output). Therefore, by moving the read pointer Rptr 4 times to the negative side in the second storage units 521 and 522 respectively, it is possible to output non-regular data during the delay period and output regular data after the delay period.

[0178] However, if the write pointer Wptr carries over during the delay period of outputting irregular data from the second storage unit 520, a portion of the data that should be output later may not be output and may be directly overwritten. Therefore, in the semiconductor memory device 2 of this embodiment, during the delay period of sending irregular data from the second storage unit 520, the sequencer 41 temporarily stops the data transmission from the first storage unit 510 to the second storage unit 520.

[0179] Figure 13 The delay circuit 410 shown is a circuit that sends the clock signal CLK1 output from the sequencer 41 to the first storage unit 510 or the write pointer generation circuit 541 in the subsequent stage. During the delay period, the delay circuit 410 temporarily stops sending the clock signal CLK1. Specifically, it counts the clock signal CLK1 input from the sequencer 41, and at the point when the count reaches a specified number of times that the data update should stop during the delay period, it starts sending the clock signal CLK1 to the subsequent stage.

[0180] As a result, during the delay period, data transmission from the first storage unit 510 to the second storage unit 520 ceases. This prevents the situation where data in the second storage unit 520 is overwritten without being transmitted. The delay circuit 410 can also be configured as part of the sequencer 41.

[0181] As described above, the semiconductor memory device 2 of this embodiment includes: a first storage unit 510 and a second storage unit 520, which temporarily store a plurality of data read from the memory cell array 110; an output unit (driver 532 and input / output pad group 31), which outputs data repeatedly sent from the second storage unit 520 to an external memory controller 1; a receiving unit (logic control pad group 32 and logic control circuit 22), which repeatedly receives read signals (read enable signal / RE) for reading data from the memory controller 1; and a control unit (sequencer 41), which sends data from the second storage unit 520 to the output unit in response to each read signal.

[0182] The sequencer 41, acting as the control unit, sends irregular data (different from the data requested by the memory controller 1) from the storage unit to the output unit as data corresponding to the read signals initially received by the receiving unit a specified number of times. Conversely, it sends the regular data (the data requested by the memory controller 1) from the storage unit to the output unit as data corresponding to the read signals subsequently received by the receiving unit. As a result, by the time regular data transmission begins, the reduced power supply voltage can be restored to approximately its normal value, thus ensuring stable data output to the memory controller 1.

[0183] The sequencer 41, acting as the control unit, sends irregular data from the storage unit by pre-adjusting the read pointer Rptr according to the "specified number of times." The read pointer Rptr indicates the storage position of the data to be sent to the output unit from among the multiple data stored in the second storage unit 520. Specifically, the sequencer 41 pre-adjusts the read pointer Rptr in a manner that indicates the storage position reached by moving the pointer a number of times from the storage position of the regular data to the negative side, corresponding to the specified number of times. This allows for easy output of irregular data during the delay period.

[0184] Furthermore, as a configuration for the semiconductor storage device 2 that transmits irregular data during the delay period, it is also possible to consider using... Figure 17 The comparative example shown has a configuration that differs from this embodiment in that a delay circuit 543 is provided in the input / output circuit 21.

[0185] The delay circuit 543 transmits the clock signal CLK2 output from the sequencer 41 to the subsequent read pointer generation circuit 542. During the delay period, the delay circuit 543 temporarily stops transmitting the clock signal CLK2. Specifically, it counts the clock signal CLK2 input from the sequencer 41, and at the point when the count reaches a specified number of times that the data update should stop during the delay period, it begins to transmit the clock signal CLK2 to the subsequent stage. Furthermore, the clock signal CLK2 continues to be transmitted to the multiplexer 531 during the delay period.

[0186] In this case, during the delay period, the data output from the second storage unit 520 is not updated; instead, the same data indicated by the (stationary) read pointer Rptr continues to be sent as non-regular data. After the delay period ends, regular data transmission begins in the same manner as in this embodiment.

[0187] However, since the delay circuit 543 needs to count the rapidly switching clock signal CLK2, it requires high-speed transistors or similar components that consume relatively large amounts of power. Furthermore, if the delay period is longer, the number of counts increases, requiring even more transistors, thus increasing the size of the delay circuit 543. This can lead to increased power consumption and a larger circuit size. Additionally, since the data output from the second storage unit 520 is not updated during the delay period, but instead the same data indicated by the stationary read pointer Rptr is continuously sent as non-regular data, it is impossible to apply a suitable current load to the voltage generation circuit.

[0188] In contrast, in this embodiment, it is not necessary to temporarily stop updating the data output from the second storage unit 520 during the delay period. Therefore, the delay circuit 543 in the comparative example is not required, thereby avoiding increased power consumption and larger circuit size.

[0189] In this embodiment, the second storage unit 520 is provided in the input / output circuit 21. However, the configuration of the second storage unit 520 is not limited to this. For example, the second storage unit 520 may also be configured as follows: Figure 21 The variation shown is typically configured to span the second data bus 502.

[0190] Alternatively, as in this variation, the multiplexer M1 and multiple flip-flops FF of the second storage unit 520 can be positioned directly behind the first storage unit 510, and the multiplexer M2 of the second storage unit 520 can be positioned within the input / output circuit 21. In this case, the write pointer generation circuit 541 is positioned near the multiplexer M1 and multiple flip-flops FF, and the read pointer generation circuit 542 is positioned near the multiplexer M2.

[0191] When the second storage unit 520 is configured to span the second data bus 502, the number of wiring increases compared to the case where the first storage unit 510 is connected to the input / output circuit 21 via the second data bus 502. For example, if the second data bus 502 consists of 16 wirings, then when the second storage unit 520 is configured to span the second data bus 502, and the second storage unit 522 corresponding to odd-numbered data and the second storage unit 521 corresponding to even-numbered data each have 3 flip-flops (FF), 48 wirings are required to connect the first storage unit 510 to the input / output circuit 21. However, as the number of wirings increases, the switching speed of signals transmitted in each wiring can be slowed down. Therefore, it is not necessary to set the threshold voltage of the transistors used to transmit and receive signals low, thereby reducing the power consumed by the semiconductor memory device 2 during data transmission.

[0192] On the other hand, the write pointer generation circuit 541 can be positioned near the first storage unit 510. A high-speed clock signal CLK1 is supplied to the write pointer generation circuit 541 and the first storage unit 510. Therefore, by configuring the second storage unit 520 across the second data bus 502, the write pointer generation circuit 541 and the first storage unit 510 can be positioned close to ground, thus shortening the control signal line used to transmit the clock signal CLK1. As a result, the power consumed by the semiconductor memory device 2 during data transmission can be further reduced.

[0193] Furthermore, in this embodiment, it has been described that each of the first storage unit 510 and the second storage unit 520 includes multiple flip-flops (FF). However, the configuration of the first storage unit 510 and the second storage unit 520 is not limited to this. The first storage unit 510 and the second storage unit 520 may also each include multiple latch circuits instead of multiple flip-flops (FF). As long as the configuration is such that a data storage circuit capable of storing data according to a write pointer (Wptr) is used to perform a so-called "First In First Out" (FIFO) operation, it is acceptable.

[0194] The embodiments described above have been illustrated with reference to specific examples. However, the present invention is not limited to these specific examples. Products obtained by making appropriate design modifications to these specific examples, as long as they possess the features of the present invention, are also included within the scope of the present invention. The elements, their configurations, conditions, shapes, etc., of each specific example are not limited to those illustrated, but can be appropriately modified. The elements of each specific example can be appropriately combined as long as no technical contradiction occurs.

[0195] [Explanation of Symbols]

[0196] 1. Memory controller

[0197] 2 Semiconductor memory devices

[0198] 31 Input / output pad group

[0199] 32 Logic Control Pad Group

[0200] 41 Sequencer

[0201] 110,210 memory cell array

[0202] 510 First Preservation Department

[0203] 520 Second Preservation Department.

Claims

1. A semiconductor memory device, comprising: Storage cell array, used to store data; The storage unit temporarily stores multiple data items read from the storage unit array; The output unit outputs the data repeatedly sent from the storage unit to an external memory controller; The receiving unit repeatedly receives read signals from the memory controller for reading data; and The control unit, in response to each of the read signals, sends data from the storage unit to the output unit; and The control unit Irregular data that differs from the data requested by the memory controller is transmitted from the storage unit to the output unit as data corresponding to each of the read signals initially received by the receiving unit a specified number of times. The data requested by the memory controller, i.e., the regular data, is transmitted from the storage unit to the output unit as data corresponding to the read signal subsequently received by the receiving unit. The control unit The irregular data is sent from the storage unit by pre-adjusting the read pointer according to the specified number of times. The read pointer indicates the storage location of the data to be sent to the output unit next among the multiple data stored in the storage unit.

2. The semiconductor memory device according to claim 1, wherein The control unit pre-adjusts the read pointer so that it moves from the storage location of the normal data to the negative data storage location a number of times corresponding to the specified number of times.

3. The semiconductor memory device according to claim 1 or 2, wherein The storage unit includes: The first storage unit stores multiple data read from the storage cell array; and The second storage unit stores multiple data items sent from the first storage unit; and In response to the read signal, data is sent from the second storage unit to the output unit. The control unit controls the data transmission from the first storage unit to the second storage unit and the data transmission from the second storage unit to the output unit.

4. The semiconductor memory device according to claim 3, wherein During the period when the control unit sends the irregular data from the second storage unit to the output unit, The transmission of data from the first storage unit to the second storage unit is stopped.

5. The semiconductor memory device according to claim 3, wherein Multiple second storage units are provided.

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