Analog switch circuit

Abstract

The analog switch circuit of the embodiment includes a CMOS analog switch having a gate operating voltage resistance VGT, a first gate drive circuit, and a second gate drive circuit to which an enable signal and a control signal are input. If VGT < VSH ≤ 2 × VGT, the second gate drive circuit outputs a signal of voltage VSH / 2 to the gate terminal of the PMOS when the control signal is 0, and the first gate drive circuit outputs a signal of voltage VSH / 2 to the gate terminal of the NMOS when the control signal is 1, in the case where the enable signal is 0.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2022-40740 (filed on March 15, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The implementation involves an analog switching circuit composed of N-type MOSFETs and P-type MOSFETs connected in parallel. Background Technology

[0003] If an N-type MOSFET (hereinafter referred to as NMOS) is used as an analog switch, the high-voltage side of the input signal sometimes results in distortion in the output signal. Conversely, if a P-type MOSFET (hereinafter referred to as PMOS) is used as an analog switch, the low-voltage side of the input signal sometimes results in distortion in the output signal. Therefore, CMOS analog switches that combine NMOS and PMOS in parallel have been conventionally used to reduce output signal distortion.

[0004] The gate terminals of NMOS and PMOS are insulated from the source and drain terminals by an oxide film. However, if a voltage higher than the gate withstand voltage is applied between the gate terminal and the source terminal, the insulating oxide film can sometimes be damaged. Therefore, analog switches are used at voltages below the gate withstand voltage.

[0005] Additionally, high-gate-voltage transistors can be used when operating at voltages higher than the standard gate voltage. However, high-gate-voltage transistors are expensive. Summary of the Invention

[0006] The implementation provides a low-cost analog switching circuit that uses transistors with conventional gate breakdown voltages and can be used at voltages higher than the gate breakdown voltage.

[0007] The analog switch circuit of the embodiment includes: an analog switch, wherein the source terminals of an N-type MOSFET and a P-type MOSFET with a gate operating withstand voltage of VGT are connected to each other and the drain terminals are connected to each other, and the N-type MOSFET and the P-type MOSFET are configured in parallel, wherein when a voltage higher than VGT and less than 2×VGT is set as VSH, the potential of the drain terminal is (VSH / 2); a first gate drive circuit, which is input with an enable signal and a control signal and is connected to the gate terminal of the N-type MOSFET of the analog switch; and a second gate drive circuit, which is input with the enable signal and the control signal and is connected to the gate terminal of the P-type MOSFET of the analog switch. When the logic value of the enable signal is 0, a voltage of 0 or a voltage of VSH is applied to the source terminal of the analog switch depending on whether the logic value of the control signal is 0 or 1. When the logic value of the control signal is 0, the first gate drive circuit outputs a signal of voltage 0 to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal of voltage (VSH / 2) to the gate terminal of the P-type MOSFET. When the logic value of the control signal is 1, the first gate drive circuit outputs a signal of voltage (VSH / 2) to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal of voltage VSH to the gate terminal of the P-type MOSFET. Attached Figure Description

[0008] Figure 1 This is a diagram showing the structure of a typical analog switch.

[0009] Figure 2 This is a diagram used to illustrate the function of the analog switch involved in the comparative example.

[0010] Figure 3 This is a diagram illustrating an example of the circuit configuration of the analog switch circuit according to the first embodiment.

[0011] Figure 4 A diagram showing the structure of the analog switching circuit according to the first embodiment.

[0012] Figure 5 This is a timing diagram showing the first operation example of the analog switching circuit according to the first embodiment.

[0013] Figure 6 This is a timing diagram showing the second operation example of the analog switching circuit according to the first embodiment.

[0014] Figure 7 This is a diagram used to explain the operation of the NMOS gate drive circuit and the PMOS gate drive circuit of the analog switch circuit according to the first embodiment.

[0015] Figure 8 This is a graph showing an example of the gate / source voltage of the analog switching circuit according to the first embodiment.

[0016] Figure 9 This is a flowchart illustrating the operation of the analog switching circuit according to the first embodiment.

[0017] Figure 10 This is a diagram showing a ΔΣ modulator as an example of a circuit to which the analog switching circuit of the first embodiment is applied.

[0018] Figure 11 This is a diagram illustrating an example of the circuit configuration of the differentiator and integrator in the ΔΣ modulator according to the first embodiment.

[0019] Figure 12 This diagram illustrates a configuration example in which an analog switching circuit is applied to the ΔΣ modulator according to the first embodiment. Detailed Implementation

[0020] Before providing a detailed description of the implementation method, the structure of the analog switch and the function of the comparative example will be explained. Figure 1 This is a diagram showing the structure of a typical analog switch.

[0021] The analog switch 10 is a CMOS (Complementary MOS) analog switch formed by connecting an N-type MOSFET (N-type Metal-Oxide-Semiconductor Field-Effect Transistor) 10n (hereinafter referred to as NMOS) and a P-type MOSFET (P-type Metal-Oxide-Semiconductor Field-Effect Transistor) 10p in parallel.

[0022] The source terminal (S) of NMOS10n and the source terminal (S) of PMOS10p are connected through the input terminal 10a of analog switch 10. The drain terminal (D) of NMOS10n and the drain terminal (D) of PMOS10p are connected through the output terminal 10b of analog switch 10.

[0023] Input an analog input signal IN to input terminal 10a. Output an analog output signal OUT from output terminal 10b.

[0024] Input the gate drive signal GN to the gate terminal (G) of NMOS10n, and input the gate drive signal GP to the gate terminal (G) of PMOS10p. Set the gate operating withstand voltage of NMOS10n and PMOS10p to VGT (where the unit of voltage and potential is, for example, volts, and the unit is omitted below).

[0025] The back gate terminal (B) of the NMOS10n is connected to ground, and the back gate terminal (B) of the PMOS10p is connected to the positive power supply. Here, the voltage VSH is higher than VGT, and is set to a voltage below (2×VGT) [VGT<VSH≤(2×VGT)]. At this time, the back gate operating withstand voltage is above the voltage VSH for both the NMOS10n and PMOS10p.

[0026] Output terminal 10b is connected to power supply 20. Power supply 20 maintains the potential of output terminal 10b at (VSH / 2). Therefore, the potential of the drain terminal (D) of NMOS 10n and the drain terminal (D) of PMOS 10p is both (VSH / 2).

[0027] Figure 2 This is a diagram used to illustrate the function of the analog switch 10 involved in the comparative example.

[0028] Before analog switch 10 is turned on (conducted), the voltage V_IN of the input signal IN is 0 or VSH.

[0029] If the gate drive signal GN with a voltage V_GN = VSH is input to the gate terminal (G) of NMOS10n, and the gate drive signal GP with a voltage V_GP = 0 is input to the gate terminal (G) of PMOS10p, then analog switch 10 is turned on.

[0030] If analog switch 10 is turned on, input terminal 10a and output terminal 10b are connected. Therefore, regardless of whether the voltage V_IN of the input signal IN is 0 or VSH before analog switch 10 is turned on (conducted), the potential of input terminal 10a, that is, the potential of the source terminal (S) of NMOS 10n and PMOS 10p, is (VSH / 2).

[0031] At this time, the gate / source voltage of NMOS10n is (VSH / 2), and the gate / source voltage of PMOS10p is (-VSH / 2) (refer to...). Figure 2 (Switch on / off section). Since (VGT / 2) < (VSH / 2) ≤ VGT, when analog switch 10 is on, the absolute values ​​of the gate / source voltages of NMOS10n and PMOS10p both satisfy the condition that the gate withstand voltage VGT is below.

[0032] On the other hand, if the gate drive signal GN with a voltage V_GN = 0 is input to the gate terminal (G) of NMOS10n, and the gate drive signal GP with a voltage V_GP = VSH is input to the gate terminal (G) of PMOS10p, then the analog switch 10 is turned off.

[0033] At this time, if the voltage V_IN of the input signal IN is VSH, then the gate / source voltage of NMOS10n is (-VSH), and the gate / source voltage of PMOS10p is 0. Alternatively, if the voltage V_IN of the input signal IN is 0, then the gate / source voltage of NMOS10n is 0, and the gate / source voltage of PMOS10p is VSH (refer to...). Figure 2 (The switch is open). Therefore, when analog switch 10 is open, the absolute value of either the gate / source voltage of NMOS10n or PMOS10p becomes higher than the gate withstand voltage VGT.

[0034] Referring to the accompanying drawings, the following describes the structure of an embodiment in which the analog switch 10 is open, and the gate / source voltage of NMOS 10n and PMOS 10p is at least the gate withstand voltage VGT, regardless of whether the voltage V_IN of the input signal IN is 0 or VSH.

[0035] (First Embodiment)

[0036] (constitute)

[0037] Figure 3 This is a diagram showing an example of the circuit configuration of the analog switch circuit 1 according to the first embodiment.

[0038] The analog signal output circuit 30 receives the input control signal CNT, generates an analog input signal IN corresponding to the control signal CNT, and outputs the generated input signal IN to the analog switch 10. The control signal CNT takes a logic value of "0" or "1". When CNT = 0, the analog signal output circuit 30 outputs the input signal IN with voltage V_IN = 0, and when CNT = 1, it outputs the input signal IN with voltage V_IN = VSH.

[0039] Figure 4 This is a diagram showing the structure of the analog switch circuit 1 according to the first embodiment.

[0040] The analog switch circuit 1 includes an analog switch 10, an NMOS gate drive circuit 11 (first gate drive circuit), and a PMOS gate drive circuit 12 (second gate drive circuit).

[0041] The NMOS gate drive circuit 11 is connected to the gate terminal (G) of the NMOS 10n of the analog switch 10. An enable signal EN and a control signal CNT are input to the NMOS gate drive circuit 11. The NMOS gate drive circuit 11 generates a gate drive signal GN with a voltage V_GN corresponding to the enable signal EN and the control signal CNT, and outputs it to the gate terminal (G) of the NMOS 10n.

[0042] The PMOS gate drive circuit 12 is connected to the gate terminal (G) of the PMOS 10p of the analog switch 10. An enable signal EN and a control signal CNT are input to the PMOS gate drive circuit 12. The PMOS gate drive circuit 12 generates a gate drive signal GP with a voltage V_GP corresponding to the enable signal EN and the control signal CNT, and outputs it to the gate terminal (G) of the PMOS 10p.

[0043] The enable signal EN takes a logic value of "0" or "1". When the enable signal EN is a logic value of "0", the analog switch 10 is open; when the enable signal EN is a logic value of "1", the analog switch 10 is on.

[0044] When the logic value of the enable signal EN is 0, the voltage V_IN of the input signal IN output from the analog signal output circuit 30 is applied to the source terminal (S) of the analog switch 10. The voltage V_IN applied to the source terminal (S) is 0 when the logic value of the control signal CNT is 0, and is VSH when the logic value of the control signal CNT is 1.

[0045] (effect)

[0046] Reference Figures 5-8 The operation of analog switch circuit 1 will be explained. Figure 5 This is a timing diagram showing the first operation example of the analog switch circuit 1 according to the first embodiment. Figure 6 This is a timing diagram showing the second operation example of the analog switch circuit 1 according to the first embodiment. Figure 7 This is a diagram used to explain the operation of the NMOS gate drive circuit 11 and the PMOS gate drive circuit 12 of the analog switch circuit 1 according to the first embodiment. Figure 8 This is a diagram showing an example of the gate / source voltage of the analog switching circuit 1 according to the first embodiment.

[0047] exist Figure 5 In the first action example shown, the logic value of the control signal CNT changes from "0" to "1" at time t1.

[0048] When the logic value of the control signal CNT is “0”, if switch 10 is open, the analog signal output circuit 30 outputs the input signal IN with voltage V_IN = 0.

[0049] When the control signal CNT = 0 and the enable signal EN = 0 (when OFF1 is off), such as Figure 7 As shown in the column where CNT=0, the NMOS gate drive circuit 11 outputs a gate drive signal GN with a voltage V_GN=0 (normal operation), and the PMOS gate drive circuit 12 outputs a gate drive signal GP with a voltage V_GP=(VSH / 2). Here, the voltage V_GP=(VSH / 2) of the gate drive signal GP output by the PMOS gate drive circuit 12 is lower than the normal voltage VSH by (VSH / 2).

[0050] At this time, since the voltage V_IN = 0, the gate / source voltage of NMOS10n is 0, and the gate / source voltage of PMOS10p is (VSH / 2) (refer to...). Figure 8 (Column where V_IN = 0 and the switch is off).

[0051] At time t1, the control signal CNT changes from 0 to 1, and the enable signal EN changes from 0 to 1. With the enable signal EN = 1, regardless of the logic value of the control signal CNT, the NMOS gate drive circuit 11 outputs a gate drive signal GN with voltage V_GN = VSH (normal operation), and the PMOS gate drive circuit 12 outputs a gate drive signal GP with voltage V_GP = 0 (normal operation). Therefore, the analog switch 10 is turned on, and the input terminal 10a and the output terminal 10b are connected. The potential of the input terminal 10a is (VSH / 2) (refer to...). Figure 5 The time graph of V_IN).

[0052] The gate / source voltage of NMOS10n and the gate / source voltage of PMOS10p when analog switch 10 is turned on are as follows: Figure 8 The switch connection is shown in the diagram, and... Figure 2 The switching on / off state is the same as shown in the comparative example. That is, the gate / source voltage of NMOS10n is (VSH / 2), and the gate / source voltage of PMOS10p is (-VSH / 2).

[0053] With the control signal CNT maintained at 1, at time t2, which is later than time t1, the enable signal EN changes from 1 to 0.

[0054] When the logic value of the control signal CNT is "1", if switch 10 is open, the analog signal output circuit 30 outputs the input signal IN of voltage V_IN = VSH.

[0055] With control signal CNT=1 and enable signal EN=0 (when OFF2 is off), such as Figure 7 As shown in the column where CNT=1, the NMOS gate drive circuit 11 outputs a gate drive signal GN with a voltage V_GN=(VSH / 2), and the PMOS gate drive circuit 12 outputs a gate drive signal GP with a voltage V_GP=VSH (normal operation). Here, the voltage V_GN=(VSH / 2) of the gate drive signal GN output by the NMOS gate drive circuit 11 is a voltage (VSH / 2) higher than the normal voltage 0.

[0056] At this point, since the voltage V_IN = VSH, the gate / source voltage of NMOS10n is (-VSH / 2), and the gate / source voltage of PMOS10p is 0 (refer to...). Figure 8 The column where V_IN = VSH and the switch is off.

[0057] Therefore, as Figure 8 As shown, in any one of the following scenarios—when analog switch 10 is ON, when analog switch 10 is OFF1, and when analog switch 10 is OFF2—the absolute values ​​of the gate / source voltage of NMOS 10n and the gate / source voltage of PMOS 10p are maintained below the gate withstand voltage VGT.

[0058] exist Figure 6 In the second example of operation shown, the logic value of the control signal CNT changes from "1" to "0" at time t3. In addition, the logic value of the enable signal EN changes from "0" to "1" at time t3, and changes from "1" to "0" at time t4, which is later than time t3.

[0059] In the second operating example, the NMOS gate drive circuit 11 and the PMOS gate drive circuit 12 are also... Figure 5 Similarly, in the first action example shown, the action of OFF2 is performed when CNT=1 and EN=0, the action of turning on is performed regardless of the logic value of CNT when EN=0, and the action of OFF1 is performed when CNT=0 and EN=0.

[0060] Figure 9 This is a flowchart illustrating the function of the analog switch circuit 1 according to the first embodiment.

[0061] If processing begins, analog switch circuit 1 branches the processing based on whether the enable signal EN=0 (step S1).

[0062] Here, when the enable signal EN=1, the NMOS gate drive circuit 11 and PMOS gate drive circuit 12 of the analog switch circuit 1 perform the normal operation of turning on the analog switch circuit 1 (step S2).

[0063] Additionally, when the enable signal EN = 0 in step S1, the analog switch circuit 1 enables the processing branch (step S3) based on whether the control signal CNT = 0.

[0064] Here, when the control signal CNT = 0, the NMOS gate drive circuit 11 of the analog switch circuit 1 operates normally and makes V_GN = 0, and the PMOS gate drive circuit 12 reduces the voltage by (VSH / 2) compared to the normal voltage VSH, so that V_GP = (VSH / 2) (step S4).

[0065] On the other hand, when the control signal CNT = 1 in step S3, the NMOS gate drive circuit 11 of the analog switch circuit 1 raises the voltage by (VSH / 2) compared to the normal voltage 0, so that V_GN = (VSH / 2), and the PMOS gate drive circuit 12 performs normal operation so that V_GP = VSH (step S5).

[0066] If steps S2, S4, or S5 are performed, then the analog switch circuit 1 ends. Figure 9 The processing.

[0067] Figure 10 This is a diagram showing a ΔΣ modulator 40 as an example of the circuit of the analog switch circuit 1 according to the first embodiment.

[0068] The ΔΣ modulator 40 is an analog-to-digital converter that processes the input analog signal AIN to generate a digital signal DOUT and outputs the digital signal DOUT. The ΔΣ modulator 40 includes a differentiator 41, an integrator 42, a comparator 43, and a digital-to-analog converter (DAC) 44.

[0069] The analog signal AIN is input to differentiator 41, where it is subtracted from the analog signal from DAC 44. Differentiator 41 outputs the subtracted analog signal to integrator 42. Integrator 42 integrates the input analog signal to output analog signal VOUT. Comparator 43 compares the voltage of analog signal VOUT with a specified voltage, and based on the comparison result, quantizes analog signal VOUT to generate a 1-bit digital signal DOUT. The digital signal DOUT generated by comparator 43 is output to the external ΔΣ modulator 40 and also to DAC 44. DAC 44 converts the digital signal DOUT input from comparator 43 into an analog signal and outputs it to differentiator 41.

[0070] Figure 11 This is a diagram illustrating an example of the circuit configuration of the differentiator 41 and the integrator 42 in the ΔΣ modulator 40 according to the first embodiment. Figure 11 It indicates that in Figure 10 Example of circuit configuration for the part enclosed by dashed lines.

[0071] Differentiator 41 and integrator 42 include, for example, switched capacitor (SC) circuit 45, operational amplifier 46, capacitor 47 and analog switch circuit 1.

[0072] The SC circuit 45 includes a capacitor 45a, a switch 45b, a switch 45c, a switch 45d, and a switch 45e. Switch 45b, capacitor 45a, and switch 45e are connected in series sequentially. Switch 45c is connected between switch 45b and capacitor 45a, and switch 45d is connected between capacitor 45a and switch 45e. Furthermore, an analog signal AIN is input to switch 45b, switch 45c is connected to DAC 44, and switch 45d is connected to a 20A power supply (refer to...). Figure 12 The switch 45e is connected to the inverting input terminal 46a of the operational amplifier 46.

[0073] The non-inverting input terminal 46b of operational amplifier 46 is connected to a power supply of 20A (reference) at voltage (VSH / 2). Figure 12 Therefore, the voltage at the inverting input terminal 46a, which is virtually shorted to the non-inverting input terminal 46b, becomes (VSH / 2).

[0074] Capacitor 47 is connected in the feedback path of operational amplifier 46, specifically between output terminal 46c and inverting input terminal 46a. Analog switch circuit 1 is connected across capacitor 47. Thus, integrator 42 is configured as an SC integrator, which is an inverting analog integrator that inverts and integrates the signal input from inverting input terminal 46a.

[0075] SC circuit 45 performs a crawling operation. If switches 45b and 45d are turned on and switches 45c and 45e are turned off, the analog signal AIN is connected to capacitor 45a.

[0076] Additionally, if switches 45b and 45d are open and switches 45c and 45e are closed, then DAC44 is connected to capacitor 45a. At this time, since the inverted integration signal from integrator 42 is input to capacitor 45a via comparator 43 and DAC44, the differentiator 41 operates by connecting capacitor 45a to DAC44.

[0077] The analog switch circuit 1 connected to both ends of capacitor 47 can charge capacitor 47 if it is disconnected, and discharge capacitor 47 if it is connected.

[0078] The analog signal VOUT output from the output terminal 46c of the operational amplifier 46 becomes a pulse wave that changes under voltage 0 and voltage VSH, and is input to the comparator 43.

[0079] Comparator 43 compares the voltage of the analog signal VOUT with a specified voltage, such as (VSH / 2). If the voltage is greater than (VSH / 2), it outputs a logic value "1"; if it is less than (VSH / 2), it outputs a logic value "0". Therefore, based on whether the logic value of the digital signal DOUT is 1 or 0, it is possible to determine whether the voltage of the analog signal VOUT is VSH or 0.

[0080] The digital signal DOUT output from comparator 43, as described above, is output to the external ΔΣ modulator 40 and DAC 44, and is also output as a control signal CNT to analog switch circuit 1 (see reference). Figure 12 ).

[0081] Figure 12 This diagram illustrates a configuration example in which the analog switching circuit 1 is applied to the ΔΣ modulator 40 according to the first embodiment.

[0082] DAC44, SC circuit 45, operational amplifier 46, and capacitor 47 and Figure 3 The analog signal output circuit 30 corresponds to this.

[0083] The output terminal 10b of analog switch 10 is connected to the inverting input terminal 46a, which is virtually short-circuited by the non-inverting input terminal 46b. Therefore, the potential of the output terminal 10b is maintained at (VSH / 2) as described above.

[0084] The input terminal 10a of the analog switch 10 is connected to the output terminal 46c of the operational amplifier 46. Therefore, the analog signal VOUT, which varies with voltage 0 and voltage VSH, is input to the input terminal 10a as the input signal IN.

[0085] The analog switch circuit 1 operates as described above based on the enable signal EN and the control signal CNT. That is, when the analog switch 10 is open, the voltage of the analog signal VOUT input from the operational amplifier 46 to the input terminal 10a of the analog switch 10 is determined based on the digital signal DOUT (i.e., the control signal CNT) fed back to the DAC 44 side, and the NMOS gate drive circuit 11 and the PMOS gate drive circuit 12 control the voltages of the gate drive signals GN and GP. Thus, when the switch is open, the absolute value of the gate / source voltage of the analog switch circuit 1 can be maintained below the gate withstand voltage VGT. In addition, the case where the absolute value of the gate / source voltage of the analog switch circuit 1 is maintained below the gate withstand voltage VGT when the switch is on is as described above.

[0086] According to the first embodiment, the voltages of the gate drive signals GN and GP when the switch is off can be controlled according to the control signal CNT. Therefore, even when the gate drive signals GN and GP, which have a voltage higher than the gate withstand voltage VGT, are output to the gate terminal (G) of the analog switch 10 when the switch is on, the absolute value of the gate / source voltage will not exceed the gate withstand voltage VGT, regardless of whether the analog switch 10 is on or off.

[0087] Therefore, the transistor constituting the analog switch 10 will not be damaged, and its reliability will not be reduced. Moreover, since the analog switch circuit 1 can be constructed using transistors with common gate voltage ratings, the analog switch circuit 1 can be made low-cost.

[0088] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention and its equivalents described in the technical solution.

Claims

1. An analog switch circuit, characterized by, have: An analog switch connects the source terminals of an N-type MOSFET and a P-type MOSFET with a gate operating withstand voltage of VGT to each other and connects their drain terminals to each other. The N-type MOSFET and the P-type MOSFET are connected in parallel. When the voltage above VGT and below 2×VGT is set as VSH, the potential of the drain terminal is VSH / 2. The first gate drive circuit, receiving an enable signal and a control signal, is connected to the gate terminal of the N-type MOSFET of the analog switch; and The second gate drive circuit, which receives the aforementioned enable signal and control signal, is connected to the gate terminal of the aforementioned P-type MOSFET of the aforementioned analog switch. When the logic value of the above enable signal is 0, Depending on whether the logic value of the control signal is 0 or 1, a voltage of 0 or a voltage VSH is applied to the source terminal of the analog switch. When the logic value of the aforementioned control signal is 0, the first gate drive circuit outputs a signal indicating a voltage of 0 to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a signal indicating a voltage of VSH / 2 to the gate terminal of the P-type MOSFET. When the logic value of the control signal is 1, the first gate drive circuit outputs a voltage VSH / 2 signal to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a voltage VSH signal to the gate terminal of the P-type MOSFET.

2. The analog switch circuit according to claim 1, characterized in that, When the logic value of the above enable signal is 1, Regardless of the logic value of the aforementioned control signal, the first gate drive circuit outputs a voltage VSH signal to the gate terminal of the N-type MOSFET, and the second gate drive circuit outputs a voltage 0 signal to the gate terminal of the P-type MOSFET. The source terminal and the drain terminal of the aforementioned analog switch are connected and the potential is VSH / 2.

3. The analog switch circuit according to claim 1, characterized in that, The analog switch circuit described above also includes an analog signal output circuit, which receives the control signal and outputs a signal of voltage 0 or voltage VSH to the source terminal of the analog switch according to whether the logic value of the control signal is 0 or 1.

4. The analog switch circuit according to claim 1, characterized in that, The back-gate operating withstand voltage of the aforementioned N-type MOSFET and the back-gate operating withstand voltage of the aforementioned P-type MOSFET in the analog switch are above voltage VSH.

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