output buffer

Abstract

An output buffer includes a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and is configured to generate a gate control signal to a gate of the first transistor. The output buffer is selectively operable in an input mode and a failsafe mode, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on a voltage of the pad when the voltage of the pad is a high voltage level.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to buffers, and more specifically, to output buffers with pad tracking circuitry that prevent leakage current from occurring. Background Technology

[0002] In traditional general purpose input / output (GPIO) designs, the output buffer and input buffer are connected to the same pad, and the GPIO can operate in output mode, input mode, or fail-safe mode. Regarding the three GPIO modes, when the GPIO operates in output mode, the output buffer is enabled so that a signal can be output to another device through the pad; when the GPIO operates in input mode, the output buffer is disabled; and when the GPIO operates in fail-safe mode, the output buffer is disabled and no power supply voltage is applied to the output buffer, while a high voltage is supplied to the pad. However, in the above design, if the power supply voltage rises or falls, the output buffer will generate leakage current; that is, the output buffer will leak current when switching between input mode and fail-safe mode. Summary of the Invention

[0003] One of the objectives of this invention is to provide an output buffer that can prevent leakage current from being generated.

[0004] The following summary is illustrative only and is not intended to be limiting in any way. That is, it provides an overview to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Therefore, the following summary is neither intended to identify the essential features of the claimed subject matter nor to define the scope of the claimed subject matter.

[0005] This invention provides an output buffer, including a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a power supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and generates a gate control signal to the gate of the first transistor. The output buffer operates in at least an input mode and a fail-safe mode. When the output buffer operates in the input mode, the pad tracking circuit generates the gate control signal to disable the first transistor, and the second transistor is also disabled. When the output buffer operates in the fail-safe mode, the first transistor is de-energized, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on the voltage of the pad. Specifically, when the voltage of the pad is high, the pad tracking circuit generates the gate control signal to the gate of the first transistor based on the voltage of the pad.

[0006] In some embodiments, when the voltage of the pad is at a high voltage level, the pad tracking circuit always generates the gate control signal to the gate of the first transistor according to the voltage of the pad, and the voltage level of the gate control signal is substantially equal to the voltage of the pad.

[0007] In some embodiments, when the voltage of the pad is at a high voltage level, the pad tracking circuit generates a base control signal to the base of the first transistor based on the voltage of the pad.

[0008] In some embodiments, when the voltage of the pad is at a high voltage level, the pad tracking circuit always generates the gate control signal and the base control signal to the gate and base of the first transistor according to the voltage of the pad, and the voltage level of the gate control signal and the voltage level of the base control signal are substantially equal to the voltage of the pad.

[0009] In some embodiments, when the output buffer operates in the input mode, the power supply voltage has a fixed voltage level; and the pad tracking circuit refers to the voltage of the pad to determine whether to generate the gate control signal based on the voltage of the pad or based on the power supply voltage having the fixed voltage level.

[0010] In some embodiments, if the voltage of the pad has a high voltage level, the pad tracking circuit generates the gate control signal with reference to the voltage of the pad, and the voltage level of the gate control signal is substantially equal to the voltage of the pad; if the voltage of the pad has a low voltage level, the pad tracking circuit generates the gate control signal with reference to the power supply voltage having the fixed voltage level, and the voltage level of the gate control signal is substantially equal to the power supply voltage having the fixed voltage level.

[0011] In some embodiments, the pad tracking circuit refers to the voltage of the pad to determine whether to generate a base control signal to the base of the first transistor based on the voltage of the pad or based on a power supply voltage having the fixed voltage level.

[0012] In some embodiments, if the pad voltage has a high voltage level, the pad tracking circuit generates the gate control signal and the base control signal with reference to the pad voltage, and the voltage levels of the gate control signal and the base control signal are substantially equal to the pad voltage; if the pad voltage is a low voltage level, the pad tracking circuit generates the gate control signal and the base control signal with reference to the power supply voltage having the fixed voltage level, wherein the voltage levels of the gate control signal and the base control signal are substantially equal to the voltage of the power supply voltage having the fixed voltage level.

[0013] In some embodiments, the pad tracking circuit includes: a first multiplexer for receiving a plurality of input signals and selecting one of the plurality of input signals as the gate control signal, wherein the plurality of input signals includes a first input signal having the fixed voltage level and a second input signal having the voltage of the pad.

[0014] In some embodiments, the pad tracking circuit refers to the voltage of the pad to determine whether to generate the base control signal to the base of the first transistor based on the voltage of the pad or based on the power supply voltage having the fixed voltage level; and the pad tracking circuit includes a second multiplexer for receiving the plurality of input signals and selecting one of the plurality of input signals as the base control signal.

[0015] These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0016] The accompanying drawings (in which the same numerals denote the same components) illustrate embodiments of the present invention. The included drawings are used to provide a further understanding of embodiments of the present disclosure, and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to actual dimensions in order to clearly illustrate the concepts of the embodiments of the present disclosure.

[0017] Figure 1 This is a schematic diagram illustrating the operation of the output buffer in output mode according to an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram illustrating the operation of the output buffer in input mode according to an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram illustrating the operation of the output buffer in fail-safe mode according to an embodiment of the present invention.

[0020] Figure 4 This illustrates a conventional output buffer where the voltage at the pads exhibits an IR drop when it switches between input mode and fail-safe mode.

[0021] Figure 5 This demonstrates that no leakage current occurred in the embodiments of the present invention.

[0022] Figure 6 This is a schematic diagram of a pad tracking circuit according to an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of a first multiplexer and a second multiplexer operating in input mode according to an embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of a first multiplexer and a second multiplexer operating in fail-safe mode according to an embodiment of the present invention.

[0025] Figure 9 This is a schematic diagram of an output buffer according to another embodiment of the present invention.

[0026] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0027] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0028] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0029] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0030] Figure 1 This is a schematic diagram illustrating the operation of the output buffer 100 in output mode according to an embodiment of the present invention. Figure 1As shown, the output buffer 100 includes a control circuit 110, a pad-tracking circuit 120, a P-type transistor MP1, and an N-type transistor MN1. The output buffer 100 is powered by a supply voltage VDIO1 and a reference voltage VSS. The supply voltage VDIO1 can be equal to a fixed high voltage VDDQ, and the reference voltage VSS can be equal to 0V (such as ground voltage). Furthermore, the output buffer 100 is coupled to a pad 104, which is selectively coupled to a specific voltage provider 102. This specific voltage provider 102 is configured to selectively supply the supply voltage VDIO2 to the pad 104 via a resistor R.

[0031] When the output buffer 100 operates in output mode, it is configured to output a high voltage (i.e., logic value "1") or a low voltage (i.e., logic value "0") to the pad 104, and a specific voltage provider 102 is disabled (power supply voltage VDIO2 is not connected to the pad). Specifically, the control circuit 110 receives two control signals VC_I and VC_E, where control signal VC_E indicates whether the output buffer 100 operates in output mode, and control signal VC_I controls whether the output buffer 100 outputs a high or low voltage. In this embodiment, when the control signal VC_E equals "1", the control circuit 110 determines that it is in output mode. If the control signal VC_I equals "0", the control circuit 110 controls the pad tracking circuit 120 to generate a high-voltage (e.g., VDDQ) gate control signal PG1 to the gate of transistor MP1 and a high-voltage (e.g., VDDQ) bulk control signal PB1 to the base of transistor MP1 to disable transistor MP1. The control circuit 110 also generates a high-voltage (e.g., VDDQ) gate control signal NG1 to the gate of transistor MN1 to enable transistor MN1. At this time, since transistor MN1 is turned on, the pad 104 has a low voltage, for example, 0V. On the other hand, when the control signal VC_E equals "1", the control circuit 110 determines that it is in output mode. If the control signal VC_I equals "1", the control circuit 110 controls the pad tracking circuit 120 to generate a low-voltage (e.g., 0V) gate control signal PG1 to the gate of transistor MP1 and a high-voltage (e.g., VDDQ) base control signal PB1 to the base of transistor MP1 to enable transistor MP1. The control circuit 110 also generates a low-voltage (e.g., 0V) gate control signal NG1 to the gate of transistor MN1 to disable transistor MN1. At this time, since transistor MP1 is turned on, pad 104 has a high voltage, for example, VDDQ.

[0032] Figure 2 This is a schematic diagram illustrating the operation of the output buffer 100 in input mode according to an embodiment of the present invention. Figure 2As shown, when the output buffer 100 operates in input mode, the output buffer 100 and the specific voltage provider 102 are disabled, and the input buffer (not shown) is configured / used to receive signals at pad 104. Specifically, the control circuit 110 receives two control signals VC_I and VC_E, wherein the control signal VC_E is used to indicate whether the output buffer 100 operates in input mode. In this embodiment, when the control signal VC_E equals "0", the control circuit 110 determines that it is in input mode. Furthermore, when the voltage VPAD at pad 104 has a low voltage level (e.g., 0V), regardless of whether the control signal VC_I is equal to 0 or 1, the control circuit 110 controls the pad tracking circuit 120 to generate a high-voltage (e.g., VDDQ) gate control signal PG1 to the gate of transistor MP1, and a high-voltage (e.g., VDDQ) base control signal PB1 to the base of transistor MP1 to disable transistor MP1. Additionally, the control circuit 110 also generates a low-voltage (e.g., 0V) gate control signal NG1 to the gate of transistor MN1 to disable transistor MN1. At this time, the output buffer 100 does not provide any signal to pad 104.

[0033] Figure 3 This is a schematic diagram illustrating the operation of the output buffer 100 in fail-safe mode according to an embodiment of the present invention. Figure 3 As shown, when the output buffer 100 operates in fail-safe mode, the control circuit 110 of the output buffer 100 and the transistor MP1 are powered down (e.g., the power supply voltage VDIO1 becomes 0V), a specific voltage provider 102 is enabled to provide a high voltage / high level / high voltage level to the pad 104 (in this embodiment, the voltage at the pad 104 is VPAD, which is very close to / substantially equal to / completely equal to the power supply voltage VDIO2, and the power supply voltage VDIO2 may be equal to or higher than VDDQ), and the pad tracking circuit 120 can be powered by the power supply voltage VDIO2 to generate a gate control signal PG1 and a base control signal PB1 based on the voltage VPAD at the pad 104. Specifically, when the output buffer 100 operates in fail-safe mode, the pad tracking circuit 120 generates a gate control signal PG1 with voltage VPAD and a base control signal PB1 with voltage VPAD to the gate and body of the transistor MP1 to disable the transistor MP1, thereby preventing leakage current. Furthermore, in this embodiment, VDDQ is provided by a voltage source, and VDDQ always has a high voltage level (i.e., a fixed high voltage level) regardless of whether the output buffer 100 operates in output mode or input mode.

[0034] In conventional technology, when the output buffer 100 operates in input mode, the control circuit 110 always controls the pad tracking circuit 120 to generate a gate control signal PG1 with VDDQ to disable transistor MP1. However, when the output buffer 100 switches between input mode and fail-safe mode, i.e., when the power supply voltage VDIO1 increases from 0V to VDDQ or decreases from VDDQ to 0V, transistor MP1 is enabled for a period of time, thus causing leakage current. Specifically, refer to... Figure 4 When the power supply voltage VDIO1 coupled to transistor MP1 ramps up or ramps down, the gate control signal PG1 and the base control signal PB1 drop, and transistor MP1 is enabled. As a result, leakage current flows from pad 104 to the source electrode of transistor MP1, causing voltage VPAD to have an IR drop. To address this issue, the pad tracking circuit 120 is configured to always provide voltage VPAD at pad 104 as the gate control signal PG1 when the voltage VPAD at the pad is at a high voltage level (e.g., this high voltage level refers to any voltage level higher than the default value, which is a predefined reasonable value; in one example, the default value can be 0V. Of course, to avoid voltage fluctuations caused by changes in PVT conditions or other factors, the default value can also be set to other reasonable values ​​greater than 0V; the specific setting can be combined with actual needs, and the present invention does not impose any limitations on this). Optionally, voltage VPAD at pad 104 is also provided as the base control signal PB1. This embodiment of the invention uses the voltage VPAD at pad 104 as an example to illustrate the gate control signal PG1 and the base control signal PB1. That is, regardless of the output buffer's mode (e.g., whether in input mode, fail-safe mode, or undergoing mode switching), and / or regardless of changes in the power supply voltage VDIO1, once the voltage VPAD at the pad is high, the pad tracking circuit 120 always provides the voltage VPAD at pad 104 as the gate control signal PG1 and the base control signal PB1. Therefore, there will be no leakage current between pad 104 and the power supply voltage VDIO1. Figure 5As shown. In some embodiments, whether the voltage VPAD at pad 104 is high can be determined by detecting the voltage VPAD at pad 104, or by determining whether the power supply voltage VDIO2 provided by a specific voltage provider 102 is turned on to pad 104, or by other means. Specifically, the embodiments of the present invention do not limit this. Any circuit that can always provide the voltage VPAD at pad 104 as the gate control signal PG1 (and the base control signal PB1) when the voltage VPAD at pad 104 is high can be used as the pad tracking circuit 120 in the embodiments of the present invention.

[0035] Figure 6 This is a schematic diagram of a pad tracking circuit 120 according to an embodiment of the present invention. Figure 6As shown, the pad tracking circuit 120 includes a first multiplexer 610 and a second multiplexer 620. The first multiplexer 610 is configured to receive multiple input signals, such as VDDQ and VPAD (the voltage at pad 104), and select one of the input signals as the gate control signal PG1 according to a first selection signal SEL1. The second multiplexer 620 is configured to receive multiple input signals, such as VDDQ and VPAD, and select one of the input signals as the base control signal PB1 according to a second selection signal SEL2. In this embodiment, when the power supply voltage VDIO1 is equal to 0V and the output buffer 100 operates in fail-safe mode, the first multiplexer 610 outputs the voltage VPAD at pad 104 as the gate control signal PG1, and the second multiplexer 620 outputs the voltage VPAD at pad 104 as the base control signal PB1. That is, if VPAD is a low voltage, such as 0V, then the gate control signal PG1 and the base control signal PB1 are at that low voltage (e.g., 0V); if VPAD is a high voltage (e.g., VDIO2, which is illustrated as VDDQ in this embodiment), then the gate control signal PG1 and the base control signal PB1 are equal to that high voltage (e.g., VDDQ). Furthermore, when the power supply voltage VDIO1 is equal to VDDQ and the output buffer 100 operates in input mode, if VPAD is a low voltage (e.g., 0V), then the first multiplexer 610 outputs VDDQ as the gate control signal PG1, and the second multiplexer 620 outputs VDDQ as the base control signal PB1. If VPAD is high (e.g., VDIO2, which is exemplified as VDDQ in this embodiment), then the VPAD at pad 104 of the first multiplexer 610 is used as the gate control signal PG1, and the VPAD at pad 104 of the second multiplexer 620 is used as the base control signal PB1, regardless of the output buffer's mode. Furthermore, in input mode, the first selection signal SEL1 and the second selection signal SEL2 can be any signal capable of indicating the level of VPAD.

[0036] exist Figure 6 In the illustrated embodiment, regardless of the mode (input mode or fail-safe mode), when pad 104 receives a high voltage (such as VDIO2) from a specific voltage provider 102 (or, when the voltage VPAD at pad 104 is at a high voltage level / high level), the pad tracking circuit 120 always provides the voltage VPAD at pad 104 as the gate control signal PG1 and the base control signal PB1 to prevent the transistor MP1 from generating leakage current when the power supply voltage VDIO1 rises or falls.

[0037] Figure 7This is a schematic diagram illustrating the first multiplexer 610 and the second multiplexer 620 when the output buffer 100 operates in input mode, according to an embodiment of the present invention. Figure 7 As shown, the first multiplexer 610 includes P-type transistors MP2-MP4 and N-type transistors MN2-MN3. Transistors MP2 and MN2 act as transmission gates, selectively outputting VDDQ as the gate control signal PG1. Transistors MP3 and MN3 are coupled between VPAD and VSS. Transistor MP4 is used to selectively output VPAD as the gate control signal PG1. In the first multiplexer 610, transistors MN2, MP3, and MN3 are controlled by an enable signal EN (e.g., EN=0 enables the corresponding P-type transistor, and EN=1 disables the corresponding P-type transistor). Transistor MP2 is controlled by the output signals of transistors MP3 and MN3. Furthermore, the second multiplexer 620 includes P-type transistors MP5-MP7 and N-type transistor MN4. Transistors MP5 and MN4 are coupled between the power supply voltage VDIO1 and VSS, and transistors MP6 and MP7 are coupled between the power supply voltage VDIO1 and VPAD. In the second multiplexer 620, transistors MP5, MN4 and MP6 are controlled by voltage VPAD, transistor MP7 is controlled by the output signals of transistors MP5 and MN4, the output signals of transistors MP5 and MN4 are also used to control transistor MP4 of the first multiplexer 610, and the output signals of transistors MP6 and MP7 (such as drain signals) are used as base control signals PB1.

[0038] exist Figure 7 In the operation of the first multiplexer 610 and the second multiplexer 620 shown, when the enable signal EN has a low voltage level (e.g., equal to 0V) and the voltage VPAD is high (e.g., VDDQ), transistors MP2, MN2, MN3, MP5, and MP6 are disabled, while transistors MP3, MP4, MN4, and MP7 are enabled, causing the gate control signal PG1 and the base control signal PB1 to equal VPAD. Conversely, when the enable signal EN has a high voltage level (e.g., high level) and the voltage VPAD is low (e.g., 0V), transistors MP3, MP4, MN4, and MP7 are disabled, while transistors MN2, MN3, MP2, MP5, and MP6 are enabled, causing the gate control signal PG1 and the base control signal PB1 to equal VDDQ.

[0039] Figure 8 This is a schematic diagram illustrating the first multiplexer 610 and the second multiplexer 620 when the output buffer 100 operates in fail-safe mode, according to an embodiment of the present invention. Figure 8As shown, regardless of whether the voltage VPAD is high or low, the gate control signal PG1 and the base control signal PB1 are equal to VPAD. For example, please refer to [the documentation / reference]. Figure 6 When the output buffer is in fail-safe mode and VPAD = 0 (low level), PG1 = 0V and PB1 = 0V; and when the output buffer is in fail-safe mode and VPAD = 1 (high level), PG1 = VPAD and PB1 = VPAD.

[0040] It is important to note that Figures 6 to 8 The embodiments shown are for illustrative purposes and not for limiting the invention. In other embodiments, the pad tracking circuit 120 may have other circuit designs as long as it can always provide the voltage VPAD at pad 104 as the gate control signal PG1 and the base control signal PB1 when the power supply voltage VDIO1 rises and falls, and the invention does not limit this.

[0041] exist Figures 1 to 3 In the illustrated embodiment, the output buffer 100 includes only one P-type transistor MP1 and only one N-type transistor MN1 as the output stage. However, in other embodiments, the output stage may have more than one P-type transistor and / or more than one N-type transistor. Figure 9 For example, the output stage includes P-type transistors MP1-MPN and N-type transistors MN1-MNM connected in cascode, and the P-type transistors MP1-MPN and N-type transistors MN1-MNM are controlled by control signals PG1-PGM and NG1-NGM, respectively.

[0042] In short, in the output buffer of this invention, when the voltage VPAD at the pad is high, the pad tracking circuit always provides gate control signals and base control signals that are substantially equal to the voltage at the pad to control the P-type transistor. Therefore, even when the output buffer switches between input mode and fail-safe mode, and the power supply voltage of the P-type transistor rises or falls, no leakage current flows through the P-type transistor.

[0043] The use of ordinal terms such as “first,” “second,” and “third” in the claims to modify patent elements does not in itself indicate any priority, order, or sequence of one patent element relative to another, or the chronological order of the actions of the method, but is merely used as a marker to distinguish one patent element with the same name from another element with the same name.

[0044] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. An output buffer, comprising: The first transistor is coupled between the power supply voltage and the output node, wherein the output node is coupled to the pad; The second transistor is coupled between the output node and the reference voltage; A pad tracking circuit, coupled to the first transistor, is used to generate a gate control signal to the gate of the first transistor; The output buffer operates in at least two modes: an input mode and a fail-safe mode. When the output buffer operates in the input mode, the pad tracking circuit generates a gate control signal to disable the first transistor, and the second transistor is also disabled. When the output buffer operates in the fail-safe mode, the first transistor is de-energized, and the pad tracking circuit generates a gate control signal to the gate of the first transistor based on the voltage of the pad. Specifically, when the output buffer operates in the input mode, the power supply voltage has a fixed voltage level. If the pad voltage has a high voltage level, the pad tracking circuit generates the gate control signal with reference to the pad voltage, and the voltage level of the gate control signal is substantially equal to the pad voltage. If the pad voltage has a low voltage level, the pad tracking circuit generates the gate control signal with reference to the power supply voltage having the fixed voltage level, and the voltage level of the gate control signal is substantially equal to the power supply voltage having the fixed voltage level.

2. The output buffer as described in claim 1, characterized in that, When the voltage of the pad is at a high voltage level, the pad tracking circuit always generates the gate control signal to the gate of the first transistor according to the voltage of the pad, and the voltage level of the gate control signal is basically equal to the voltage of the pad.

3. The output buffer as described in claim 1, characterized in that, When the voltage of the pad is at a high voltage level, the pad tracking circuit generates a base control signal to the base of the first transistor based on the voltage of the pad.

4. The output buffer as described in claim 3, characterized in that, When the voltage of the pad is at a high voltage level, the pad tracking circuit always generates the gate control signal and the base control signal to the gate and base of the first transistor according to the voltage of the pad, and the voltage level of the gate control signal and the voltage level of the base control signal are basically equal to the voltage of the pad.

5. The output buffer as described in claim 1, characterized in that, The pad tracking circuit refers to the voltage of the pad to determine whether to generate a base control signal to the base of the first transistor based on the voltage of the pad or based on a power supply voltage having the fixed voltage level.

6. The output buffer as described in claim 5, characterized in that, If the pad voltage is high, the pad tracking circuit generates the gate control signal and the base control signal with reference to the pad voltage, and the voltage levels of the gate control signal and the base control signal are substantially equal to the pad voltage; if the pad voltage is low, the pad tracking circuit generates the gate control signal and the base control signal with reference to the power supply voltage having the fixed voltage level, wherein the voltage levels of the gate control signal and the base control signal are substantially equal to the power supply voltage having the fixed voltage level.

7. An output buffer, characterized in that, The output buffer includes: The first transistor is coupled between the power supply voltage and the output node, wherein the output node is coupled to the pad; The second transistor is coupled between the output node and the reference voltage; A pad tracking circuit, coupled to the first transistor, is used to generate a gate control signal to the gate of the first transistor; The output buffer operates in at least two modes: an input mode and a fail-safe mode. When the output buffer operates in the input mode, the pad tracking circuit generates a gate control signal to disable the first transistor, and the second transistor is also disabled. When the output buffer operates in the fail-safe mode, the first transistor is de-energized, and the pad tracking circuit generates a gate control signal to the gate of the first transistor based on the voltage of the pad. When the voltage of the pad is at a high voltage level, the pad tracking circuit generates the gate control signal to the gate of the first transistor based on the voltage of the pad. The pad tracking circuit includes: A first multiplexer is configured to receive multiple input signals and select one of the multiple input signals as the gate control signal, wherein the multiple input signals include a first input signal having a fixed voltage level and a second input signal having the voltage of the pad.

8. The output buffer as described in claim 7, characterized in that, The pad tracking circuit refers to the voltage of the pad to determine whether to generate a base control signal to the base of the first transistor based on the voltage of the pad or based on the power supply voltage having the fixed voltage level. In addition, the pad tracking circuit includes: The second multiplexer is used to receive the multiple input signals and select one of the multiple input signals as the base control signal.

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