Transmitting and receiving circuit

Abstract

Embodiments of the present application relate to a transceiving circuit. A transceiving circuit is provided which has a simple circuit structure. The transceiving circuit has a first circuit, a second circuit, and an insulating element. The first circuit generates a second clock signal by high-frequencying a first clock signal. The insulating element transmits the second clock signal to the second circuit as a third clock signal. The second circuit transmits a first data signal in accordance with the third clock signal. The insulating element transmits the first data signal as a second data signal. The first circuit receives the second data signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to transceiver circuits. Background Technology

[0002] There are known transceiver circuits capable of bidirectional signal transmission between two circuits connected via insulating elements such as transformers or converters. Typically, such transceiver circuits use two insulating elements: one for transmission from one circuit to another, and another for transmission from one circuit to the other.

[0003] There are also transceiver circuits that can transmit bidirectionally using a single insulating element. However, to replace this with a single insulating element for bidirectional transmission, additional circuitry such as a receiving timing circuit is required. As a result, the overall transceiver circuit may not necessarily be a simple circuit structure. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a transceiver circuit with a simple circuit structure.

[0005] Means for solving technical problems

[0006] The transceiver circuit of the embodiment includes: a first circuit capable of transmitting and receiving signals; a second circuit capable of transmitting and receiving signals; and an insulating element that electrically isolates the first circuit and the second circuit and is capable of transmitting a signal sent from one of the first circuit and the second circuit to the other. The first circuit has a first terminal into which a first clock signal is input, generates a second clock signal by increasing the frequency of the first clock signal, and transmits the second clock signal to the second circuit via the insulating element. The second circuit receives a third clock signal after the second clock signal is delayed via the insulating element, and transmits a first data signal to the first circuit via the insulating element in accordance with the third clock signal. The first circuit receives a second data signal after the first data signal is delayed via the insulating element.

[0007] Based on the transceiver circuit structure described above, bidirectional transmission can be achieved through a simple circuit structure. Attached Figure Description

[0008] Figure 1 This is a diagram showing the structure of the transceiver circuit involved in Embodiment 1.

[0009] Figure 2 This is a timing diagram that provides a general description of the operation of the transceiver circuit involved in Implementation Method 1.

[0010] Figure 3 This is a timing diagram that explains in detail the operation of the transceiver circuit involved in Implementation Method 1.

[0011] Figure 4 This is a timing diagram illustrating the operation of the transceiver circuit involved in Implementation Method 2.

[0012] Figure 5 This is a timing diagram illustrating the operation of the transceiver circuit involved in Implementation Method 3.

[0013] Figure 6 This is a diagram showing the structure of the transceiver circuit involved in the first variation.

[0014] Figure 7 This is a diagram showing the structure of the transceiver circuit involved in the second variation.

[0015] Explanation of reference numerals in the attached figures

[0016] 10 Circuit 1

[0017] 10a Terminal 1

[0018] 11 First Transmitting Circuit

[0019] 11a Output

[0020] 11b Output

[0021] 12 First Receiving Circuit

[0022] 12a Input

[0023] 12b input

[0024] 20 Circuit 2

[0025] 21. Second transmitting circuit

[0026] 21a Output

[0027] 21b Output

[0028] 22 Second Receiving Circuit

[0029] 22a Input

[0030] 22b input

[0031] 30 Insulating elements

[0032] 31 Primary Side

[0033] 32 secondary side

[0034] 40 Signal Processing Circuit

[0035] 41 Clock terminal

[0036] 42 Output terminals

[0037] 43 A / D Converter

[0038] 44 P / S converter

[0039] 100 Transceiver Circuit

[0040] 200 transceiver circuits

[0041] 230A First Insulating Element

[0042] 230B Second Insulating Element

[0043] 300 transceiver circuit

[0044] 330 Insulating Components

[0045] 331 Primary Side

[0046] 332 Secondary side

[0047] CLK1 Clock Signal 1

[0048] CLK2 second clock signal

[0049] CLK3 3rd clock signal

[0050] CLK4, the fourth clock signal

[0051] DATA signal

[0052] DATA1 First data signal

[0053] DATA2 Second data signal

[0054] R1, Area 1

[0055] R2, Region 2 Detailed Implementation

[0056] The embodiments will now be described with reference to the accompanying drawings. In the drawings, the same or corresponding elements are labeled with the same reference numerals, and detailed descriptions are omitted where appropriate.

[0057] (Implementation Method 1)

[0058] Figure 1 This diagram illustrates the structure of the transceiver circuit 100 according to Embodiment 1. The transceiver circuit 100 includes a first circuit 10 capable of transmitting and receiving signals, a second circuit 20 capable of transmitting and receiving signals, an insulating element 30 consisting of a single transformer or converter, and a signal processing circuit 40. The first circuit 10 is disposed in a first region R1, and the second circuit 20 is disposed in a second region R2. The first circuit 10 and the second circuit 20 are connected via the insulating element 30. The first circuit 10 and the second circuit 20 are electrically insulated but magnetically coupled, thus a signal transmitted from one circuit is transmitted to the other circuit via the insulating element 30.

[0059] The first circuit 10 includes a first transmitting circuit 11, a first receiving circuit 12, and a first control circuit 13 that controls the operation of these two circuits. Additionally, the first circuit 10 has a first terminal 10a on which a first clock signal CLK1 is periodically input from outside the transceiver circuit 100. The first transmitting circuit 11 receives the first clock signal CLK1 periodically via the first terminal 10a. As described later, the first clock signal CLK1 is used, for example, in switching the operating mode of the first circuit 10. The outputs 11a and 11b of the first transmitting circuit 11 are connected to the primary side 31 of the insulating element 30. The inputs 12a and 12b of the first receiving circuit 12 are also connected to the primary side 31 of the insulating element 30.

[0060] If the first clock signal CLK1 is input to the first terminal 10a of the first circuit 10, the first circuit 10 will increase the frequency of the first clock signal CLK1 to generate a second clock signal and send it. The insulating element 30 will transmit the second clock signal CLK2 from the first circuit 10 with a slight time delay as the third clock signal CLK3. The second circuit 20 will receive the third clock signal CLK3 from the insulating element 30.

[0061] The first circuit 10 has two operating modes: a first transmitting mode and a first receiving mode. In the first transmitting mode, the first transmitting circuit 11 operates by supplying operating power to the circuit portion within it that transmits signals, resulting in power consumption, while the first receiving circuit 12 operates by not supplying operating power to the circuit portion within it that receives signals, resulting in no power consumption. Conversely, in the first receiving mode, the first transmitting circuit 11 operates by not supplying operating power to the circuit portion within it that transmits signals, resulting in no power consumption, while the first receiving circuit 12 operates by supplying operating power to the circuit portion within it that receives signals, resulting in power consumption. Furthermore, in both the operating and stopped states, the first transmitting circuit 11 and the first receiving circuit 12 continuously supply operating power to the circuit portion that receives control signals from the control circuit 13.

[0062] The second circuit 20 includes a second transmitting circuit 21, a second receiving circuit 22, and a second control circuit 23 that controls the operation of these two circuits. A data signal DATA is input from the signal processing circuit 40 to the second transmitting circuit 21. The third clock signal CLK3 received by the second receiving circuit 22 is down-frequencyd to become a fourth clock signal CLK4, which is input to the clock terminal 41 of the signal processing circuit 40. The aforementioned first clock signal CLK1 is a clock signal input from outside the transceiver circuit 100; in contrast, the second clock signal CLK2 and the third clock signal CLK3 are clock signals used internally by the transceiver circuit 100. The third clock signal CLK3 is used, for example, for the output of the data signal DATA transmitted through the second circuit 20. The outputs 21a and 21b of the second transmitting circuit 21 are connected to the secondary side 32 of the insulating element 30. The inputs 22a and 22b of the second receiving circuit 22 are also connected to the secondary side 32 of the insulating element 30.

[0063] The second circuit 20 has two operating modes: a second transmitting mode and a second receiving mode. In the second transmitting mode, the second transmitting circuit 21 operates by supplying operating power to the circuit portion within it that transmits signals, resulting in power consumption, while the second receiving circuit 22 operates by not supplying operating power to the circuit portion within it that receives signals, resulting in no power consumption. Conversely, in the second receiving mode, the second transmitting circuit 21 operates by not supplying operating power to the circuit portion within it that transmits signals, resulting in no power consumption, while the second receiving circuit 22 operates by supplying operating power to the circuit portion within it that receives signals, resulting in power consumption. Furthermore, in both the operating and stopped states, the second transmitting circuit 21 and the second receiving circuit 22 continuously supply operating power to the circuit portion that receives control signals from the control circuit 23.

[0064] Whenever the fourth clock signal CLK4 is input to the clock terminal 41, the signal processing circuit 40 outputs a 1-bit data signal DATA with a value of 0 or 1 from the output terminal 42. Specifically, the signal processing circuit 40 includes an analog-to-digital (A / D) converter 43 and a parallel-to-serial (P / S) converter 44. The A / D converter 43 converts the externally input analog signal into a multi-bit digital signal for output. The P / S converter 44 converts the multi-bit digital signal, i.e., the parallel bit signal, output from the A / D converter 43 into a serial bit signal for output. Whenever the fourth clock signal CLK4 is input to the clock terminal 41, the serial bit signal output from the P / S converter 44 is output bit by bit from the output terminal 42 as the data signal DATA.

[0065] The type of analog signal input to the signal processing circuit 40 is not particularly limited; for example, it could be a sensor signal output from a current sensor or a voltage sensor. In this case, the transceiver circuit 100 functions as a voltage measuring circuit or a current measuring circuit that transmits the voltage or current value of the measured object from the first circuit 10 to the second circuit 20 via the insulating element 30. Furthermore, the specific structure of the A / D converter 43 is not particularly limited; for example, the A / D converter 43 could be constructed using a ΔΣ modulator.

[0066] The data signal DATA output from the output terminal 42 of the signal processing circuit 40 is frequency-enhanced by the second circuit 20 and transmitted as the first data signal DATA1. The insulating element 30 transmits the first data signal DATA1 from the second circuit 20 with a slight time delay as the second data signal CLK2. The first circuit 10 receives the second data signal DATA2 from the insulating element 30. The first circuit 10 then frequency-enhances the received second data signal DATA2 to restore the original data signal DATA.

[0067] Next, regarding the general outline of the operation of the transceiver circuit 100 according to Embodiment 1, please refer to... Figure 2 The timing diagram is used for illustration. Figure 2 The initial state is shown at the left end of the sequence diagram, where the first circuit 10 is in the first receiving mode and the second circuit 20 is in the second receiving mode.

[0068] At time t1, if the first clock signal CLK1 is input, the first circuit 10 switches from the first receiving mode to the first transmitting mode and transmits the second clock signal CLK2 (S1). Then, at time t5, the first circuit 10 switches from the first transmitting mode to the first receiving mode. The insulating element 30 transmits the second clock signal CLK2 from the first circuit 10 with a slight time delay as the third clock signal CLK3.

[0069] If the second circuit 20 receives the third clock signal CLK3 from the insulating element 30 (S2), it switches from the second receiving mode to the second transmitting mode and transmits the first data signal DATA1 (S3). Then, at time t10, the second circuit 20 switches from the second transmitting mode to the second receiving mode. The insulating element 30 transmits the first data signal DATA1 from the second circuit 20 with a slight time delay as the second data signal DATA2.

[0070] The first circuit 10 receives the second data signal DATA2 (S4) from the insulating element 30. Then, at time t11, if the first clock signal CLK1 is input again, the first circuit 10 switches from the first receive mode to the first transmit mode again. Thereafter, the above operation is repeated each time the first clock signal CLK1 is input.

[0071] about Figure 2 The timing diagrams are shown in detail as the operations of the first transmitting circuit 11 and the first receiving circuit 12 included in the first circuit 10, and the second transmitting circuit 21 and the second receiving circuit 22 included in the second circuit 20, becoming... Figure 3 The following detailed description of the operation of the transceiver circuit 100 according to Embodiment 1 will be provided by referring to... Figure 3 The timing diagram is used for illustration.

[0072] First, in this embodiment 1, the first to fourth clock signals CLK1 to 4, the data signal DATA, and the first to second data signals DATA1 to 2 are all voltage pulses or current pulses. Furthermore, the determination of receiving the first clock signal CLK1 and the third clock signal CLK3 is performed by detecting the rising edge (rising edge) of the pulse.

[0073] exist Figure 3 In the initial state, i.e., at the left end of the sequence diagram, the first circuit 10 is in the first receiving mode. Therefore, the first transmitting circuit 11 is in the stopped state, and the first receiving circuit 12 is in the operating state. Additionally, the second circuit 20 is in the second receiving mode. Therefore, the second transmitting circuit 21 is in the stopped state, and the second receiving circuit 22 is in the operating state.

[0074] At time t1, if the first clock signal CLK1 is input, the first circuit 10 switches from the first receiving mode to the first transmitting mode. Specifically, the first control circuit 13 starts supplying operating power to the signal transmission circuit portion included in the first transmitting circuit 11, thereby setting the first transmitting circuit 11 to an operating state, and stops supplying operating power to the signal receiving circuit portion included in the first receiving circuit 12, thereby setting the first receiving circuit 12 to a stopped state. In this state, the first transmitting circuit 11 transmits the second clock signal CLK2 (S1).

[0075] If the transmission of the second clock signal CLK2 is completed at time t3, then the first circuit 10 switches from the first transmitting mode to the first receiving mode. Specifically, the first control circuit 13 stops supplying operating power to the signal transmission circuit portion within the first transmitting circuit 11, thereby stopping the first transmitting circuit 11, and starts supplying operating power to the signal reception circuit portion within the first receiving circuit 12, thereby activating the first receiving circuit 12. However, a certain amount of time is required during the switching process to allow the residual transmission signal from the first transmitting circuit 11 to decay and disappear. Figure 3 In this context, the "switching" period from time t3 to t5 corresponds to a certain amount of time. The switching time is predetermined as a design value.

[0076] On the other hand, from time t2 to t4, the second receiving circuit 22 of the second circuit 20 receives the third clock signal CLK3 from the insulating element 30 (S2). The received third clock signal CLK3 is down-frequencyd to become the fourth clock signal CLK4, which is input to the clock terminal 41 of the signal processing circuit 40. As a result, a 1-bit data signal DATA with a value of 0 or 1 is output from the output terminal 42 of the signal processing circuit 40, and this data signal DATA is input to the second transmitting circuit 21. Furthermore, the data signal DATA output from the signal processing circuit 40 maintains the same value until the next fourth clock signal CLK4 is input. Additionally, Figure 3 In the diagram, the time difference between time t1 and time t2, and the time difference between time t3 and time t4, represent the delays that occur during the transmission of the second clock signal CLK2 via the insulating element 30.

[0077] If the reception of the third clock signal CLK3 is completed at time t4, then the second receiving circuit 22 will standby for a certain period of time in order to wait for the residual transmission signal of the first transmitting circuit 11 of the first circuit 10 to attenuate and disappear. Figure 3 In this context, the period from time t4 to t6 corresponds to the standby time. The standby time is predetermined as a design value.

[0078] At time t6, the second circuit 20 switches from the second receiving mode to the second transmitting mode. Specifically, the second control circuit 23 starts supplying operating power to the signal transmission circuit portion included in the second transmitting circuit 21, thereby setting the second transmitting circuit 21 to an operating state, and stops supplying operating power to the signal receiving circuit portion included in the second receiving circuit 22, thereby setting the second receiving circuit 22 to a stopped state. In this state, the second transmitting circuit 21 transmits the first data signal DATA1 (S3). This first data signal DATA1 is obtained by increasing the frequency of the data signal DATA output from the output terminal 42 of the signal processing circuit 40 when the fourth clock signal CLK4 is first input to the clock terminal 41 of the signal processing circuit 40.

[0079] If the transmission of the first data signal DATA1 is completed at time t8, then the second circuit 20 switches from the second transmission mode to the second reception mode. Specifically, the second control circuit 23 stops supplying operating power to the signal transmission circuit portion within the second transmission circuit 21, thereby stopping the second transmission circuit 21, and starts supplying operating power to the signal transmission circuit portion within the second transmission circuit 22, thereby activating the second reception circuit 22. Here, a certain amount of time is required during the switching process to allow for the residual transmission signal from the second transmission circuit 21 to attenuate and disappear. Figure 3 In this context, the "switching" period from time t8 to t10 corresponds to this specific time. This switching time is also predetermined as a design value. However, this switching needs to be completed before receiving the next third clock signal CLK3.

[0080] On the other hand, from time t7 to t9, the first receiving circuit 12 of the first circuit 10 receives the second data signal DATA2 from the insulating element 30 (S4). The received second data signal DATA2 is de-frequencyized and restored to the original data signal DATA, then output to the outside of the transceiver circuit 100 for various uses depending on the purpose. For example, the analog signal input to the signal processing circuit 40 is a sensor signal output from a voltage sensor or a current sensor. When the transceiver circuit 100 functions as a voltage measuring circuit or a current measuring circuit, the data signal DATA constitutes part of the digital representation of the voltage or current value of the measured object. After the second data signal DATA2 is received, the first circuit 10 continues in the first receiving mode to wait for the first clock signal CLK1 to be input again.

[0081] At time t11, if the first clock signal CLK1 is input again, the first circuit 10 switches from the first receive mode back to the first transmit mode. Thereafter, this operation is repeated each time the first clock signal CLK1 is input. Thus, each time the first clock signal CLK1 is input, the first circuit 10 can repeatedly receive the high-frequency second data signal DATA corresponding to the 1-bit data signal DATA from the second circuit 20 via the insulating element 30.

[0082] As explained above, in the transceiver circuit 100 according to Embodiment 1, the first circuit 10 has a first terminal 10a into which a first clock signal CLK1 is input. It generates a second clock signal CLK2 by increasing the frequency of the first clock signal CLK1 and transmits it (S1). The insulating element 30 transmits the second clock signal CLK2 from the first circuit 10 as a third clock signal CLK3. The second circuit 20 receives the third clock signal CLK3 from the insulating element 30 (S2) and transmits the first data signal DATA1 according to the third clock signal CLK3 (S3). The insulating element 30 transmits the first data signal DATA1 from the second circuit 20 as a second data signal DATA2. The first circuit 10 receives the second data signal DATA2 from the insulating element 30 (S4).

[0083] Based on the above features, the transceiver circuit 100 of this embodiment 1 can achieve bidirectional transmission through a simple circuit structure.

[0084] Furthermore, the first circuit 10 has two operating modes: a first transmitting mode and a first receiving mode. In the first transmitting mode, only the first transmitting circuit 11 is active, and power is consumed by supplying operating power to the signal transmitting circuit portion included in the first transmitting circuit 11. However, the first receiving circuit 12 is in a stopped state, and no operating power is supplied to the signal receiving circuit portion included in the first receiving circuit 12, thus no power consumption occurs. On the other hand, in the first receiving mode, the first receiving circuit 12 is active, and power is consumed by supplying operating power to the signal receiving circuit portion included in the first receiving circuit 12. However, the first transmitting circuit 11 is in a stopped state, and no operating power is supplied to the signal transmitting circuit portion included in the first transmitting circuit 11, thus no power consumption occurs.

[0085] Similarly, the second circuit 20 has two operating modes: a second transmitting mode and a second receiving mode. In the second transmitting mode, only the second transmitting circuit 21 is active, and power is consumed by supplying operating power to the circuit portion within the second transmitting circuit 21 that handles signal transmission. However, the second receiving circuit 22 is in a stopped state, and no operating power is supplied to the circuit portion within the second receiving circuit 22 that handles signal reception, thus no power consumption occurs. On the other hand, in the second receiving mode, only the second receiving circuit 22 is active, and power is consumed by supplying operating power to the circuit portion within the second receiving circuit 22 that handles signal reception. However, the second transmitting circuit 21 is in a stopped state, and no operating power is supplied to the circuit portion within the second transmitting circuit 21 that handles signal transmission, thus no power consumption occurs.

[0086] Based on the above features, bidirectional transmission between the first circuit 10 and the second circuit 20 can be achieved using a single insulating element 30, specifically the transmission of the second clock signal CLK2 and the first data signal DATA1. Therefore, compared to existing transceiver circuits using two insulating elements, the number of components can be reduced. Furthermore, the first receiving circuit 12 is in a stopped state when the first transmitting circuit 11 is operating, and the first transmitting circuit 11 is in a stopped state when the first receiving circuit 12 is operating; therefore, the first circuit 10 consumes low power. Similarly, the second receiving circuit 22 is in a stopped state when the second transmitting circuit 21 is operating, and the second transmitting circuit 21 is in a stopped state when the second receiving circuit 22 is operating; therefore, the second circuit 20 also consumes low power.

[0087] In addition, in the first transmission mode, the first circuit 10, after a predetermined switching time elapsed since the transmission of the second clock signal CLK2 is completed ( Figure 3 After the time interval t3 to t5, the circuit switches to the first receiving mode. Similarly, in the second receiving mode, the second circuit 20, after a predetermined standby time elapsed since the reception of the third clock signal CLK3 is completed ( Figure 3 After the time interval t4 to t6, the system switches to the second transmission mode. Based on this feature, the first data signal DATA1 can be transmitted without being affected by the residual transmission signal of the first transmission circuit 11.

[0088] (Implementation Method 2)

[0089] In Embodiment 1 described above, the first circuit 10 has two operating modes: a first transmitting mode and a first receiving mode. In contrast, the first circuit 10 in Embodiment 2, in addition to the first transmitting mode and the first receiving mode, also has a first standby mode. In the first standby mode, both the first transmitting circuit 11 and the first receiving circuit 12 are in a stopped state.

[0090] exist Figure 4 The initial state is shown at the left end of the sequence diagram, where the first circuit 10 is in the first standby mode. Therefore, both the first transmitting circuit 11 and the first receiving circuit 12 are in a stopped state.

[0091] At time t1, if the first clock signal CLK1 is input, the first circuit 10 switches from the first standby mode to the first transmit mode. Specifically, the first control circuit 13 sets the first transmit circuit 11 to the active state, while keeping the first receive circuit 12 in the stopped state. Thereafter, the operation until time t9 is the same as in Embodiment 1.

[0092] If the reception of the second data signal DATA2 is completed at time t9, then the first circuit 10 switches from the first receiving mode to the first standby mode. Specifically, the first control circuit 13 sets both the first transmitting circuit 11 and the first receiving circuit 12 to a stopped state.

[0093] At time t11, if the first clock signal CLK1 is input again, the first circuit 10 will switch from the first standby mode to the first transmit mode again. Thereafter, the above action will be repeated every time the first clock signal CLK1 is input.

[0094] As explained above, in the transceiver circuit 100 according to Embodiment 2, the first circuit 10, in addition to the first transmitting mode and the first receiving mode, also has a first standby mode. In the first standby mode, both the first transmitting circuit 11 and the first receiving circuit 12 are in a stopped state.

[0095] In the above-described implementation method 1, in Figure 3 In this embodiment, the period from the initial state at the left end to time t1 and the period from time t9 to t11 constitute the first receiving mode. Therefore, although the first transmitting circuit 11 is stopped, the first receiving circuit is in an active state, and power is consumed by the first receiving circuit 12. In contrast, in this embodiment 2, in Figure 4 In this embodiment, the period from the initial state at the left end to time t1 and the period from time t9 to t11 constitute the first standby mode. Therefore, both the first transmitting circuit 11 and the first receiving circuit 12 are stopped, and the power consumption of the first circuit 10 is further reduced compared to Embodiment 1. As a result, the transceiver circuit 100 involved in this Embodiment 2 consumes less power than that in Embodiment 1.

[0096] (Implementation Method 3)

[0097] In the aforementioned Embodiment 1, if the second circuit 20 completes the transmission of the first data signal DATA1 at time t8, it switches from the second transmission mode to the second reception mode. However, if an error occurs and the mode switching fails, the second circuit 20 remains fixed in the second transmission mode. In this case, the next third clock CLK3 cannot be received, and as a result, the transmission of the first data signal DATA1 from the second circuit 20 to the first circuit 10 stops. As a safety measure against such a phenomenon, in the transceiver circuit 100 of this Embodiment 3, if the second transmission mode continues for a predetermined time, the second circuit 20 switches to the second reception mode. Specifically, if the second control circuit 23 detects that a predetermined timeout period has elapsed through the built-in timer circuit, it sets the second transmission circuit 21 to a stop state and sets the second reception circuit 22 to an operating state.

[0098] exist Figure 5 In the example, the second control circuit 23 switches to the second transmission mode at time t6, triggering the built-in timer. If the built-in timer detects that a predetermined timeout period ΔT has elapsed, then at time t30, the second transmission circuit 21 is set to a stop state, and the second receiving circuit 22 is set to an active state. Here, the predetermined timeout period ΔT is predetermined as a value obtained by adding a desired margin to the time typically required to transmit the first data signal DATA1.

[0099] As explained above, in the transceiver circuit 100 according to Embodiment 3, if the second transmission mode continues for a predetermined time, the second circuit 20 switches to the second reception mode. This prevents the second circuit 20 from being fixed in the second transmission mode. Figure 5 In the example, the second circuit 20 is unable to respond to the second and third clock signals CLK3 received from the first circuit 10 and send back the first data signal DATA1, but from the fourth clock signal CLK3 onwards, it returns to the state where it can send back the first data signal DATA1 as usual.

[0100] (Modified Example)

[0101] In embodiments 1 to 3 described above, a structure for bidirectional transmission using a single insulating element 30 is shown; however, it is not impossible to use multiple insulating elements. As an example, such as... Figure 6As shown, instead of a single insulating element 30, a first insulating element 230A and a second insulating element 230B can be provided. The second clock signal CLK2 is transmitted via the first insulating element 230A, and the first data signal DATA1 is transmitted via the second insulating element 230B. Therefore, it can operate in two paths: one between the first transmitting circuit 11 and the second receiving circuit 22, and the other between the second transmitting circuit 21 and the first receiving circuit 12. Furthermore, the single insulating element 30 can also replace... Figure 1 Instead of the magnetically coupled transformer or converter shown, it uses... Figure 7 The capacitor shown is coupled by an electric field.

[0102] Furthermore, in the embodiments 1 to 3 described above, the determination of receiving the first clock signal CLK1 and the third clock signal CLK3 is performed by detecting the rising edge of a voltage pulse or a current pulse. Alternatively, the determination of receiving each clock signal can be performed by detecting both the falling edge (falling edge) and the rising edge and falling edge of the voltage pulse or current pulse.

[0103] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, modifications, and combinations can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and likewise within the scope of the invention as described in the claims and its equivalents.

[0104] Furthermore, the above-described embodiments can be summarized into the following technical solution.

[0105] Technical Solution 1

[0106] A transceiver circuit, wherein:

[0107] The first circuit capable of transmitting and receiving signals;

[0108] A second circuit capable of transmitting and receiving signals; and

[0109] An insulating element electrically insulates the first circuit and the second circuit, and is capable of transmitting a signal emitted from either the first circuit or the second circuit to the other.

[0110] The first circuit has a first terminal that receives a first clock signal, generates a second clock signal by increasing the frequency of the first clock signal, and transmits the second clock signal.

[0111] The insulating element transmits the second clock signal from the first circuit as the third clock signal to the second circuit.

[0112] The second circuit transmits the first data signal according to the third clock signal from the insulating element.

[0113] The insulating element transmits the first data signal from the second circuit as the second data signal.

[0114] The first circuit receives the second data signal from the insulating element.

[0115] Technical Solution 2

[0116] According to the above technical solution 1,

[0117] The first circuit has a first transmitting mode and a first receiving mode.

[0118] When the first clock signal is input, the first circuit switches to the first transmitting mode to transmit the second clock signal; when the transmission of the second clock signal is completed, it switches to the first receiving mode.

[0119] In the first receiving mode, the first circuit receives the second data signal from the insulating element.

[0120] Technical Solution 3

[0121] According to the above technical solution 2,

[0122] The first circuit includes a first transmitting circuit and a first receiving circuit.

[0123] In the first transmission mode, the first transmission circuit is in an operational state where it supplies operating power to the circuit portion within it that is responsible for transmitting signals, and the first receiving circuit is in a stopped state where it does not supply operating power to the circuit portion within it that is responsible for receiving signals.

[0124] In the first receiving mode, the first transmitting circuit is in a stopped state, and the first receiving circuit is in an active state.

[0125] Technical Solution 4

[0126] According to the above technical solution 3,

[0127] The first circuit switches to the first receiving mode after a predetermined switching time has elapsed since the transmission of the second clock signal is completed.

[0128] Technical Solution 5

[0129] According to the above technical solution 3 or 4

[0130] In the first receiving mode, upon receiving the second data signal from the insulating element, the first circuit switches to a first standby mode.

[0131] In the first standby mode, both the first transmitting circuit and the first receiving circuit are in a stopped state.

[0132] Technical Solution 6

[0133] According to the above technical solutions 1 to 5,

[0134] The second circuit has a second transmitting mode and a second receiving mode.

[0135] In the second receiving mode, upon receiving the third clock signal from the insulating element, the second circuit switches to the second transmitting mode.

[0136] The second circuit transmits the first data signal in the second transmission mode, and switches to the second reception mode when the transmission of the first data signal is completed.

[0137] Technical Solution 7

[0138] According to the above technical solution 6,

[0139] The second circuit includes a second transmitting circuit and a second receiving circuit.

[0140] In the second transmission mode, the second transmission circuit is in an operational state where it supplies operating power to the circuit portion within it that transmits signals, and the second receiving circuit is in a stopped state where it does not supply operating power to the circuit portion within it that receives signals.

[0141] In the second receiving mode, the second transmitting circuit is in a stopped state, and the second receiving circuit is in an active state.

[0142] Technical Solution 8

[0143] According to the above technical solution 7,

[0144] After a predetermined standby time has elapsed since the reception of the third clock signal is completed, the second circuit switches to the second transmission mode.

[0145] Technical Solution 9

[0146] According to the above technical solutions 6-8,

[0147] The second circuit switches to the second receiving mode when the second transmitting mode continues for a specified time.

[0148] Technical Solution 10

[0149] According to the above technical solution 9,

[0150] The second circuit also includes a timer circuit that counts time based on the switching to the second transmission mode, and switches to the second reception mode when the timer circuit detects that the predetermined time has elapsed.

[0151] Technical Solution 11

[0152] According to the above technical solutions 1 to 10,

[0153] The insulating element is a single insulating element, and both the second clock signal and the first data signal are transmitted through the single insulating element.

[0154] Technical Solution 12

[0155] According to the above technical solutions 1 to 10,

[0156] The insulating element includes a first insulating element and a second insulating element.

[0157] The second clock signal is transmitted through the first insulating element, and the first data signal is transmitted through the second insulating element.

[0158] Technical Solution 13

[0159] According to the above technical solutions 1 to 12,

[0160] The insulating element is composed of a transformer, converter, or capacitor.

[0161] Technical Solution 14

[0162] According to the above technical solutions 1 to 13,

[0163] The second clock signal, the third clock signal, the first data signal, and the second data signal are voltage pulses or current pulses.

[0164] Technical Solution 15

[0165] According to the above technical solutions 1 to 14,

[0166] The first circuit determines the reception of the first clock signal by detecting the rising edge, falling edge, or both rising and falling edges of the first clock signal.

[0167] The second circuit determines the reception of the third clock signal by detecting the rising edge, falling edge, or both rising and falling edges of the third clock signal.

[0168] Technical Solution 16

[0169] According to the above technical solutions 1 to 15,

[0170] It also includes a signal processing circuit that supplies data signals to the second circuit.

[0171] The second circuit reduces the frequency of the third clock signal to generate a fourth clock signal, and then inputs the fourth clock signal to the signal processing circuit.

[0172] The signal processing circuit supplies the data signal synchronously with the fourth clock signal input from the second circuit.

[0173] The second circuit generates the first data signal by increasing the frequency of the data signal supplied from the signal processing circuit.

[0174] Technical Solution 17

[0175] According to the above technical solution 16,

[0176] The signal processing circuit includes an A / D converter.

[0177] Technical Solution 18

[0178] According to the above technical solution 17,

[0179] The A / D converter is composed of a ΔΣ modulator.

Claims

1. A transceiver circuit, wherein, have: The first circuit capable of transmitting and receiving signals; A second circuit capable of transmitting and receiving signals; as well as An insulating element electrically insulates the first circuit and the second circuit, and is capable of transmitting a signal emitted from either the first circuit or the second circuit to the other. The first circuit has a first terminal that receives an externally input first clock signal that repeatedly alternates between a first level and a second level at a certain period. The first clock signal is then frequency-enhanced to generate a second clock signal, which is then transmitted. The insulating element transmits the second clock signal from the first circuit as the third clock signal to the second circuit. The second circuit transmits the first data signal according to the third clock signal from the insulating element. The insulating element transmits the first data signal from the second circuit as the second data signal. The first circuit receives the second data signal from the insulating element. The first circuit has a first transmitting mode and a first receiving mode. When the first clock signal input from the outside becomes the first level, the first circuit switches to the first transmission mode and transmits the second clock signal. When the transmission of the second clock signal is completed, before the level of the first clock signal changes to the second level, the first circuit switches to the first reception mode and receives the second data signal from the insulating element.

2. The transceiver circuit as described in claim 1, wherein, The first circuit includes a first transmitting circuit and a first receiving circuit. In the first transmission mode, the first transmission circuit is in an operational state where it supplies operating power to the circuit portion within it that is responsible for transmitting signals, and the first receiving circuit is in a stopped state where it does not supply operating power to the circuit portion within it that is responsible for receiving signals. In the first receiving mode, the first transmitting circuit is in a stopped state, and the first receiving circuit is in an active state.

3. The transceiver circuit as described in claim 2, wherein, The first circuit switches to the first receiving mode after a predetermined switching time has elapsed since the transmission of the second clock signal is completed.

4. The transceiver circuit as described in claim 2 or 3, wherein, In the first receiving mode, upon receiving the second data signal from the insulating element, the first circuit switches to a first standby mode. In the first standby mode, both the first transmitting circuit and the first receiving circuit are in a stopped state.

5. The transceiver circuit as described in any one of claims 1 to 3, wherein, The second circuit has a second transmitting mode and a second receiving mode. In the second receiving mode, upon receiving the third clock signal from the insulating element, the second circuit switches to the second transmitting mode. The second circuit transmits the first data signal in the second transmission mode, and switches to the second reception mode when the transmission of the first data signal is completed.

6. The transceiver circuit as described in claim 5, wherein, The second circuit includes a second transmitting circuit and a second receiving circuit. In the second transmission mode, the second transmission circuit is in an operational state where it supplies operating power to the circuit portion within it that transmits signals, and the second receiving circuit is in a stopped state where it does not supply operating power to the circuit portion within it that receives signals. In the second receiving mode, the second transmitting circuit is in a stopped state, and the second receiving circuit is in an active state.

7. The transceiver circuit as described in claim 6, wherein, After a predetermined standby time has elapsed since the reception of the third clock signal is completed, the second circuit switches to the second transmission mode.

8. The transceiver circuit as described in claim 5, wherein, The second circuit switches to the second receiving mode when the second transmitting mode continues for a specified time.

9. The transceiver circuit as described in claim 8, wherein, The second circuit also includes a timer circuit that counts time based on the switching to the second transmission mode, and switches to the second reception mode when the timer circuit detects that the predetermined time has elapsed.

10. The transceiver circuit as described in any one of claims 1 to 3, wherein, The insulating element is a single insulating element, and both the second clock signal and the first data signal are transmitted through the single insulating element.

11. The transceiver circuit as described in any one of claims 1 to 3, wherein, The insulating element includes a first insulating element and a second insulating element. The second clock signal is transmitted through the first insulating element, and the first data signal is transmitted through the second insulating element.

12. The transceiver circuit as described in any one of claims 1 to 3, wherein, The insulating element is composed of a transformer, converter, or capacitor.

13. The transceiver circuit as described in any one of claims 1 to 3, wherein, The second clock signal, the third clock signal, the first data signal, and the second data signal are voltage pulses or current pulses.

14. The transceiver circuit as described in any one of claims 1 to 3, wherein, The first circuit detects the rising edge, falling edge, or both rising and falling edges of the first clock signal to determine whether the first clock signal has been received. The second circuit detects the rising edge, falling edge, or both rising and falling edges of the third clock signal to determine whether the third clock signal has been received.

15. The transceiver circuit as described in any one of claims 1 to 3, wherein, It also includes a signal processing circuit that supplies data signals to the second circuit. The second circuit reduces the frequency of the third clock signal to generate a fourth clock signal, and then inputs the fourth clock signal to the signal processing circuit. The signal processing circuit supplies the data signal bit by bit whenever the fourth clock signal is input from the second circuit. The second circuit generates the first data signal by increasing the frequency of the data signal supplied from the signal processing circuit.

16. The transceiver circuit as described in claim 15, wherein, The signal processing circuit includes an A / D converter.

17. The transceiver circuit as claimed in claim 16, wherein, The A / D converter is composed of a ΔΣ modulator.

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