Configurable fixed-point pooling engine hardware optimization method and system

Abstract

The application provides a configurable fixed-point pooling engine hardware optimization method and system, comprising: reading data from a higher-level unit or an external storage unit through a data bus read control unit; parallelly buffering data of three channels in a line buffer unit; determining a used pooling method through a pooling mode selection unit; sending the data to a pooling calculation unit; and writing the data processed through the pooling to a lower-level unit or the external storage unit through a data bus write control unit. The application quantizes a parameter scaling factor through a register, and increases a quantization parameter reset function. The application designs multiple paths, supports rounding, floor and positive rounding multiple rounding modes, makes the module more flexible, and meets different requirements. The application optimizes an algorithm, reduces the bit width of a dividend and the bit width of a divisor under the condition of ensuring consistent calculation results, and greatly reduces the hardware overhead of a fixed-point divider.

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