Wideband analog adaptive cancellation circuit based on loop iteration of digital accumulation

Abstract

The application belongs to the technical field of wireless communication, and specifically provides a wideband analog adaptive cancellation circuit based on digital accumulation loop iteration, which is used to solve the problem of reduced iteration depth and decreased cancellation ratio of the existing analog adaptive cancellation circuit due to the incomplete digital integral function. The application comprises an analog adaptive cancellation module and a digital enhancement module, taking the analog adaptive interference cancellation module as the main body, using the digital enhancement module (digital circuit) to process the direct current component, and realizing the accumulation function when updating the weight, i.e. completely realizing the digital integral function, which significantly increases the iteration depth of the system and improves the cancellation ratio of the system. Meanwhile, the algorithm of the digital enhancement module can be adjusted to determine the convergence condition of the system, and the convergence time is reduced under the condition of meeting the demand cancellation ratio. Furthermore, the analog phase shifter is used to change the optimal cancellation frequency of the system, increase the working bandwidth of the system, and relax the convergence condition of the system.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, specifically providing a broadband analog adaptive cancellation circuit based on digital accumulation to form a loop iteration. Background Technology

[0002] Anti-interference is an indispensable and important component of wireless communication systems. Compared with traditional anti-interference methods in wireless communication systems, adaptive cancellation technology has advantages such as strong robustness, not overly relying on prior knowledge, and being able to handle co-channel interference.

[0003] Adaptive noise cancellation technology is mainly based on the LMS algorithm. Specifically, in 1975, Widrow proposed the Least Mean Square Error (LMS) algorithm in the paper "B. Widrow, J.R.G. Lover Jr., J.M.M.C. Cool., J. Kaunitz, C.S. Williams, R.H. Hearn, J.R. Zeidler, E. Dong Jr., and R.C. Goodlin, "Adaptive noise cancelling: Principles and applications," Proceedings of the IEEE, vol. 63, no. 12, pp. 1692–1716, 1975." and designed an adaptive cancellation circuit based on digital technology, such as... Figure 1 As shown, this circuit is mainly used to handle known interference, and also has the potential to handle unknown interference.

[0004] With the continuous advancement of communication technology, analog adaptive interference cancellation technology has been proposed. In 2015, Rezazadeh Reyhani et al. proposed an adaptive cancellation circuit based on fully analog technology in the paper "A. Rezazadeh Reyhani, C. Jayanthmurthy, B. Gillman, J. Walling, J. Belz and B. Farhang-Boroujeny, An analog adaptive notch filter based on the noise cancellation principle, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015, pp. 2660-2663." For example... Figure 2As shown, when implementing the adaptive cancellation algorithm, the original digital module is simplified, and an integrator or low-pass filter is used to implement the integration function during weight update. However, the analog integrator in the adaptive cancellation circuit cannot fully realize the digital integration function, which leads to a reduction in the circuit iteration depth and a decrease in the cancellation ratio. Summary of the Invention

[0005] The purpose of this invention is to address the problems of reduced circuit iteration depth and decreased cancellation ratio caused by the inability of existing analog adaptive cancellation circuits to fully realize digital integration. This invention provides a broadband analog adaptive cancellation circuit based on digital accumulation to form a loop iteration. The invention designs a digital enhancement module that uses digital circuits to process the DC component in the analog circuit, implementing accumulation during weight updates. This effectively increases the iteration depth of the analog adaptive interference cancellation circuit, thereby improving the cancellation ratio. Simultaneously, an analog phase shifter and AGC are added to the analog adaptive cancellation module to enable it to handle high-power blind strong interference (interference power greater than signal power and unknown frequency).

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration is characterized by comprising: an analog adaptive cancellation module and a digital enhancement module; wherein,

[0008] The analog adaptive cancellation module includes: a first LMS adaptive module, a second LMS adaptive module, an orthogonal power divider, a first power divider, a second power divider, a first combiner, a second combiner, a first automatic gain control module (AGC), a second automatic gain control module (AGC), a bandpass filter (BPF), and an analog phase shifter; the digital enhancement module includes: a microcontroller, a first addition circuit, a second addition circuit, a third subtraction circuit, and a fourth subtraction circuit;

[0009] The reference input signal Sr is split into two orthogonal signals Si and Sq by an orthogonal power divider. Signals Si and Sq are then combined into signal S by a first combiner after passing through the first and second LMS adaptive modules, respectively. Signal S then passes through a bandpass filter, a first AGC, and an analog phase shifter before being combined with the original input signal Sp by a second combiner to form signal S'. Signal S' passes through the second AGC and enters the first power divider, where it is split into signals Se and So. Signal So serves as the error output signal. Signal Se enters the second power divider and is split into signals Se1 and Se2, which then enter the first and second LMS adaptive modules, respectively.

[0010] Furthermore, the LMS adaptive module includes: a low-pass filter (LPF), a first multiplier, a second multiplier, a first subtraction circuit, a second subtraction circuit, an inverting amplifier circuit, and a third power divider. The signal Si or Sq enters the third power divider and is divided into signals Sa and Sb. Signal Sa and signal Se1 or Se2 enter the first multiplier. The differential output of the first multiplier is converted into a single-ended signal Sc by the first subtraction circuit, and then passes through the second subtraction circuit and the inverting amplifier circuit to obtain signal Swi or Swq. Signal Swi or Swq enters the digital enhancement module. The output signal Sdi or Sdq of the digital enhancement module passes through the low-pass filter (LPF) and then enters the second multiplier with signal Sb. The output signal of the second multiplier is sent to the first combiner.

[0011] Furthermore, in the digital enhancement module, signals Swi and Swq are fed into the microcontroller after passing through an addition circuit. The two signals are accumulated independently and output from the microcontroller. After passing through a subtraction circuit, signals Sdi and Sdq are output.

[0012] Furthermore, before the circuit operates, it is powered on and zeroed. The input voltage of the second subtraction circuit in the LMS adaptive module is adjusted so that the output of the inverting amplifier circuit is 0mV; the input voltage of the addition circuit in the digital enhancement module is adjusted so that its output is V. AD / 2,V AD This is the maximum AD sampling voltage of the microcontroller; adjust the input voltage of the subtraction circuit in the digital enhancement module so that its output is -V. AD / 2; Adjust the input voltage of the analog phase shifter in the analog adaptive cancellation module so that the cancellation center of the system is located within the signal operating frequency.

[0013] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0014] This invention provides a broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration, comprising an analog adaptive cancellation module and a digital enhancement module. The analog adaptive interference cancellation module is the main component, while the digital enhancement module (digital circuit) processes the DC component. Accumulation is implemented during weight updates, thus fully realizing digital integration, significantly increasing the system's iteration depth and improving the cancellation ratio. Simultaneously, the system convergence conditions can be determined by adjusting the algorithm of the digital enhancement module, reducing convergence time while meeting the required cancellation ratio. Furthermore, an analog phase shifter is used to change the optimal cancellation frequency, increasing the system's operating bandwidth and relaxing the convergence conditions. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of an existing all-digital adaptive cancellation circuit.

[0016] Figure 2This is the schematic diagram of an existing fully analog adaptive cancellation circuit.

[0017] Figure 3 This is a schematic diagram of the broadband analog adaptive cancellation circuit based on digital accumulation to form a loop iteration in this invention.

[0018] Figure 4 This is a schematic diagram of the digital enhancement module of the broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration in this invention.

[0019] Figure 5 This is a schematic diagram of the LMS module of the broadband analog adaptive cancellation circuit based on digital accumulation to form a loop iteration in this invention.

[0020] Figure 6 The image shows the signal (Sr / Sp) before cancellation in the MATLAB simulation of the broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration in this invention.

[0021] Figure 7 The image shows the signal (Se) after cancellation in MATLAB simulation of the broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration in this invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0023] This embodiment provides a broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration, the schematic diagram of which is shown below. Figure 3 As shown, it specifically includes: an analog adaptive cancellation module and a digital enhancement module; wherein,

[0024] The analog adaptive cancellation module includes: a first LMS adaptive module, a second LMS adaptive module, an orthogonal power divider, a first power divider, a second power divider, a first combiner, a second combiner, a first automatic gain control module (AGC), a second automatic gain control module (AGC), a bandpass filter (BPF), and an analog phase shifter; the digital enhancement module includes: a microcontroller, a first addition circuit, a second addition circuit, a third subtraction circuit, and a fourth subtraction circuit.

[0025] Furthermore, the reference input signal Sr is divided into two orthogonal signals Si and Sq by an orthogonal power divider. Signals Si and Sq are then combined into signal S by a first combiner after passing through the first and second LMS adaptive modules, respectively. Signal S then passes through a bandpass filter, a first AGC, and an analog phase shifter, and is combined with the original input signal Sp by a second combiner to form signal S'. Signal S' passes through the second AGC and enters the first power divider, where it is divided into signals Se and So. Signal So serves as the error output signal. Signal Se enters the second power divider and is divided into signals Se1 and Se2, which then enter the first and second LMS adaptive modules, respectively.

[0026] The LMS adaptive module, as follows Figure 5 As shown, the system includes: a low-pass filter (LPF), a first multiplier, a second multiplier, a first subtraction circuit, a second subtraction circuit, an inverting amplifier circuit, and a third power divider. Taking the first LMS adaptive module as an example, the first signal Si enters the third power divider and is divided into signals Sai and Sbi. Signals Sai and Se1 enter the first multiplier. The differential output of the first multiplier is converted into a single-ended signal Sci by the first subtraction circuit, and then passes through the second subtraction circuit and the inverting amplifier circuit to obtain signal Swi. Signal Swi enters the digital enhancement module. The output signal Sdi of the digital enhancement module passes through the low-pass filter (LPF) and is then... Signal Sbi enters the second multiplier, and the output signal of the second multiplier goes to the first combiner. Similarly, taking the second LMS adaptive module as an example, the first signal Sq enters the third power divider and is divided into signals Saq and Sbq. Signals Saq and Se1 enter the first multiplier. The differential output of the first multiplier is converted into a single-ended signal Scq by the first subtraction circuit, and then passes through the second subtraction circuit and the inverting amplifier circuit to obtain signal Swq. Signal Swq enters the digital enhancement module. The output signal Sdq of the digital enhancement module passes through a low-pass filter (LPF) and then enters the second multiplier with signal Sbq. The output signal of the second multiplier goes to the first combiner.

[0027] The digital enhancement module includes a microcontroller, a first addition circuit, a second addition circuit, a third subtraction circuit, and a fourth subtraction circuit. Signals Swi and Swq enter the microcontroller after passing through the addition circuits. The two signals are independently accumulated and output from the microcontroller, and then output after passing through the subtraction circuits.

[0028] Additionally, it should be noted that the analog multipliers in the LMS adaptive module can be selected to use single-ended input, differential input, single-ended output, and differential output. The first multiplier uses single-ended input and differential output, while the second multiplier uses single-ended input and single-ended output. The reference input signal Sr and the original input signal Sp are the same signal before and after differential processing; Sp is the signal before differential processing, and Sr is the signal after differential processing. The analog phase shifter controls the input voltage via a potentiometer to generate a 0°-180° phase change, ensuring the system's cancellation frequency center is located in the interference band. The microcontroller's algorithm can be implemented through direct accumulation, or with equal or variable step increments. Direct accumulation is simpler, equal step increments offer deeper iteration depth, and variable step increments have shorter convergence time. The microcontroller has two AD converters and two DA converters, enabling parallel processing of two signals. The algorithm simultaneously performs AD sampling, accumulation, and DA output on both signals. The AD converter acquires the DC component, and the DA converter generates the DC component. The microcontroller's operating speed and the algorithm's time complexity determine the system's convergence time. The AGC gain depends on the physical characteristics of the circuit and each module. The first AGC module ensures the system meets the convergence condition, while the gain provided by the second AGC module is related to the system's cancellation ratio.

[0029] Based on the above broadband analog adaptive cancellation circuit that forms a loop through digital accumulation, the specific process of cancellation is as follows:

[0030] 1) Input signal acquisition (differentiation processing):

[0031] Two antennas, spaced further apart than the coherence distance, are used to receive the signal; one is denoted as the reference input signal S. r The other is denoted as the original input signal S. p ;

[0032] 2) Zeroing before use:

[0033] Before activating the circuit, power it on and zero it. Adjust the input voltage of the second subtraction circuit in the LMS module so that the output of the inverting amplifier circuit in the LMS module is 0mV; adjust the input voltage of the addition circuit in the digital enhancement module so that its output is V. AD / 2,V AD This is the maximum AD sampling voltage of the microcontroller; adjust the input voltage of the subtraction circuit in the digital enhancement module so that its output is -V. AD / 2; Adjust the input voltage of the analog phase shifter in the analog adaptive cancellation module so that the system cancellation center is located within the signal operating frequency;

[0034] 3) Calculate the initial weights:

[0035] Reference input signal S r After being divided into two orthogonal paths by an orthogonal power divider, denoted as S, the power divider outputs the power into two orthogonal paths.i With S q Initial weight W i With W q Represented as:

[0036] W i =∫S i ×S p

[0037] W q =∫S q ×S p

[0038] 4) Generate a synthesized signal:

[0039] The synthesized signal S is represented as:

[0040] S I ×S I +W Q ×S Q

[0041] 5) Generate error signal:

[0042] Error signal S e Represented as:

[0043] S e =S p -α×S

[0044] Where α is the open-loop gain, which mainly depends on the circuit's AGC, the gain of the inverting amplifier circuit, and the energy loss of the multiplier.

[0045] 6) Weight update (accumulation process):

[0046] The error signal is split into two orthogonal paths, denoted as S, by a power divider. E1 S E2 Then the weight W in the (N+1)th iteration i,n+1 W q,n+1 Represented as:

[0047] W i,n+1 1W i,n +∫S e1 ×S p

[0048] W q,n+1 =W q,n +∫S e2 ×S p

[0049] Therefore, this invention, through the design of an analog adaptive cancellation module and a digital enhancement module, obtains a broadband analog adaptive cancellation circuit based on digital accumulation to form a loop iteration, which can perfectly implement the LMS algorithm. Compared with the all-digital adaptive cancellation circuit, the digital enhancement module in this invention only needs to process DC signals, which greatly reduces the complexity of the digital circuit. Compared with the all-analog adaptive cancellation circuit, this invention can solve the problems of reduced circuit iteration depth and decreased cancellation ratio caused by its inability to fully realize digital integration function.

[0050] The broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration in this embodiment was simulated and tested in MATLAB. The interference frequency was 100Hz, the power was -10dBm, the center frequency was 100Hz, the signal bandwidth was 100Hz, the power was -30dBm, and the system open-loop gain was 25dB. The signals Sr / Sp before cancellation and Se after cancellation were as follows: Figure 6 , Figure 7 As shown in the figure, the cancellation ratio of the adaptive cancellation circuit in this invention is 65dB.

[0051] In summary, this invention proposes a broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration, which uses digital circuits to achieve the accumulation function to a minimum, improves the iteration depth of the system, and thus improves the cancellation ratio; furthermore, this invention can also be applied to cancel strong blind interference in the same frequency (interference power is greater than signal power).

[0052] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration, characterized in that, include: Analog adaptive cancellation module and digital enhancement module; among them, The analog adaptive cancellation module includes: a first LMS adaptive module, a second LMS adaptive module, an orthogonal power divider, a first power divider, a second power divider, a first combiner, a second combiner, a first automatic gain control module (AGC), a second automatic gain control module (AGC), a bandpass filter (BPF), and an analog phase shifter; the digital enhancement module includes: a microcontroller, a first addition circuit, a second addition circuit, a third subtraction circuit, and a fourth subtraction circuit; The reference input signal Sr is divided into two orthogonal signals Si and Sq by an orthogonal power divider. Signals Si and Sq are combined into signal S by a first combiner after passing through the first and second LMS adaptive modules, respectively. Signal S passes through a bandpass filter, a first AGC, and an analog phase shifter in sequence, and is then combined with the original input signal Sp by a second combiner to form signal S'. Signal S' passes through the second AGC and enters the first power divider, where it is divided into signals Se and So. Signal So serves as the error output signal. Signal Se enters the second power divider and is divided into signals Se1 and Se2, which then enter the first and second LMS adaptive modules, respectively. The first LMS adaptive module and the second LMS adaptive module adopt the same structure, including: a low-pass filter (LPF), a first multiplier, a second multiplier, a first subtraction operation circuit, a second subtraction operation circuit, an inverting amplifier circuit, and a third power divider. The signal Si or Sq enters the third power divider and is divided into signals Sa and Sb. The signal Sa and the signal Se1 or Se2 enter the first multiplier. The differential output of the first multiplier is converted into a single-ended signal Sc by the first subtraction operation circuit, and then passes through the second subtraction operation circuit and the inverting amplifier circuit to obtain the signal Swi or Swq. The signal Swi or Swq enters the digital enhancement module. The output signal Sdi or Sdq of the digital enhancement module passes through the low-pass filter and enters the second multiplier with the signal Sb. The output signal of the second multiplier is sent to the first combiner. In the digital enhancement module, signals Swi and Swq enter the microcontroller after passing through the first and second addition circuits, respectively. The two signals are accumulated independently and output from the microcontroller. After passing through the third and fourth subtraction circuits, signals Sdi and Sdq are output.

2. The broadband analog adaptive cancellation circuit based on digital accumulation forming loop iteration as described in claim 1, characterized in that, Before activating the circuit, power it on and zero it. Adjust the input voltage of the second subtraction circuit in the two LMS adaptive modules so that the output of the inverting amplifier circuit is 0mV; adjust the input voltage of the two addition circuits in the digital enhancement module so that their outputs are V. AD / 2,V AD This is the maximum AD sampling voltage of the microcontroller; adjust the input voltage of the two subtraction circuits in the digital enhancement module so that their output is -V. AD / 2; Adjust the input voltage of the analog phase shifter in the analog adaptive cancellation module so that the cancellation center of the system is located within the signal operating frequency.

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