A communication anti-interference method, device, system and storage medium

Abstract

The application discloses a communication anti-interference method, device, system and storage medium. The method comprises the following steps: a communication host sends a communication preparation signal to a communication slave; after detecting the communication preparation signal, the communication slave resets a preset register, and after the resetting is completed, controls a level signal on a preset communication state signal line to be a reset completion signal, wherein the preset register is a register associated with communication between the communication host and the communication slave; after detecting the reset completion signal, the communication host sends a control instruction to the communication slave. According to the technical scheme of the embodiment of the application, after the communication host sends the communication preparation signal to the communication slave, the communication slave can reset the preset register in time, delete interference data generated in the preset register due to electromagnetic interference in time, and notify the communication host that the resetting has been completed through the preset communication state signal line, so that the problem of communication abnormality caused by electromagnetic interference on a communication line is solved, and the communication reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a communication anti-interference method, apparatus, system, and storage medium. Background Technology

[0002] As the scale of integrated circuits continues to increase, the functions of ICs (Integrated Circuits) are becoming more and more numerous. Before leaving the factory, ICs must be tested. The core chips used in the testing instruments typically include Field Programmable Gate Array (FPGA) chips and Microcontroller Unit (MCU) chips.

[0003] Currently, the communication between FPGA and MCU in existing technologies uses the standard Serial Peripheral Interface (SPI) communication method, which is a high-speed, synchronous communication bus with full-duplex and half-duplex characteristics.

[0004] However, due to the complex electromagnetic environment in the IC test field and the long service life of the test instruments, the electromagnetic interference generated seriously affects the communication quality of the SPI communication signal lines, often leading to communication abnormalities and affecting the performance and working efficiency of the test instruments. Summary of the Invention

[0005] This invention provides a communication anti-interference method, apparatus, system, and storage medium to solve the problem of electromagnetic interference severely affecting communication.

[0006] In a first aspect, the present invention provides a communication anti-interference method, comprising:

[0007] The communication host sends a communication readiness signal to the communication slave;

[0008] After the communication slave detects the communication preparation signal, it resets the preset register, and after the reset is completed, it controls the level signal on the preset communication status signal line to be the reset completion signal. The preset register is a register associated with the communication between the communication master and the communication slave.

[0009] After detecting the reset completion signal, the communication host sends a control command to the communication slave.

[0010] Furthermore, according to a communication anti-interference method provided by the present invention, after the communication slave device detects the communication preparation signal, it resets the preset register, and after the reset is completed, it controls the level signal on the preset communication state signal line to be a reset completion signal, including:

[0011] After detecting the communication preparation signal, the communication slave device sends a high-level signal to the preset communication status signal line and resets the preset register;

[0012] After determining that the preset register has been reset, the communication slave device switches the high-level signal on the preset communication status signal line to a low-level signal, wherein the low-level signal on the preset communication status signal line is a reset completion signal.

[0013] Furthermore, according to a communication anti-interference method provided by the present invention, after the communication host sends a control command to the communication slave, the method further includes:

[0014] After executing the control command and verifying the received cyclic redundancy check code, the communication slave device sends an acknowledgment pulse signal to the communication host device through the preset communication status signal line. The acknowledgment pulse signal is used to notify the communication host device that the control command has been processed.

[0015] Furthermore, according to a communication anti-interference method provided by the present invention, after the communication slave device sends a high-level signal to the preset communication state signal line and resets the preset register, it further includes:

[0016] If the communication host fails to detect the first cumulative time used for the reset completion signal, and the time exceeds the first preset duration, then it is determined that the communication slave failed to reset the preset register. The starting time of the first cumulative time is the moment when the communication host detects the high-level signal sent by the communication slave to the preset communication status signal line.

[0017] Furthermore, according to a communication anti-interference method provided by the present invention, after the communication slave device sends an acknowledgment pulse signal to the communication host device through the preset communication status signal line, the method further includes:

[0018] If the communication host fails to detect the second cumulative timer used for the response pulse signal and the timer exceeds the second preset duration, then a communication anomaly is determined to have occurred between the communication host and the communication slave. The start time of the second cumulative timer is the time when the communication host sends the control command corresponding to the response pulse signal to the communication slave.

[0019] Furthermore, in a communication anti-interference method provided by the present invention, the preset register includes at least a shift register.

[0020] Furthermore, according to the communication anti-interference method provided by the present invention, there are multiple communication slave devices communicating with the communication host, and the communication between the communication host and the communication slave devices is independent of each other.

[0021] Secondly, the present invention provides a communication anti-interference device, comprising a signal transmitting module and an instruction transmitting module disposed on a communication host, and a signal control module disposed on a communication slave, wherein:

[0022] The signal transmitting module is used to send a communication preparation signal to the communication slave device;

[0023] The signal control module is used to reset a preset register after detecting the communication preparation signal, and after the reset is completed, control the level signal on the preset communication status signal line to be a reset completion signal, wherein the preset register is a register associated with the communication between the communication host and the communication slave;

[0024] The instruction sending module is used to send control instructions to the communication slave device after detecting the reset completion signal.

[0025] Thirdly, the present invention provides a communication anti-interference system, the system comprising:

[0026] A communication host and multiple communication slaves;

[0027] At least one processor; and a memory communicatively connected to said at least one processor;

[0028] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to instruct the communication host to execute the content executed by the communication host in the communication anti-interference method described in any of the preceding claims, and to instruct the communication slave to execute the content executed by the communication slave in the communication anti-interference method described in any of the preceding claims.

[0029] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a processor to execute the communication anti-interference method of the first aspect described above.

[0030] The communication anti-interference scheme provided by this invention involves a communication host sending a communication preparation signal to a communication slave. Upon detecting the communication preparation signal, the communication slave resets a preset register and, after the reset is complete, controls the level signal on the preset communication status signal line to be a reset completion signal. The preset register is a register associated with communication between the communication host and the communication slave. Upon detecting the reset completion signal, the communication host sends a control command to the communication slave. By adopting this technical solution, when the communication host sends a communication preparation signal to the communication slave, the communication slave can promptly reset the preset register, thereby deleting interference data caused by electromagnetic interference from the preset register and avoiding interference with the reception of normal data. After the reset is complete, the communication slave promptly notifies the communication host via the preset communication status signal line that it can send control commands to the communication slave. This solves the problem of communication anomalies caused by electromagnetic interference on the communication line and improves communication reliability.

[0031] It should be understood that the description in this section is not intended to identify key or essential features of the invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of a communication anti-interference method provided in Embodiment 1 of the present invention;

[0034] Figure 2 This is a flowchart of a communication anti-interference method provided in Embodiment 2 of the present invention;

[0035] Figure 3 This is a flowchart of anti-interference control for communication between an FPGA and an MCU according to Embodiment 2 of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a communication anti-interference device according to Embodiment 3 of the present invention;

[0037] Figure 5 This is a schematic diagram of a communication anti-interference system according to Embodiment 4 of the present invention;

[0038] Figure 6This is a structural example diagram of a communication host communicating with multiple communication slaves according to Embodiment 4 of the present invention. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0041] Example 1

[0042] Figure 1 The flowchart of a communication anti-interference method provided in Embodiment 1 of the present invention is applicable to communication anti-interference situations, such as communication anti-interference between FPGA chip and MCU chip in an integrated circuit tester. The method can be executed by a communication anti-interference device, which can be implemented in hardware and / or software. The communication anti-interference device can be configured in a communication anti-interference system, which includes a communication host and multiple communication slaves. The communication host can execute the content executed by the communication host in the communication anti-interference method, and the communication slaves can execute the content executed by the communication slaves in the communication anti-interference method.

[0043] like Figure 1 As shown, the communication anti-interference method provided in Embodiment 1 of the present invention specifically includes the following steps:

[0044] S101, The communication host sends a communication preparation signal to the communication slave.

[0045] In this embodiment, the communication between the communication master (such as an FPGA chip) and the communication slave (such as an MCU chip) can be achieved through various communication methods, including SPI communication, bidirectional two-wire synchronous serial bus communication, and CAN communication. Taking SPI communication as an example, the communication signal lines between the communication master and the communication slave include: MISO (Master Input Slave Output) signal lines, MOSI (Master Output Slave Input) signal lines, SCK (CMOS clock) signal lines, and CS (Chip Select) signal lines. A communication preparation signal can be sent to the communication slave through a preset communication signal line. In this embodiment, the preset communication signal line can be the CS signal line, and the communication preparation signal can be a low-level signal. For example, a low-level signal can be sent to the CS signal line first, indicating that the communication master is ready to communicate with the communication slave.

[0046] S102. After the communication slave detects the communication preparation signal, it resets the preset register, and after the reset is completed, it controls the level signal on the preset communication status signal line to be the reset completion signal. The preset register is a register associated with the communication between the communication master and the communication slave.

[0047] In this embodiment, after detecting the communication preparation signal, the communication slave device triggers a high-priority interrupt and resets a preset register, such as the register related to SPI communication. After the reset, the communication slave device can control the level signal on the newly added preset communication status signal line to be a reset completion signal. The preset communication status signal line is a newly added signal line that can be used to transmit the status signal of the communication slave device, such as transmitting a reset completion signal. The reset completion signal is used to notify the communication master that the preset register has been reset, and it can be a low-level signal, etc.

[0048] S103. After the communication host detects the reset completion signal, it sends a control command to the communication slave.

[0049] In this embodiment, after detecting the reset completion signal, the communication host can send control commands and data to the slave device via signal lines, such as sending data to the slave device via the MOSI signal line. The control commands include read commands and write commands. The structure of the write command frame is shown in Table 1, the structure of the read command frame is shown in Table 2, and the structure of the read data frame is shown in Table 3. CRC stands for Cyclic Redundancy Check.

[0050] Table 1 Write Instruction Structure Table

[0051]

[0052] Table 2 Read Command Frame Structure Table

[0053]

[0054] Table 3 Read Data Frame Structure Table

[0055] Bytes 1 to 4 5th byte Data Frame (D) Data Frame (CRC) DATA CRC

[0056] The communication anti-interference method provided in this embodiment of the invention involves a communication host sending a communication preparation signal to a communication slave. Upon detecting the communication preparation signal, the communication slave resets a preset register and, after the reset is complete, controls the level signal on the preset communication status signal line to be a reset completion signal. The preset register is a register associated with communication between the communication host and the communication slave. Upon detecting the reset completion signal, the communication host sends a control command to the communication slave. This technical solution allows the communication slave to promptly reset the preset register after the communication host sends the communication preparation signal, thereby deleting interference data caused by electromagnetic interference from the preset register and avoiding interference with the reception of normal data. After the reset is complete, the communication slave promptly notifies the communication host via the preset communication status signal line that it can send control commands to the communication slave. This solves the problem of communication anomalies caused by electromagnetic interference on the communication line and improves communication reliability.

[0057] Example 2

[0058] Figure 2 This is a flowchart of a communication anti-interference method provided in Embodiment 2 of the present invention. The technical solution of the present invention is further optimized based on the above optional technical solutions, and a specific method for communication anti-interference is given.

[0059] Optionally, after detecting the communication preparation signal, the communication slave device resets the preset register, and after the reset is complete, controls the level signal on the preset communication state signal line to be a reset completion signal. This includes: after detecting the communication preparation signal, the communication slave device sends a high-level signal to the preset communication state signal line and resets the preset register; after determining that the preset register has been reset, the communication slave device switches the high-level signal on the preset communication state signal line to a low-level signal, wherein the low-level signal on the preset communication state signal line is a reset completion signal. The advantage of this setting is that by changing the level signal on the preset communication state signal line before and after resetting the preset register, the communication host can promptly determine the state of the preset register, ensuring the accuracy and integrity of data transmission.

[0060] Optionally, after the communication host sends a control command to the communication slave, the method further includes: after the communication slave executes the control command and passes the verification of the received cyclic redundancy check code, it sends an acknowledgment pulse signal to the communication host through the preset communication status signal line. The acknowledgment pulse signal is used to notify the communication host that the control command has been processed. The advantage of this configuration is that by sending an acknowledgment pulse signal to the communication host through the preset communication status signal line, the communication slave can inform the communication host that the command has been processed, allowing the communication host to send the next command, thus ensuring the orderly nature of communication.

[0061] Optionally, after the communication slave sends a high-level signal to the preset communication status signal line and resets the preset register, the method further includes: if the communication host fails to detect the first cumulative timer used for the reset completion signal, and the timer exceeds a first preset duration, then it is determined that the communication slave failed to reset the preset register. The starting time of the first cumulative timer is the moment the communication host detects the high-level signal sent by the communication slave to the preset communication status signal line. The advantage of this setting is that by determining the first cumulative timer, the communication host can accurately determine whether the reset of the preset register is normal and whether a reset failure has occurred in the communication slave.

[0062] like Figure 2 As shown, the communication anti-interference method provided in Embodiment 2 of the present invention specifically includes the following steps:

[0063] S201, The communication host sends a communication preparation signal to the communication slave.

[0064] For example, if the communication master is an FPGA chip (hereinafter referred to as FPGA), the communication slave is an MCU chip (hereinafter referred to as MCU), and the communication method is SPI communication. Figure 3This is a flowchart illustrating an anti-interference control process for communication between an FPGA and an MCU. Figure 3 As shown, if the low-level signal is a communication preparation signal, the FPGA can first send a low-level signal to CS (signal line), that is, "CS is pulled low".

[0065] S202. After the communication slave detects the communication preparation signal, it sends a high-level signal to the preset communication status signal line and resets the preset register.

[0066] For example, if the preset communication status signal line is the BUSY signal line, such as Figure 3 As shown, after the MCU detects a low-level signal (communication preparation signal) on the CS signal line, it will trigger an interrupt response, send a high-level signal to the BUSY signal line, and reset the preset register.

[0067] Optionally, the preset register may include at least a shift register.

[0068] Specifically, the preset register can be a shift register related to communication.

[0069] S203. If the first cumulative time used by the communication host to detect the reset completion signal exceeds the first preset time, it is determined that the communication slave failed to reset the preset register.

[0070] The timing start time of the first cumulative timing is the moment when the communication host detects the high-level signal sent by the communication slave to the preset communication state signal line.

[0071] For example, the FPGA starts timing from the moment it detects a high-level signal sent by the MCU to a preset communication state signal line, and stops timing upon receiving a low-level signal (reset completion signal). Figure 3 As shown, if the first cumulative time exceeds the first preset duration, such as 2 microseconds, it can be determined that the waiting timeout or the MCU failed to reset the SPI peripheral (i.e., the preset register). The first preset duration can be set according to actual needs, such as 3 microseconds, etc., and is not limited here.

[0072] S204. After the communication slave device has completed the preset register reset, it switches the high-level signal on the preset communication status signal line to a low-level signal.

[0073] Among them, the low-level signal on the preset communication status signal line is the reset completion signal.

[0074] For example, such as Figure 3 As shown, after the MCU confirms that the SPI-related preset registers (SPI peripherals) have been reset, it will switch the high-level signal on the BUSY signal line to a low-level signal. It should be noted that... Figure 3In SPI peripherals, the term refers to preset registers, which can be shift registers, etc.

[0075] S205. After the communication host detects the reset completion signal, it sends a control command to the communication slave.

[0076] For example, such as Figure 3 As shown, after the FPGA detects a low-level signal on the BUSY signal line, it will output a rising edge (valid signal) on the SCK signal line, as well as an output control word (i.e., control instruction) and a data frame address. If the control instruction is a write instruction, the FPGA will send a data frame and a CRC check frame to the MCU, and after sending, it will send a high-level signal to the SCK and CS signal lines. If the control instruction is a read instruction, the FPGA will maintain a high-level output on the SCK signal line, send a CRC check frame, and after sending, it will send a high-level signal to the SCK and CS signal lines.

[0077] S206. After executing the control command and verifying the received cyclic redundancy check code, the communication slave sends an acknowledgment pulse signal to the communication host through the preset communication status signal line.

[0078] The response pulse signal is used to notify the communication host that the control command has been processed.

[0079] For example, such as Figure 3 As shown, after the MCU executes the control command and verifies the received cyclic redundancy check code, it will send an acknowledgment pulse signal to the FPGA via the BUSY signal line.

[0080] Optionally, after the communication slave sends an acknowledgment pulse signal to the communication host via the preset communication status signal line, the method further includes: if the communication host fails to detect the second cumulative timer used for the acknowledgment pulse signal, and the timer exceeds a second preset duration, then it determines that a communication anomaly has occurred with the communication slave. The starting time of the second cumulative timer is the moment when the communication host sends the control command corresponding to the acknowledgment pulse signal to the communication slave. The advantage of this configuration is that by determining the second cumulative timer, the communication host can promptly detect communication failures occurring in the communication slave.

[0081] For example, such as Figure 3 As shown, the second preset duration is 30 microseconds. The FPGA sends a control command to the MCU to start timing and stops timing upon receiving a response pulse signal. If the second cumulative timing exceeds the second preset duration, i.e., greater than 30 microseconds, it can be determined that the waiting timeout or CRC check failure has occurred, i.e., a communication abnormality has occurred.

[0082] Optional, such as Figure 3As shown, if the control command sent by the FPGA is a read command, after the MCU sends an acknowledgment pulse signal to the FPGA via the BUSY signal line, the FPGA will continue to send a high-level signal to the SCK signal line and a low-level signal to the CS signal line, receiving the readback data frame and readback CRC check frame sent by the MCU. After receiving all the data, it will send a high-level signal to the CS signal line and continue sending a high-level signal to the SCK signal line. If the FPGA passes the cyclic redundancy check (CRC) check, it can exit.

[0083] Optionally, the number of communication slaves communicating with the communication host can be multiple, and the communication between the communication host and the communication slaves is independent of each other. This configuration improves the efficiency of communication between the communication host and multiple communication slaves.

[0084] The communication anti-interference method provided in this embodiment of the invention, by changing the level signal on the preset communication state signal line before and after resetting the preset register, enables the communication host to determine the state of the preset register in a timely manner, ensuring the accuracy and integrity of data transmission. The communication slave sends an acknowledgment pulse signal to the communication host through the preset communication state signal line, which can inform the communication host that the instruction has been processed and the communication host can send the next instruction, thus ensuring the orderliness of communication. By determining the first cumulative time, the communication host can accurately determine whether the reset of the preset register is normal and whether the communication slave has experienced a reset failure.

[0085] Example 3

[0086] Figure 4 This is a schematic diagram of a communication anti-interference device provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes a signal transmission module 401 and a command transmission module 403 disposed on the communication host, and a signal control module 402 disposed on the communication slave, wherein:

[0087] The signal transmitting module is used to send a communication preparation signal to the communication slave device;

[0088] The signal control module is used to reset a preset register after detecting the communication preparation signal, and after the reset is completed, control the level signal on the preset communication status signal line to be a reset completion signal, wherein the preset register is a register associated with the communication between the communication host and the communication slave;

[0089] The instruction sending module is used to send control instructions to the communication slave device after detecting the reset completion signal.

[0090] The communication anti-interference device provided in this embodiment of the invention enables the communication slave to promptly reset the preset register after the communication host sends a communication preparation signal to the communication slave. This promptly deletes the interference data generated by electromagnetic interference in the preset register, which affects the reception of normal data. After the reset is completed, the communication slave promptly notifies the communication host using the preset communication status signal line, so that the communication host can send control commands to the communication slave. This solves the problem of communication abnormalities caused by electromagnetic interference on the communication line and improves communication reliability.

[0091] Optionally, the signal control module includes:

[0092] A reset unit is used to send a high-level signal to a preset communication state signal line and reset a preset register after detecting the communication preparation signal.

[0093] The signal switching unit is used to switch the high-level signal on the preset communication state signal line to a low-level signal after determining that the preset register has been reset. The low-level signal on the preset communication state signal line is a reset completion signal.

[0094] Optionally, the device may also include:

[0095] The pulse signal transmitting module, belonging to the communication slave unit, is used to send an acknowledgment pulse signal to the communication host through the preset communication status signal line after the communication host sends a control command to the communication slave unit, and after executing the control command and verifying the received cyclic redundancy check code. The acknowledgment pulse signal is used to notify the communication host that the control command has been processed.

[0096] Optionally, the signal control module includes:

[0097] The reset judgment unit is used to determine that the communication slave failed to reset the preset register if, after the communication slave sends a high-level signal to the preset communication status signal line and resets the preset register, the first cumulative time used to detect the reset completion signal is not detected and the time exceeds a first preset duration. The timing start time of the first cumulative time is the moment when the communication host detects the high-level signal sent by the communication slave to the preset communication status signal line.

[0098] Optionally, the device may also include:

[0099] The communication anomaly determination module, belonging to the communication host, is used to determine that a communication anomaly has occurred between the communication slave and the communication host if, after the communication slave sends an acknowledgment pulse signal to the communication host through the preset communication status signal line, the second cumulative timer used for the acknowledgment pulse signal is not detected and exceeds the second preset duration. The timing start time of the second cumulative timer is the time when the communication host sends the control command corresponding to the acknowledgment pulse signal to the communication slave.

[0100] Optionally, the preset register may include at least a shift register.

[0101] Optionally, there may be multiple communication slaves communicating with the communication host, and the communication between the communication host and the communication slaves is independent of each other.

[0102] The communication anti-interference device provided in the embodiments of the present invention can execute the communication anti-interference method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0103] Example 4

[0104] Figure 5 A schematic diagram of a communication anti-jamming system 50, which can be used to implement embodiments of the present invention, is shown. The communication anti-jamming system includes: a communication host terminal 51, multiple communication slave terminals 52, a processor 53, and a memory 54. The memory stores a computer program executable by the processor. When executed by the processor, the computer program enables the processor to instruct the communication host terminal to perform the content executed by the communication host in the communication anti-jamming method, and to instruct the communication slave terminals to perform the content executed by the communication slave terminals in the communication anti-jamming method. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein. Figure 6 This is a structural example of a communication master communicating with multiple communication slaves. If the communication master is an FPGA chip, the communication slaves are MCU chips, and the communication method is SPI communication, then... Figure 6 As shown, the communication host and the communication slave can be different chips in the same electronic device. The processor and memory in the system can be built into the same host computer, which can be used to control the communication host and the communication slave to implement the communication anti-interference method.

[0105] The memory in a communication anti-jamming system can be a read-only memory (ROM), random access memory (RAM), etc. The memory stores computer programs that can be executed by at least one processor. The processor can perform various appropriate actions and processes based on the computer program stored in the ROM or loaded from a memory location into the RAM. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0106] Multiple components in the communication jamming suppression system are connected to I / O interfaces, including: input units such as keyboards and mice; output units such as various types of displays and speakers; storage units such as disks and optical discs; and communication units such as network interface cards (NICs), modems, and wireless transceivers. The communication units allow the communication jamming suppression system to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0107] A processor can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processors include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processors perform the various methods and processes described above, such as communication anti-interference methods.

[0108] In some embodiments, the communication jamming method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed into the communication jamming system via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the communication jamming method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the communication jamming method by any other suitable means (e.g., by means of firmware).

[0109] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0111] The computer equipment provided above can be used to execute the communication anti-interference method provided in any of the above embodiments, and has the corresponding functions and beneficial effects.

[0112] Example 5

[0113] In the context of this invention, the computer-readable storage medium may be a tangible medium, and the computer-executable instructions, when executed by a computer processor, are used to perform a communication anti-interference method, the method comprising:

[0114] The communication host sends a communication readiness signal to the communication slave;

[0115] After the communication slave detects the communication preparation signal, it resets the preset register, and after the reset is completed, it controls the level signal on the preset communication status signal line to be the reset completion signal. The preset register is a register associated with the communication between the communication master and the communication slave.

[0116] After detecting the reset completion signal, the communication host sends a control command to the communication slave.

[0117] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by, or in conjunction with, an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0118] The computer equipment provided above can be used to execute the communication anti-interference method provided in any of the above embodiments, and has the corresponding functions and beneficial effects.

[0119] It is worth noting that in the embodiments of the above-mentioned communication anti-interference device, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0120] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A communication anti-interference method, characterized in that, include: The communication master sends a communication preparation signal to the communication slave; wherein the communication slave is an MCU chip; the communication master and the communication slave use SPI communication; the communication preparation signal is a low-level signal sent to the CS signal line of SPI communication, and the communication preparation signal is used to trigger a high-priority interrupt of the communication slave; After detecting the communication preparation signal, the communication slave device resets the preset register, and after the reset is completed, controls the level signal on the preset communication status signal line to be the reset completion signal. The preset register is a register associated with communication between the communication master and the communication slave device; the register is a register associated with SPI communication; and the preset communication status signal line is the BUSY signal line. After detecting the reset completion signal, the communication host sends a control command to the communication slave.

2. The method according to claim 1, characterized in that, After the communication slave device detects the communication preparation signal, it resets the preset register, and after the reset is complete, it controls the level signal on the preset communication status signal line to be the reset completion signal, including: After detecting the communication preparation signal, the communication slave device sends a high-level signal to the preset communication status signal line and resets the preset register; After determining that the preset register has been reset, the communication slave device switches the high-level signal on the preset communication status signal line to a low-level signal, wherein the low-level signal on the preset communication status signal line is a reset completion signal.

3. The method according to claim 1, characterized in that, After the communication host sends a control command to the communication slave, the method further includes: After executing the control command and verifying the received cyclic redundancy check code, the communication slave device sends an acknowledgment pulse signal to the communication host device through the preset communication status signal line. The acknowledgment pulse signal is used to notify the communication host device that the control command has been processed.

4. The method according to claim 2, characterized in that, After the communication slave device sends a high-level signal to the preset communication status signal line and resets the preset register, the following steps are also included: If the communication host fails to detect the first cumulative time used for the reset completion signal, and the time exceeds the first preset duration, then it is determined that the communication slave failed to reset the preset register. The starting time of the first cumulative time is the moment when the communication host detects the high-level signal sent by the communication slave to the preset communication status signal line.

5. The method according to claim 3, characterized in that, After the slave device sends an acknowledgment pulse signal to the master device via the preset communication status signal line, the method further includes: If the communication host fails to detect the second cumulative timer used for the response pulse signal and the timer exceeds the second preset duration, then a communication anomaly is determined to have occurred between the communication host and the communication slave. The start time of the second cumulative timer is the time when the communication host sends the control command corresponding to the response pulse signal to the communication slave.

6. The method according to claim 1, characterized in that, The preset registers include at least a shift register.

7. The method according to claim 1, characterized in that, The number of communication slaves communicating with the communication host is multiple, and the communication between the communication host and the communication slaves is independent of each other.

8. A communication anti-interference device, characterized in that, It includes a signal transmission module and a command transmission module located on the communication host, and a signal control module located on the communication slave, wherein: The signal transmitting module is used to send a communication preparation signal to the communication slave device; wherein, the communication slave device is an MCU chip; the communication master and the communication slave device adopt SPI communication; the communication preparation signal is a low-level signal sent to the CS signal line of SPI communication, and the communication preparation signal is used to trigger a high-priority interrupt of the communication slave device; The signal control module is used to reset a preset register after detecting the communication preparation signal, and after the reset is completed, control the level signal on the preset communication status signal line to be a reset completion signal. The preset register is a register associated with communication between the communication master and the communication slave; the register is a register associated with SPI communication; and the preset communication status signal line is a BUSY signal line. The instruction sending module is used to send control instructions to the communication slave device after detecting the reset completion signal.

9. A communication anti-interference system, characterized in that, The system includes: A communication host and multiple communication slaves; At least one processor; and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to instruct the communication host to execute the content executed by the communication host in the communication anti-interference method according to any one of claims 1-7, and to instruct the communication slave to execute the content executed by the communication slave in the communication anti-interference method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the communication anti-interference method according to any one of claims 1-7.

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