A hardware implementation network architecture of a full-digital large-scale phased array multi-beam forming

Abstract

This invention discloses a hardware implementation network architecture for all-digital large-scale phased array multibeamforming, comprising: a subarray including multiple TR components and a primary DBF board connected to each of the multiple TR components; the primary DBF board is used to perform digital multibeamforming on the digital signals transmitted by the multiple TR components to obtain a primary beamforming digital downlink signal, and is also used to transmit digital uplink signals to the multiple TR components; a secondary DBF board is connected to the primary DBF board, used to process the received primary digital multibeamforming signals to obtain a third-level beamforming digital downlink signal and a beamforming analog signal, and is also used to transmit the baseband digital uplink signal to the primary DBF board. This invention features a modular board design and a clear hardware architecture.

Description

Technical Field

[0001] This invention relates to the field of digital beamforming technology, and in particular to a hardware implementation network architecture for all-digital large-scale phased array multi-beamforming. Background Technology

[0002] Digital multibeam is a technology that combines electronic beam scanning of array antennas with flexible digital signal processing. By controlling the beamforming weighting coefficients and maintaining stable equipment delay, it can generate multiple independently operating beams in different directions simultaneously and achieve rapid and efficient switching of beam pointing, enabling tasks such as simultaneous tracking and communication of multiple targets across the entire airspace.

[0003] Digital beamforming (DBF) is a new technology developed and extended from the phased array principle, integrating digital signal processing methods. It generates directional beams by controlling parameters such as the phase and amplitude of the excitation signal for each element of the array antenna. In traditional phased array antennas, the amplitude weighting and phase control required for beamforming are implemented in the radio frequency (RF) section using microwave networks (attenuators and phase shifters). Analog phase shifters and attenuators result in large networks and insufficient beam control accuracy and flexibility, making them unsuitable for large-scale phased array implementations. In a DBF system, amplitude and phase weighting control is implemented in the baseband signal. For the transmit beam, digital weighting is performed before the baseband signal is converted from analog to digital (i.e., before being fed into the antenna elements). For the receive beam, the received signal is down-converted from analog to digital and then digitally weighted. By using digital weighting, the RF phase shifter and attenuator networks are eliminated, enhancing beam control accuracy and flexibility.

[0004] With the rapid development of chip technology today, high-speed AD / DA chips, high-speed programmable logic devices (FPGAs), high-speed digital signal processing chips (DSPs), high-speed backplane transmission VPX technology, advanced optoelectronic / electro-optical conversion technology, and high-speed fiber optic transmission technology have made the design of all-digital large-scale phased array beamforming a reality.

[0005] All-digital large-scale phased array multibeamforming is based on an efficient, stable and reliable hardware network architecture. Therefore, the technical solution should focus on designing high-speed and stable DBF hardware boards and high-speed communication connection networks between DBF boards. Summary of the Invention

[0006] In view of this, the present invention provides a hardware implementation network architecture for all-digital large-scale phased array multibeamforming to solve the above-mentioned technical problems.

[0007] This invention discloses a hardware implementation network architecture for all-digital large-scale phased array multibeamforming, which includes: a subarray, a secondary DBF board, and a DBF switching board connected in sequence, and also includes a digital interface board and an analog interface board respectively connected to the DBF switching board;

[0008] The subarray includes multiple TR components and primary DBF boards connected to the multiple TR components respectively; wherein, the TR components are used to implement downlink received signal filtering, low-noise amplification, analog downconversion, and analog-to-digital conversion; and to implement uplink transmitted signal digital-to-analog conversion, analog upconversion, and power amplification;

[0009] The primary DBF board is used to perform digital multi-beamforming on the digital signals sent by multiple TR components to obtain primary beamforming digital downlink signals, and is also used to send primary beamforming digital uplink signals to multiple TR components.

[0010] The secondary DBF board is connected to the primary DBF board and is used to process the received primary digital multi-beamforming signal to obtain the third-level beamforming digital downlink signal and beamforming analog signal. It is also used to send the baseband digital uplink signal to the primary DBF board.

[0011] Furthermore, the secondary DBF board includes a second-level board, a third-level board, a DBF switching board connected in sequence, and a digital interface board and an analog interface board respectively connected to the DBF switching board;

[0012] The second-level board is connected to the primary DBF board and is used to converge the primary beamforming digital downlink signal sent by the primary DBF board to obtain the second-level beamforming digital downlink signal, and then send the second-level beamforming digital downlink signal to the third-level board.

[0013] The third-level board is used to converge the received second-level beamforming digital downlink signal to obtain the third-level beamforming digital downlink signal, and send the formed third-level beamforming digital downlink signal to the DBF switching board; at the same time, it sends the formed third-level beamforming digital uplink signal to the second-level board.

[0014] The DBF switching board is used to send the received third-level beamforming digital downlink signal to the digital interface board and the analog interface board respectively, and at the same time send the baseband digital uplink signal received from the digital interface board to the third-level board.

[0015] The digital interface board is used to send the received baseband digital uplink signal to the DBF switching board, and at the same time send the received third-level beamforming digital downlink signal to the digital baseband.

[0016] The analog interface board is used to receive the third-level beamforming digital downlink signal and convert it into a beamforming analog signal.

[0017] Furthermore, it also includes a digital baseband connected to the digital interface board, and test instruments connected to the analog interface board;

[0018] The digital baseband is used to send baseband digital uplink signals to the digital interface board and simultaneously receive third-level beamforming digital downlink signals sent by the digital interface board.

[0019] The testing instrument is used to receive beamforming analog signals sent by the analog interface board.

[0020] Furthermore, the primary DBF board includes a control chip FPGA, a signal processing FPGA, and an optical communication module connected in sequence;

[0021] The control chip FPGA is used to output control information to the signal processing FPGA and receive status information sent by the signal processing FPGA; wherein, the control information includes beam switching, rotation selection, and master / standby selection, and the status information includes the temperature, voltage, clock, link status, and beam operating status of the signal processing FPGA;

[0022] The signal processing FPGA is used to receive digital uplink multibeam signals sent by the optical communication module, and to send digital downlink multibeam signals to the optical communication module.

[0023] The optical communication module is used to send downlink multi-beam optical output signals (i.e., primary beamforming digital downlink signals) to the secondary DBF board, and simultaneously receive uplink multi-beam optical input signals (i.e., second-stage beamforming digital uplink signals) sent by the secondary DBF board.

[0024] Furthermore, the secondary DBF boards communicate with each other via the backplane of the secondary DBF chassis or via digital optical fiber and optical communication modules to achieve the convergence of downlink received digital multi-beamforming signals and the distribution of uplink transmitted digital multi-beam signals.

[0025] Furthermore, the secondary DBF chassis is a VPX chassis, each VPX chassis has M+1 slots, where M is an even number, and the M / 2+1th slot communicates with the other slots via a backplane for high-speed data exchange.

[0026] Furthermore, the second-level board includes an optical communication module group, a signal processing FPGA connected to the optical communication module group, and a chassis backplane and a DSP respectively connected to the signal processing FPGA;

[0027] The optical communication module group is used to receive primary beamforming digital downlink signals sent by the primary DBF board and to receive secondary beamforming digital uplink signals sent to the primary DBF board; wherein, the optical communication module group includes several optical communication modules;

[0028] The signal processing FPGA is used to receive the digital downlink multi-beam signal output from the optical communication module group, and at the same time output the digital uplink multi-beam signal to the optical communication module group.

[0029] The chassis backplane is used to transmit the digital downlink multibeam signal output from the signal processing FPGA to the third-level board.

[0030] The DSP is used to output control information to the signal processing FPGA and receive status information reported by the signal processing FPGA.

[0031] Furthermore, the third-level board includes a signal processing FPGA, and a chassis backplane group and an optical communication module group respectively connected to the signal processing FPGA;

[0032] The signal processing FPGA is used to aggregate the second-level digital downlink multi-beam signal transmitted from the chassis backplane group and send it to the optical communication module group. At the same time, it distributes the digital uplink multi-beam signal sent by the optical communication module group and transmits it to the chassis backplane group. The chassis backplane group includes several chassis backplanes, and the optical communication module group includes several optical communication modules.

[0033] Furthermore, the DBF switching board includes an optical communication module group, a signal processing FPGA, a chassis backplane, and a DSP;

[0034] The optical communication module group is used to receive the third-level beamforming digital downlink signal sent by the third-level board, and at the same time send digital uplink multi-beam signals to the third-level board; the optical communication module group includes several optical communication modules.

[0035] The signal processing FPGA is used to receive the digital downlink multi-beam signal output from the optical communication module group and output the digital uplink multi-beam signal to the optical communication module group; it is used to implement the configuration of the digital switch matrix, select the digital downlink beam signal to the digital baseband through the digital interface board, select the digital uplink signal from the digital baseband of the digital interface board to be transmitted to the third-level board through the optical module, and select the digital downlink beam signal to the test instrument through the analog interface board for beam performance testing.

[0036] The chassis backplane is used to output the digital downlink multibeam signal from the signal processing FPGA to the digital interface board and the analog interface board, respectively.

[0037] The DSP is used to output control information to the signal processing FPGA and receive status information reported by the signal processing FPGA.

[0038] Furthermore, the digital interface board includes a chassis backplane, a signal processing FPGA, and an optical communication module group;

[0039] The signal processing FPGA is used to transmit the digital downlink multi-beam signal sent from the chassis backplane to the optical communication module group, and at the same time output the digital uplink multi-beam signal received from the optical communication module group to the chassis backplane; wherein, the optical communication module group includes several optical communication modules;

[0040] The analog interface board includes a chassis backplane, a signal processing FPGA, and a digital-to-analog conversion module;

[0041] The signal processing FPGA is used to transmit the digital downlink multibeam signal sent from the chassis backplane to the digital-to-analog converter module;

[0042] The digital-to-analog converter module is used to convert the received digital downlink multibeam signal into an analog signal and transmit it to the test instrument.

[0043] Because of the adoption of the above technical solution, the present invention has the following advantages:

[0044] (1) Modular board design with a clear hardware architecture. This invention designs digital TR components and DBF boards at all levels, as well as secondary DBF chassis, by functionally dividing and positioning them.

[0045] (2) Flexible and dynamic configuration of DBF board quantity. This invention can flexibly and dynamically calculate the number of subarrays according to the required number of array elements for large-scale phased arrays, and then calculate the number of configurable DBF boards at each level.

[0046] (3) Dynamic configuration of the number of convergence and distribution DBF stages. This invention can dynamically calculate and configure the number of secondary convergence and distribution stages based on the number of large-scale phased array subarrays, without limiting the number of secondary DBF stages, and reasonably optimize the number of boards and chassis resources of each stage of the secondary DBF according to requirements. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0048] Figure 1 This is a schematic diagram of a hardware board implementation network architecture for a fully digital large-scale phased array multibeamforming system according to an embodiment of the present invention.

[0049] Figure 2This is a schematic diagram illustrating the communication connection between a digital TR component within a subarray and a primary DBF board according to an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of the installation of a secondary DBF second-level board and a third-level board in a custom standardized VPX chassis according to an embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of the installation of a secondary DBF switching board and a digital interface board / analog interface board in a custom standardized VPX chassis according to an embodiment of the present invention.

[0052] Figure 5 This is a schematic diagram of the main hardware components and communication of a primary DBF board according to an embodiment of the present invention.

[0053] Figure 6 This is a schematic diagram of the main hardware components and communication of a secondary DBF second-level board according to an embodiment of the present invention.

[0054] Figure 7 This is a schematic diagram of the main hardware components and communication of a secondary DBF third-level board according to an embodiment of the present invention.

[0055] Figure 8 This is a schematic diagram of the main hardware components and communication of a secondary DBF board switching board according to an embodiment of the present invention.

[0056] Figure 9 This is a schematic diagram of the main hardware components and communication of a secondary DBF board digital interface board according to an embodiment of the present invention.

[0057] Figure 10 This is a schematic diagram of the main hardware components and communication of a secondary DBF board simulation interface board according to an embodiment of the present invention. Detailed Implementation

[0058] The present invention will be further described in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0059] See Figure 1 The present invention provides an embodiment of a hardware implementation network architecture for a fully digital large-scale phased array multibeamforming system, comprising: a subarray, a secondary DBF board, and a DBF switching board connected in sequence, and further comprising a digital interface board and an analog interface board respectively connected to the DBF switching board;

[0060] See Figure 2The subarray includes multiple TR components and primary DBF boards connected to the multiple TR components respectively; wherein, the TR components are used to implement downlink received signal filtering, low noise amplification, analog downconversion, and analog-to-digital conversion; and to implement uplink transmitted signal digital-to-analog conversion, analog upconversion, and power amplification;

[0061] In the digital TR component, the analog-to-digital and digital-to-analog converter (AD / DA) chips can be Analog Devices' AD9684 / AD9739, etc.

[0062] The primary DBF board is used to perform digital multi-beamforming on digital signals sent by multiple TR components to obtain primary beamforming digital downlink signals, and is also used to send primary beamforming digital uplink signals to multiple TR components.

[0063] The secondary DBF board connects to the primary DBF board and is used to process the received primary digital multi-beamforming signal to obtain the third-level beamforming digital downlink signal and beamforming analog signal. It is also used to send the baseband digital uplink signal to the primary DBF board.

[0064] In this embodiment, a digital TR component is connected to multiple antenna elements. A primary DBF board is connected to multiple digital TR components to form a complete subarray, realizing digital multi-beamforming for signal reception and transmission of all elements within the subarray. Based on the total number of phased array elements, the number of elements connected to a single digital TR component, and the number of digital TR components connected to a primary DBF board, the number of subarrays and the required number of primary DBF boards and digital TR components for this large-scale phased array can be calculated. The primary DBF board and the digital TR components are connected via high-speed cables or high-speed digital optical fibers, and the high-speed data link communication uses the high-speed serial Auraro protocol or the 204B protocol. The secondary DBF board is connected to multiple primary DBF boards via digital multiplexed fiber optic cables and CXP modules. The high-speed data transmission protocol between them also adopts the high-speed serial Auraro protocol or the 204B protocol to achieve the convergence of downlink received subarray-level digital multi-beamforming signals and the distribution of uplink transmitted digital multi-beam signals. The required number of secondary DBF boards is calculated based on how many primary DBF boards are connected to a single secondary DBF board and the number of primary DBF boards. Secondary DBF boards communicate with each other via the secondary DBF chassis backplane or through digital fiber optic cables and CXP modules, enabling downlink reception of digital multi-beamforming signals and uplink transmission of digital multi-beamforming signals. For example, six secondary DBF level-two boards can simultaneously communicate with one secondary DBF level-three board, resulting in a 6:1 convergence-to-distribution ratio. The secondary DBF chassis uses a custom-designed large-scale data exchange VPX chassis with a standardized design. Each chassis has seven slots, symmetrically divided in half. Slots 1 / 2 / 3 / 5 / 6 / 7 communicate with slot 4 via the backplane for high-speed data exchange. (See also...) Figure 3 and Figure 4 The number of secondary DBF boards at each stage is calculated based on the number of preceding boards and the aggregation / distribution ratio. Generally, two types of secondary DBF boards are installed in one secondary DBF chassis to achieve downlink digital multi-beam signal aggregation and uplink digital multi-beam signal distribution. Finally, after multi-stage downlink aggregation, the signal is sent to the secondary DBF switching board. The secondary DBF switching board communicates with the digital interface board and analog interface board through the chassis backplane. The secondary DBF switching board implements digital switch matrix configuration, flexibly selecting digital beams to go through the digital interface board to the digital baseband, and flexibly selecting digital beams to go through the analog interface board to the test instrument for beam performance testing. The digital interface board and digital baseband communicate via digital fiber optic connection. The secondary DBF analog interface board performs digital-to-analog or analog-to-digital conversion of the beam signals, connecting to the test instrument via coaxial cable for observation and testing. The high-speed data fiber optic or backplane communication protocols between secondary DBF boards and between the secondary DBF digital interface board and digital baseband are also the high-speed serial communication Auraro protocol or 204B protocol.

[0065] Specifically, the secondary DBF board includes a second-level board, a third-level board, a DBF switching board connected in sequence, and a digital interface board and an analog interface board connected to the DBF switching board respectively;

[0066] See Figure 6 The second-level board is connected to the primary DBF board and is used to converge the primary beamforming digital downlink signal sent by the primary DBF board to obtain the second-level beamforming digital downlink signal. At the same time, the second-level beamforming digital downlink signal formed by it is sent to the third-level board.

[0067] See Figure 7 The third-level board is used to converge the received second-level beamforming digital downlink signal to obtain the third-level beamforming digital downlink signal, and at the same time send the third-level beamforming digital uplink signal formed by the second-level board to it.

[0068] See Figure 8 The DBF switching board is used to send the received third-level beamforming digital downlink signal to the digital interface board and the analog interface board respectively, and at the same time send the baseband digital uplink signal received from the digital interface board to the third-level board.

[0069] See Figure 9 The digital interface board is used to send the received baseband digital uplink signal to the DBF switching board, and at the same time send the received third-level beamforming digital downlink signal to the digital baseband.

[0070] See Figure 10 The analog interface board is used to receive the third-level beamforming digital downlink signal and convert it into a beamforming analog signal.

[0071] Specifically, it also includes a digital baseband connected to the digital interface board, and test instruments connected to the analog interface board;

[0072] The digital baseband is used to send baseband digital uplink signals to the digital interface board and simultaneously receive third-level beamforming digital downlink signals sent by the digital interface board.

[0073] The testing instrument is used to receive beamforming analog signals sent by the analog interface board.

[0074] Specifically, see Figure 5 The primary DBF board includes a control chip FPGA, a signal processing FPGA, and an optical communication module connected in sequence.

[0075] The control chip FPGA is used to output control information to the signal processing FPGA and receive status information sent by the signal processing FPGA. The control information includes beam switching, rotation selection, and master / slave selection, while the status information includes the temperature, voltage, clock, link status, and beam operating status of the signal processing FPGA.

[0076] The signal processing FPGA is used to receive digital uplink multi-beam signals sent by the optical communication module and to send digital downlink multi-beam signals to the optical communication module. The control chip can be a Xilinx Zynq-7000 series FPGA chip, and the digital beamforming large-scale FPGA chip can be a Xilinx Virtex-7 series or Virtex UltraScale series FPGA chip.

[0077] The optical communication module is used to send downlink multi-beam optical output signals (i.e., primary beamforming digital downlink signals) to the secondary DBF board, and simultaneously receive uplink multi-beam optical input signals (i.e., second-stage beamforming digital uplink signals) sent by the secondary DBF board.

[0078] Specifically, the secondary DBF boards communicate with each other through the backplane of the secondary DBF chassis or through digital optical fiber and optical communication modules to achieve the convergence of downlink received digital multi-beamforming signals and the distribution of uplink transmitted digital multi-beam signals.

[0079] Specifically, the secondary DBF chassis is a VPX chassis, with each VPX chassis having M+1 slots, where M is an even number. The M / 2+1th slot communicates with the other slots via a backplane for high-speed data exchange. Taking a 7-slot configuration as an example, the slots are symmetrically divided in half, with the second-level boards in slots 1 / 2 / 3 / 5 / 6 / 7 communicating with the third-level board in slot 4.

[0080] In this embodiment, the number of each stage of the secondary DBF board is calculated based on the number of the preceding boards and the aggregation / distribution ratio. Generally, two types of secondary DBF boards are installed in one secondary DBF chassis to achieve downlink digital multi-beam signal aggregation and uplink digital multi-beam signal distribution. Finally, after multi-stage downlink aggregation, the signal is fed to the secondary DBF switching board. The secondary DBF switching board communicates with the digital interface board and analog interface board through the chassis backplane. The secondary DBF switching board implements digital switch matrix configuration, flexibly selecting digital beams to go through the digital interface board to the digital baseband, and flexibly selecting digital beams to go through the analog interface board to the test instrument for beam performance testing. The digital interface board and digital baseband communicate via digital fiber optic connection. The secondary DBF analog interface board performs digital-to-analog or analog-to-digital conversion of the beam signals, connecting to the test instrument via coaxial cable for observation and testing. The high-speed data fiber optic communication protocol between the secondary DBF boards or backplane, and between the secondary DBF digital interface board and the digital baseband, is also the high-speed serial communication Auraro protocol or 204B protocol.

[0081] Specifically, the second-level board includes an optical communication module group, a signal processing FPGA connected to the optical communication module group, and a chassis backplane and DSP connected to the signal processing FPGA respectively.

[0082] The optical communication module group is used to receive and converge the primary beamforming digital downlink signal sent by the primary DBF board to obtain the secondary beamforming digital downlink signal. The optical communication module group includes several optical communication modules. Taking an optical communication module group with four optical communication sub-modules as an example, these four modules represent one secondary board that can communicate with four primary DBF boards. The control chip DSP can be a TI TMS320C66XX series or TMS320C64XX series DSP chip, and the digital beamforming large-scale FPGA chip can be a Xilinx Virtex-7 series or Virtex UltraScale series FPGA chip.

[0083] The signal processing FPGA is used to receive the digital downlink multi-beam signal output from the optical communication module group, and at the same time output the digital uplink multi-beam signal to the optical communication module group.

[0084] The chassis backplane is used to output the digital downlink multibeam signal from the signal processing FPGA to the third-level board.

[0085] The DSP is used to output control information to the signal processing FPGA and receive status information reported by the signal processing FPGA.

[0086] Specifically, the third-level board includes a signal processing FPGA, and a chassis backplane group and an optical communication module group that are respectively connected to the signal processing FPGA;

[0087] The signal processing FPGA is used to aggregate the digital downlink multi-beam signals sent by the chassis backplane group and transmit them to the optical communication module group, while simultaneously distributing the digital uplink multi-beam signals sent by the optical communication module group to the chassis backplane group. The chassis backplane group comprises several chassis backplanes, and the optical communication module group comprises several optical communication modules. The signal processing FPGA implements the aggregation of downlink received multi-beam signals and the distribution of uplink transmitted multi-beam signals. The digital beamforming chip FPGA can be a Xilinx Virtex-7 series or Virtex UltraScale series FPGA chip.

[0088] Specifically, the DBF switching board includes an optical communication module group, a signal processing FPGA, a chassis backplane, and a DSP;

[0089] The optical communication module group is used to receive the third-level beamforming digital downlink signal sent by the third-level board, and at the same time send digital uplink multi-beam signals to the third-level board; the optical communication module group includes several optical communication modules.

[0090] The signal processing FPGA is used to receive the digital downlink multi-beam signal output from the optical communication module group and output the digital uplink multi-beam signal to the optical communication module group; it is used to implement the configuration of the digital switch matrix, flexibly select the digital downlink beam signal to the digital baseband through the digital interface board, and flexibly select the baseband digital uplink signal from the digital interface board to be transmitted to the third-level board through the optical module; it is also flexibly select the digital downlink beam signal to the test instrument through the analog interface board for beam performance testing.

[0091] The chassis backplane is used to output the digital downlink multibeam signal from the signal processing FPGA to the digital interface board and the analog interface board, respectively.

[0092] The DSP is used to output control information to the signal processing FPGA and receive status information reported by the signal processing FPGA.

[0093] Specifically, the digital interface board includes a chassis backplane, a signal processing FPGA, and an optical communication module group;

[0094] The signal processing FPGA is used to transmit the digital downlink multi-beam signal sent from the chassis backplane to the optical communication module group, and at the same time output the digital uplink multi-beam signal received from the optical communication module group to the chassis backplane; wherein, the optical communication module group includes several optical communication modules;

[0095] The analog interface board includes a chassis backplane, a signal processing FPGA, and a digital-to-analog converter module;

[0096] The signal processing FPGA is used to transmit the digital downlink multibeam signal sent from the chassis backplane to the digital-to-analog converter module;

[0097] The digital-to-analog converter module is used to convert the received digital downlink multibeam signal into an analog signal and transmit it to the test instrument.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A hardware-implemented network architecture for all-digital large-scale phased array multibeamforming, characterized in that, include: The sub-array, secondary DBF board, and DBF switching board are connected in sequence, and also include a digital interface board and an analog interface board respectively connected to the DBF switching board; The subarray includes multiple TR components and primary DBF boards connected to the multiple TR components respectively; wherein, the TR components are used to implement downlink received signal filtering, low-noise amplification, analog downconversion, and analog-to-digital conversion; and to implement uplink transmitted signal digital-to-analog conversion, analog upconversion, and power amplification; The primary DBF board is used to perform digital multi-beamforming on the digital signals sent by multiple TR components to obtain primary beamforming digital downlink signals, and is also used to send primary beamforming digital uplink signals to multiple TR components. The secondary DBF board is connected to the primary DBF board and is used to process the received primary digital multibeamforming signal to obtain the third-level beamforming digital downlink signal and beamforming analog signal. It is also used to send the baseband digital uplink signal to the primary DBF board. The secondary DBF board includes a second-level board, a third-level board, a DBF switching board connected in sequence, and a digital interface board and an analog interface board respectively connected to the DBF switching board; The second-level board is connected to the primary DBF board and is used to converge the primary beamforming digital downlink signal sent by the primary DBF board to obtain the second-level beamforming digital downlink signal, and then send the second-level beamforming digital downlink signal to the third-level board. The third-level board is used to converge the received second-level beamforming digital downlink signal to obtain the third-level beamforming digital downlink signal, and send the formed third-level beamforming digital downlink signal to the DBF switching board; at the same time, it sends the formed third-level beamforming digital uplink signal to the second-level board. The DBF switching board is used to send the received third-level beamforming digital downlink signal to the digital interface board and the analog interface board respectively, and at the same time send the baseband digital uplink signal received from the digital interface board to the third-level board. The digital interface board is used to send the received baseband digital uplink signal to the DBF switching board, and at the same time send the received third-level beamforming digital downlink signal to the digital baseband. The analog interface board is used to receive the third-level beamforming digital downlink signal and convert it into a beamforming analog signal; The primary DBF board includes a control chip FPGA, a signal processing FPGA, and an optical communication module connected in sequence. The control chip FPGA is used to output control information to the signal processing FPGA and receive status information sent by the signal processing FPGA; wherein, the control information includes beam switching, rotation selection, and master / standby selection, and the status information includes the temperature, voltage, clock, link status, and beam operating status of the signal processing FPGA; The signal processing FPGA is used to receive digital uplink multibeam signals sent by the optical communication module, and to send digital downlink multibeam signals to the optical communication module. The optical communication module is used to send downlink multi-beam optical output signals to the secondary DBF board, i.e., primary beamforming digital downlink signals, and simultaneously receive uplink multi-beam optical input signals sent by the secondary DBF board, i.e., second-stage beamforming digital uplink signals. The secondary DBF boards communicate with each other via the backplane of the secondary DBF chassis or via digital optical fiber and optical communication modules to achieve the convergence of downlink received digital multi-beamforming signals and the distribution of uplink transmitted digital multi-beam signals. The second-level board includes an optical communication module group, a signal processing FPGA connected to the optical communication module group, and a chassis backplane and DSP connected to the signal processing FPGA respectively. The optical communication module group is used to receive primary beamforming digital downlink signals sent by the primary DBF board and to receive secondary beamforming digital uplink signals sent to the primary DBF board; wherein, the optical communication module group includes several optical communication modules; The signal processing FPGA is used to receive the digital downlink multi-beam signal output from the optical communication module group, and at the same time output the digital uplink multi-beam signal to the optical communication module group. The chassis backplane is used to transmit the digital downlink multibeam signal output from the signal processing FPGA to the third-level board. The DSP is used to output control information to the signal processing FPGA and receive status information reported by the signal processing FPGA. The third-level board includes a signal processing FPGA, and a chassis backplane group and an optical communication module group respectively connected to the signal processing FPGA; The signal processing FPGA is used to aggregate the second-level digital downlink multi-beam signal transmitted from the chassis backplane group and send it to the optical communication module group. At the same time, it distributes the digital uplink multi-beam signal sent by the optical communication module group and transmits it to the chassis backplane group. The chassis backplane group includes several chassis backplanes, and the optical communication module group includes several optical communication modules.

2. The hardware implementation network architecture for all-digital large-scale phased array multibeamforming according to claim 1, characterized in that, It also includes a digital baseband connected to the digital interface board, and test instruments connected to the analog interface board; The digital baseband is used to send baseband digital uplink signals to the digital interface board and simultaneously receive third-level beamforming digital downlink signals sent by the digital interface board. The testing instrument is used to receive beamforming analog signals sent by the analog interface board.

3. The hardware implementation network architecture for all-digital large-scale phased array multibeamforming according to claim 1, characterized in that, The secondary DBF chassis is a VPX chassis, and each VPX chassis has M+1 slots, where M is an even number. The M / 2+1th slot communicates with the other slots via a backplane for high-speed data exchange.

4. The hardware implementation network architecture for all-digital large-scale phased array multibeamforming according to claim 1, characterized in that, The DBF switching board includes an optical communication module group, a signal processing FPGA, a chassis backplane, and a DSP. The optical communication module group is used to receive the third-level beamforming digital downlink signal sent by the third-level board, and at the same time send digital uplink multi-beam signals to the third-level board; the optical communication module group includes several optical communication modules. The signal processing FPGA is used to receive the digital downlink multi-beam signal output from the optical communication module group and output the digital uplink multi-beam signal to the optical communication module group; it is used to implement the configuration of the digital switch matrix, select the digital downlink beam signal to the digital baseband through the digital interface board, select the digital uplink signal from the digital baseband of the digital interface board to be transmitted to the third-level board through the optical module, and select the digital downlink beam signal to the test instrument through the analog interface board for beam performance testing. The chassis backplane is used to output the digital downlink multibeam signal from the signal processing FPGA to the digital interface board and the analog interface board, respectively. The DSP is used to output control information to the signal processing FPGA and receive status information reported by the signal processing FPGA.

5. The hardware implementation network architecture for all-digital large-scale phased array multibeamforming according to claim 4, characterized in that, The digital interface board includes a chassis backplane, a signal processing FPGA, and an optical communication module group; The signal processing FPGA is used to transmit the digital downlink multi-beam signal sent from the chassis backplane to the optical communication module group, and at the same time output the digital uplink multi-beam signal received from the optical communication module group to the chassis backplane; wherein, the optical communication module group includes several optical communication modules; The analog interface board includes a chassis backplane, a signal processing FPGA, and a digital-to-analog conversion module; The signal processing FPGA is used to transmit the digital downlink multibeam signal sent from the chassis backplane to the digital-to-analog converter module; The digital-to-analog converter module is used to convert the received digital downlink multibeam signal into an analog signal and transmit it to the test instrument.

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