Signal processing method and signal processing circuit

Abstract

The present disclosure provides a signal processing method and a signal processing circuit, which can be applied to the technical field of pulse neural network. The method comprises: in response to a received pulse signal, performing signal conversion on the pulse signal by using a plurality of delay units in a delay device to obtain a plurality of delay signals; for each delay signal, using a plurality of multiplexers to gate the delay signal based on a preset configuration signal to obtain a preset number of gating signals; determining a transformed amplitude corresponding to the delay signal according to the number of amplitudes corresponding to each gating signal; determining an amplitude value corresponding to the delay signal based on the transformed amplitude and a historical amplitude value; and determining a potential change state of a neuron cell body connected to a target synapse based on a plurality of amplitude values of the pulse signal to complete simulation of the potential change of the neuron, wherein the target synapse is a synapse acted on by the pulse signal.

Description

Technical Field

[0001] This disclosure relates to the field of spiking neural network technology, and in particular to a signal processing method and a signal processing circuit. Background Technology

[0002] A neuron is a specialized cell that receives impulse signals transmitted from its synapse via its cell body, causing changes in its membrane potential. To describe neuronal function, it is typically abstracted into a simplified mathematical model. Among related technologies, the Spike Response Model (SRM) explicitly and analytically describes the response to an input impulse. In the SRM, each impulse signal input to the neuron generates a response potential, which accumulates under the influence of its respective synaptic weights to form the postsynaptic membrane potential.

[0003] In realizing the concept disclosed herein, the inventors discovered at least the following problems in the related technology: the impulse response model requires delay processing of the impulse signal during the processing of the impulse signal. Since the delay processing operation is relatively complex, the power consumption is high, resulting in low efficiency in simulating the change of neuronal potential. Summary of the Invention

[0004] In view of the above problems, this disclosure provides signal processing methods, signal processing circuits, and electronic devices.

[0005] According to a first aspect of this disclosure, a signal processing method is provided, comprising: responding to a received pulse signal, performing signal conversion on the pulse signal using a plurality of delay units in a delay unit to obtain a plurality of delayed signals; for each of the delayed signals, selecting the delayed signal using a plurality of multiplexers based on a preset configuration signal to obtain a preset number of selection signals; determining a transformation amplitude corresponding to the delayed signal based on the number of amplitudes corresponding to each of the selected signals; determining an amplitude value corresponding to the delayed signal based on the transformation amplitude and a historical amplitude value, wherein the historical amplitude value is the amplitude value corresponding to a historical moment, and the time interval between the historical moment and the current moment is a preset time step; and determining the potential change state of a neuron cell body connected to a target synapse based on the plurality of amplitude values ​​of the pulse signal to simulate the potential change of the neuron, wherein the target synapse is the synapse acted upon by the pulse signal.

[0006] According to an embodiment of this disclosure, the aforementioned delay unit is composed of multiple cascaded inverters. The method of using multiple delay units in the delay unit to perform signal conversion on the pulse signal to obtain multiple delayed signals includes: determining a first delay unit and multiple second delay units based on the connection order of the multiple delay units in the delay unit; inputting the pulse signal into the first delay unit; sequentially performing level conversion on the pulse signal using the multiple inverters in the first delay unit to obtain a first delayed signal, wherein the size of the starting inverter and the ending inverter among the multiple inverters is larger than the size of the remaining inverters; and continuously performing level conversion on the first delayed signal using the multiple second delay units based on the connection order to obtain multiple second delayed signals.

[0007] According to embodiments of this disclosure, the above-mentioned selection of the delayed signal using multiple multiplexers based on a preset configuration signal to obtain a preset number of selection signals includes: for each multiplexer, determining multiple data signals input to the multiplexer based on the delayed signal or a logic signal, wherein the logic signal is obtained by connecting the multiplexer to ground; determining a control signal input to the multiplexer based on the preset configuration signal; and selecting the multiple data signals or the logic signal using the multiplexer based on the control signal to obtain the selection signals.

[0008] According to an embodiment of this disclosure, determining the transformed amplitude corresponding to the delayed signal based on the number of amplitudes corresponding to each of the above-mentioned gating signals includes: adding each of the above-mentioned gating signals bit by bit to obtain the above-mentioned preset number of amplitudes; assigning network types to the above-mentioned preset number of amplitudes to obtain the number of rising amplitudes corresponding to rising networks and the number of falling amplitudes corresponding to falling networks; and subtracting the number of rising amplitudes from the number of falling amplitudes to obtain the transformed amplitude.

[0009] According to embodiments of this disclosure, determining the potential change state of a neuron cell body connected to a target synapse based on multiple amplitude values ​​of the pulse signal includes: determining the weight of the target synapse; producting the weight with the amplitude value corresponding to the current moment to obtain a current response amplitude; summing the current response amplitude and historical response amplitudes to obtain a change amplitude, wherein the historical response amplitude is obtained by producting the historical amplitude values ​​corresponding to multiple historical moments with the weight and summing them sequentially; and determining the potential change state of the neuron cell body based on the change amplitude.

[0010] According to embodiments of this disclosure, determining the potential change state of the neuronal cell body based on the aforementioned change amplitude includes: determining the change amplitude of a plurality of remaining synapses connected to the neuronal cell body, wherein the remaining synapses are synapses other than the target synapse among the synapses connected to the neuronal cell body; summing the change amplitude of the target synapse and the change amplitude of the plurality of remaining synapses to obtain a target amplitude; determining the potential change state as a change in membrane potential when the target amplitude reaches a preset amplitude; and determining the potential change state as no change in membrane potential when the target amplitude does not reach the preset amplitude.

[0011] According to embodiments of this disclosure, the above method, wherein determining the amplitude value corresponding to the delayed signal based on the transformed amplitude value and the historical amplitude value, includes: summing the transformed amplitude value and the historical amplitude value to obtain the amplitude value corresponding to the delayed signal; and / or, after determining the amplitude value corresponding to the delayed signal based on the transformed amplitude value and the historical amplitude value, it further includes: converting the amplitude value into an amplitude output value of a preset byte, so as to determine the potential change state of the neuronal cell body connected to the target synapse based on the amplitude output value.

[0012] A second aspect of this disclosure provides a signal processing circuit, comprising: a delay unit, configured to, in response to a received pulse signal, perform signal conversion on the pulse signal using a plurality of delay units in the delay unit to obtain a plurality of delayed signals; a pulse response configuration module, connected to the delay unit, configured to, for each of the delayed signals, select the delayed signal using a plurality of multiplexers based on a preset configuration signal to obtain a preset number of selection signals; and a network module, including a rising network module and a falling network module, respectively connected to the pulse response configuration module, configured to, based on each of the selection signals... The corresponding number of amplitude values ​​determines the transformed amplitude corresponding to the aforementioned delayed signal; the accumulation module, connected to the aforementioned network module, is used to determine the amplitude value corresponding to the aforementioned delayed signal based on the aforementioned transformed amplitude value and historical amplitude value, wherein the aforementioned historical amplitude value is the amplitude value corresponding to a historical moment, and the time interval between the aforementioned historical moment and the current moment is a preset time step; wherein, the multiple amplitude values ​​in the aforementioned pulse signal are used to determine the potential change state of the neuron cell body connected to the target synapse, so as to complete the simulation of the neuron potential change, wherein the aforementioned target synapse is the synapse acted upon by the aforementioned pulse signal.

[0013] A third aspect of this disclosure provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the method described above.

[0014] According to the signal processing method, signal processing circuit, and electronic device provided in this disclosure, the processing efficiency of pulse signals is effectively improved by using a delay unit to delay the pulse signal and passing it through multiple delay units. Based on multiple amplitude values ​​of the pulse signal, the potential change state of the neuron cell body connected to the target synapse is determined, and the simulation of neuronal potential changes is completed, making the simulation process simpler, reducing power consumption, and improving simulation efficiency. Attached Figure Description

[0015] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 A flowchart illustrating a signal processing method according to an embodiment of the present disclosure is shown schematically.

[0017] Figure 2 A schematic diagram of a signal processing circuit according to an embodiment of the present disclosure is shown.

[0018] Figure 3 A schematic diagram of a delay circuit for a signal processing circuit according to an embodiment of the present disclosure is shown.

[0019] Figure 4 A schematic diagram of an accumulation module of a signal processing circuit according to an embodiment of the present disclosure is shown.

[0020] Figure 5 A schematic diagram of a signal processing circuit according to another embodiment of the present disclosure is shown.

[0021] Figure 6A The diagram schematically illustrates a simulation waveform of a hyperbolic response model of a signal processing circuit according to an embodiment of the present disclosure;

[0022] Figure 6B The following is a schematic diagram illustrating a simulation waveform of a ramp-up non-leaking model of a signal processing circuit according to an embodiment of the present disclosure;

[0023] Figure 6C The diagram schematically illustrates a simulation waveform of a piecewise linear model of a signal processing circuit according to an embodiment of the present disclosure;

[0024] Figure 7 A block diagram schematically illustrates an electronic device suitable for implementing a signal processing method according to an embodiment of the present disclosure. Detailed Implementation

[0025] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0027] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0028] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0029] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision, disclosure, and application of data (including but not limited to user personal information) comply with the provisions of relevant laws and regulations, necessary confidentiality measures have been taken, and they do not violate public order and good morals.

[0030] A neuron is a specialized cell with several dendrites and an axon on its cell body. The axon's tail branches into several nerve endings. Neurons transmit impulse signals through synapses, formed at the junctions of dendrites and axon nerve endings. The function and dynamics of biological neurons can be simply described as follows: the neuron's cell body receives impulse signals transmitted from the previous neuron via synapses, causing a change in its membrane potential. When the neuron's membrane potential exceeds its threshold, an action potential is generated that propagates along the axon and further acts on other neurons through the synapse, while its membrane potential returns to its initial state.

[0031] In related technologies, to describe the function of neurons, they are usually abstracted into simplified mathematical models. The Leak-Integrate-And-Fire (LIF) neuron model is widely used in Spiking Neural Networks (SNNs), achieving computational simplicity while maintaining the integrity of neuronal function. The Spike Response Model (SRM) describes the response to input impulse signals in an explicit analytical formula. In the SRM neuron model, each input impulse signal to the neuron generates a response potential, which accumulates under the influence of its respective synaptic weights to form the postsynaptic membrane potential.

[0032] Impulse response models require delay processing of impulse signals during impulse signal processing. Related technologies use shift registers composed of D flip-flops, which rely on clock driving, making the delay processing operation complex, resulting in high power consumption and low efficiency in simulating neuronal potential changes.

[0033] In view of the above, embodiments of this disclosure provide a signal processing method, a signal processing circuit, and an electronic device. The signal processing method includes: responding to a received pulse signal, performing signal conversion on the pulse signal using multiple delay units in a delay unit to obtain multiple delayed signals; for each delayed signal, using multiple multiplexers based on a preset configuration signal to select the delayed signal to obtain a preset number of selected signals; determining a transformed amplitude corresponding to the delayed signal based on the number of amplitudes corresponding to each selected signal; determining an amplitude value corresponding to the delayed signal based on the transformed amplitude and historical amplitude values, wherein the historical amplitude value is the amplitude value corresponding to a historical time, and the time interval between the historical time and the current time is a preset time step; and determining the potential change state of the neuronal cell body connected to a target synapse based on the multiple amplitude values ​​of the pulse signal to simulate the neuronal potential change, wherein the target synapse is the synapse affected by the pulse signal.

[0034] Figure 1 A flowchart illustrating a signal processing method according to an embodiment of the present disclosure is shown schematically.

[0035] like Figure 1 As shown, the signal processing method of this embodiment includes operations S110 to S150.

[0036] In operation S110, in response to the received pulse signal, the pulse signal is converted into multiple delayed signals by using multiple delay units in the delay unit.

[0037] In operation S120, for each delayed signal, multiple multiplexers are used to select the delayed signal based on a preset configuration signal to obtain a preset number of selected signals.

[0038] In operation S130, the transformed amplitude corresponding to the delay signal is determined based on the number of amplitudes corresponding to each gating signal.

[0039] In operation S140, the amplitude value corresponding to the delayed signal is determined based on the transformed amplitude and the historical amplitude value. The historical amplitude value is the amplitude value corresponding to the historical moment, and the time interval between the historical moment and the current moment is a preset time step.

[0040] In operation S150, based on multiple amplitude values ​​of the pulse signal, the potential change state of the neuron cell body connected to the target synapse is determined to complete the simulation of the neuron potential change, wherein the target synapse is the synapse acted upon by the pulse signal.

[0041] According to embodiments of this disclosure, multiple delay units in a delay unit are used to convert a pulse signal into a 16-bit (bit, a unit of data measurement) delayed signal. Specifically, after the input pulse signal, different delays are generated in 16 time steps, thereby obtaining 16 delayed signals, which are 16 binary numbers. Specifically, each time step can be 1 nanosecond.

[0042] According to embodiments of this disclosure, a preset configuration signal is obtained, wherein the preset configuration signal may be a 3-bit signal. Both the preset configuration signal and the delay signal are input into multiple multiplexers. Based on the preset configuration signal, the multiplexers select the delay signal to determine which of the three input signals of the multiplexer will be selected as the output of the multiplexer, i.e., the selection signal. Specifically, two 3-bit preset configuration signals and one 16-bit delay signal are input into multiple multiplexers, outputting two 5-bit selection signals. The preset number can be set to two and can be adjusted based on response requirements.

[0043] According to embodiments of this disclosure, the number of corresponding amplitude values ​​is calculated based on the value of each bit in the specific binary number of the gating signal. The transformed amplitude corresponding to the delayed signal is determined based on the number of amplitude values ​​for each gating signal, wherein each amplitude value can represent either the number of rising amplitude values ​​or the number of falling amplitude values. The changed amplitude is determined based on the number of rising amplitude values ​​and the number of falling amplitude values. Specifically, two amplitude values ​​are determined based on two gating signals, one representing the number of rising amplitude values ​​and the other representing the number of falling amplitude values. These two values ​​are added or subtracted to obtain the changed amplitude.

[0044] According to embodiments of this disclosure, historical amplitude values ​​are obtained, wherein the historical amplitude value corresponds to the amplitude value at a historical moment, and the time interval between the historical moment and the current moment is a preset time step. For example, assuming the preset time step is 1 nanosecond, if the current moment is 6 nanoseconds, then the historical moment is 5 nanoseconds. The transformed amplitude value and the historical amplitude value are summed to determine the amplitude value corresponding to the delayed signal, thus realizing the superposition of the pulse signal response.

[0045] According to embodiments of this disclosure, the potential change state of the neuron cell body connected to a target synapse is determined based on multiple amplitude values ​​of a pulse signal, wherein the target synapse is the synapse acted upon by the pulse signal. The neuron cell body is connected to multiple synapses, and based on the amplitude values ​​fed back to the neuron cell body from these multiple synapses, it is determined whether the neuron's membrane potential has changed at the current moment, and further, an action potential is generated to simulate the neuron's potential change.

[0046] According to embodiments of this disclosure, by using a delay unit to delay the pulse signal, the processing efficiency of the pulse signal is effectively improved through multiple delay units. Based on multiple amplitude values ​​of the pulse signal, the potential change state of the neuron cell body connected to the target synapse is determined, thus completing the simulation of the neuron's potential change. This simplifies the simulation process, reduces power consumption, and improves simulation efficiency.

[0047] According to embodiments of this disclosure, the delay unit is composed of multiple cascaded inverters. Utilizing the multiple delay units in the delay unit to perform signal conversion on the pulse signal to obtain multiple delayed signals can include the following operations:

[0048] Based on the connection order of multiple delay units in the delay unit, a first delay unit and multiple second delay units are determined; a pulse signal is input into the first delay unit, and multiple inverters in the first delay unit are used to sequentially perform level conversion on the pulse signal to obtain a first delayed signal, wherein the size of the starting inverter and the ending inverter among the multiple inverters is larger than the size of the remaining inverters; based on the connection order, multiple second delay units are used to continuously perform level conversion on the first delayed signal to obtain multiple second delayed signals.

[0049] According to embodiments of this disclosure, the connection order of multiple delay units in a delay unit is determined. Specifically, the delay unit includes 16 delay units, each of which is connected sequentially. A first delay unit and multiple second delay units are determined, wherein the first delay unit is the first delay unit among the multiple delay units, and the second delay units are the remaining delay units in the delay unit excluding the first delay unit.

[0050] According to embodiments of this disclosure, a pulse signal is input into a first delay unit for initial delay. Specifically, the delay unit includes multiple inverters, where the size of the starting and ending inverters is larger than the size of the remaining inverters, thus resulting in a slower high-to-low level transition and a longer delay. The first delayed signal output from the first delay unit is input into a second delay unit connected to the first delay unit for continuous level conversion, thereby obtaining multiple second delayed signals.

[0051] According to embodiments of this disclosure, the delay unit includes 16 delay units, each containing 4 inverters. Each delay unit continuously delays the pulse signal, and each outputs a 16-bit delay signal to complete the delay of the pulse signal. Compared to implementation using a 16-bit shift register composed of 16 D flip-flops, this eliminates the dependence on a clock, thus reducing power consumption. Simultaneously, the area is reduced to a certain extent, enabling self-driven generation of membrane potential response.

[0052] According to embodiments of this disclosure, using multiple multiplexers to select a delayed signal based on a preset configuration signal to obtain a preset number of selected signals may include the following operations:

[0053] For each multiplexer, multiple data signals are determined based on a delay signal or a logic signal, wherein the logic signal is obtained by connecting the multiplexer to ground; the control signal is determined based on a preset configuration signal; and the multiplexer is used to select multiple data signals or logic signals based on the control signal to obtain a selection signal.

[0054] According to embodiments of this disclosure, multiple multiplexers are divided into two or more units, specifically including an ascending configuration unit and a descending configuration unit, each of which includes multiple multiplexers. Specifically, eight multiplexers can be evenly distributed across the ascending and descending configuration units.

[0055] According to embodiments of this disclosure, each multiplexer input includes three data signals and one control signal. The three data signals input to the multiplexer can be certain bits of a delayed signal or logic signals. The logic signal is obtained by connecting the multiplexer to ground, specifically by connecting the multiplexer to logic 0 (GND). The control signal input to the multiplexer is determined from two preset configuration signals.

[0056] According to embodiments of this disclosure, a multiplexer is used to select multiple data signals or logic signals based on control signals, wherein both the rising configuration unit and the falling configuration unit output a gating signal to facilitate the calculation of amplitude fluctuation.

[0057] According to embodiments of this disclosure, determining the transformed amplitude corresponding to the delayed signal based on the number of amplitudes corresponding to each gating signal may include the following operations:

[0058] Each gating signal is summed bit by bit to obtain a preset number of amplitude values; the preset number of amplitude values ​​are assigned to network types to obtain the number of rising amplitude values ​​corresponding to the rising network and the number of falling amplitude values ​​corresponding to the falling network; the difference between the number of rising amplitude values ​​and the number of falling amplitude values ​​is used to obtain the transformed amplitude.

[0059] According to embodiments of this disclosure, the number of amplitude values ​​is calculated based on the value of each bit in the specific binary number of the 5-bit strobe signal. Each strobe signal is then summed bit-by-bit to obtain a preset number of amplitude values. For example, summing the bits of strobe signal 10001 yields a number of amplitude values ​​of 2.

[0060] According to embodiments of this disclosure, the number of amplitude values ​​is assigned by network type. If the strobe signal is output by the rising configuration unit, the number of amplitude values ​​of the strobe signal is determined to be the number of rising amplitude values ​​corresponding to the rising network. If the strobe signal is output by the falling configuration unit, the number of amplitude values ​​of the strobe signal is determined to be the number of falling amplitude values ​​corresponding to the falling network.

[0061] According to embodiments of this disclosure, the difference between the number of rising amplitudes and the number of falling amplitudes is used to obtain the transformed amplitude. For example, if the number of rising amplitudes is 3 and the number of falling amplitudes is 2, then the transformed amplitude is determined to be 1. The fluctuation of the pulse signal response at the current time step is obtained by calculating the transformed amplitude.

[0062] According to embodiments of this disclosure, determining the potential change state of a neuron cell body connected to a target synapse based on multiple amplitude values ​​of a pulse signal may include the following operations:

[0063] Determine the weights of the target synapse; product the weights with the amplitude value corresponding to the current moment to obtain the current response amplitude; sum the current response amplitude and the historical response amplitude to obtain the change amplitude, where the historical response amplitude is obtained by producting the historical amplitude values ​​corresponding to multiple historical moments with the weights and summing them sequentially; determine the potential change state of the neuron cell body based on the change amplitude.

[0064] According to embodiments of this disclosure, each synapse connected to the neuron cell body has a corresponding weight. The current response amplitude of the target synapse is obtained by multiplying the weight by the amplitude value at the current moment. The change amplitude is obtained by summing the current response amplitude and historical response amplitudes, thus achieving the superposition of responses. The historical response amplitude is obtained by multiplying the historical amplitude values ​​corresponding to multiple historical moments by the weights and summing them sequentially. Multiplying the weights and amplitude values ​​makes the calculation of the current amplitude of the synapse more reasonable and accurate.

[0065] According to embodiments of this disclosure, determining the amplitude value corresponding to the delayed signal based on the transformed amplitude and historical amplitude values ​​may include the following operations:

[0066] The amplitude value corresponding to the delayed signal is obtained by summing the transformed amplitude value and the historical amplitude value.

[0067] According to an embodiment of this disclosure, assuming the current time is 3 nanoseconds, the historical response amplitude is obtained by summing the response amplitude calculated at 1 nanosecond and the response amplitude calculated at 2 nanoseconds. The response amplitude at 1 nanosecond is obtained by productting the weights with the amplitude corresponding to 1 nanosecond, and the response amplitude at 2 nanoseconds is obtained by productting the weights with the amplitude corresponding to 2 nanoseconds.

[0068] According to embodiments of this disclosure, determining the potential change state of a neuron cell body based on the magnitude of the change can include the following operations:

[0069] The amplitude of the change in multiple residual synapses connected to the neuron cell body is determined, where residual synapses are those other than the target synapse connected to the neuron cell body. The amplitude of the change in the target synapse and the amplitude of the change in multiple residual synapses are summed to obtain the target amplitude. If the target amplitude reaches the preset amplitude, the potential change state is determined to be a change in membrane potential. If the target amplitude does not reach the preset amplitude, the potential change state is determined to be no change in membrane potential.

[0070] According to embodiments of this disclosure, the amplitude changes of all synapses connected to the neuron cell body are summed to obtain the target amplitude of the neuron cell body. If the target amplitude reaches a preset amplitude, the potential change state is determined to be a change in membrane potential, generating an action potential. If the target amplitude does not reach the preset amplitude, the potential change state is determined to be no change in membrane potential, and the amplitudes continue to be summed until a change in membrane potential occurs, thereby completing the simulation of neuronal potential changes.

[0071] According to embodiments of this disclosure, after determining the amplitude value corresponding to the delayed signal based on the transformed amplitude and historical amplitude values, the following operations may also be included:

[0072] The amplitude value is converted into an amplitude output value of a preset byte, so that the potential change state of the neuron cell body connected to the target synapse can be determined based on the amplitude output value.

[0073] According to embodiments of this disclosure, the amplitude value is first converted into 3-bit data, and then the 3-bit amplitude value is converted into a 6-bit amplitude output value. Specifically, this conversion can be performed using a decoder. A reset signal is received during the conversion process. When the reset signal indicates that the amplitude output value can be output, the amplitude output value is output. When the reset signal indicates that the amplitude output value cannot be output, the amplitude output value is not output. This byte-level conversion of the amplitude value facilitates the subsequent generation of the response function.

[0074] Based on the above signal processing method, this disclosure also provides a signal processing circuit. The following will be combined with... Figure 2 Provide a detailed description of the circuit.

[0075] Figure 2 A schematic diagram of a signal processing circuit according to an embodiment of the present disclosure is shown.

[0076] like Figure 2 As shown, the signal processing circuit 200 in this embodiment includes a delay unit 210, an impulse response configuration module 220, a network module 230, and an accumulation module 240.

[0077] The delay unit 210 is used to respond to a received pulse signal by performing signal conversion on the pulse signal using multiple delay units in the delay unit to obtain multiple delayed signals. In one embodiment, the delay unit 210 can be used to perform the operation S110 described above, which will not be repeated here.

[0078] The impulse response configuration module 220, connected to the delay unit, is used to select each delayed signal using multiple multiplexers based on a preset configuration signal, thereby obtaining a preset number of selected signals. In one embodiment, the impulse response configuration module 320 can be used to perform the operation S120 described above, which will not be repeated here.

[0079] Network module 230, including a rising network module and a falling network module, is connected to the impulse response configuration module and is used to determine the transformed amplitude corresponding to the delayed signal based on the number of amplitudes corresponding to each gating signal. In one embodiment, network module 230 can be used to perform the operation S130 described above, which will not be repeated here.

[0080] The accumulation module 240, connected to the network module, is used to determine the amplitude value corresponding to the delayed signal based on the transformed amplitude and the historical amplitude value, wherein the historical amplitude value is the amplitude value corresponding to the historical time, and the time interval between the historical time and the current time is a preset time step. In one embodiment, the accumulation module 240 can be used to perform the operation S140 described above, which will not be repeated here.

[0081] The pulse signal contains multiple amplitude values ​​used to determine the potential change state of the neuron cell body connected to the target synapse, thereby simulating the neuronal potential change. The target synapse is the synapse affected by the pulse signal. In one embodiment, the operation is the same as that described above in step S140, and will not be repeated here.

[0082] According to embodiments of this disclosure, a pulse signal (Spike) is input to a signal processing circuit (SRM Module) 200, and a delay unit (delay) 210 is used to delay the pulse signal to generate multiple delayed signals. For each delayed signal, the delayed signal and a preset configuration signal (Config) are input to a pulse response configuration module (SRM Config) 220 for signal gating, and two gating signals are output.

[0083] According to an embodiment of this disclosure, two gating signals are input into network module 230, wherein network module 230 consists of an up network module 2301 and a down network module 2302, and the two gating signals are respectively input into the up network module 2301 and the down network module 2302. The up network module 2301 outputs the number of up amplitudes, and the down network module 2302 outputs the number of down amplitudes.

[0084] According to embodiments of this disclosure, the number of rising amplitude values ​​and the number of falling amplitude values ​​are input into the accumulation module 240, and the amplitude value corresponding to the delayed signal is output. Multiple amplitude values ​​in the pulse signal are used to determine the potential change state of the neuron cell body connected to the target synapse, thereby simulating the neuronal potential change. The target synapse is the synapse affected by the pulse signal.

[0085] According to embodiments of this disclosure, by using a delay unit to delay the pulse signal, the processing efficiency of the pulse signal is effectively improved through multiple delay units. Based on multiple amplitude values ​​of the pulse signal, the potential change state of the neuron cell body connected to the target synapse is determined, thus completing the simulation of the neuron's potential change. This simplifies the simulation process, reduces power consumption, and improves simulation efficiency.

[0086] Figure 3 A schematic diagram of a delay circuit for a signal processing circuit according to an embodiment of the present disclosure is shown.

[0087] According to an embodiment of the present disclosure, the delay unit 210 includes a plurality of delay units, wherein each delay unit is composed of a plurality of inverters cascaded together, and the size of the starting inverter and the ending inverter among the plurality of inverters is larger than the size of the remaining inverters.

[0088] According to embodiments of this disclosure, such as Figure 3As shown, the delay unit includes multiple delay units (τ). An input pulse signal is fed into the delay unit, and each delay unit sequentially processes it with a delay signal. Specifically, each delay unit consists of four cascaded inverters.

[0089] According to embodiments of this disclosure, the impulse response configuration module 220 includes a rising configuration unit and a falling configuration unit, wherein both the rising configuration unit and the falling configuration unit include multiple multiplexers.

[0090] Figure 4 A schematic diagram of an accumulation module of a signal processing circuit according to an embodiment of the present disclosure is shown.

[0091] According to embodiments of this disclosure, the accumulation module includes a subtractor 401, an adder 402, and a summing submodule 403. The number of rising amplitudes and falling amplitudes are input to the subtractor 401 to calculate the transformed amplitude. The adder 402 sums the transformed amplitude and historical amplitude values, and outputs the calculated value to the summing submodule 403 for subsequent response superposition. The summing submodule 403 outputs the amplitude value corresponding to the final delayed signal.

[0092] Figure 5 A schematic diagram of a signal processing circuit according to another embodiment of the present disclosure is shown.

[0093] According to embodiments of the present disclosure, the signal processing circuit 200 further includes a decoder 250 for converting the amplitude value into an amplitude output value of a preset byte, so as to determine the potential change state of the neuronal cell body connected to the target synapse based on the amplitude output value.

[0094] According to embodiments of this disclosure, an input pulse signal is fed into a signal processing circuit 200, where a delay unit 210, a pulse response configuration module 220, a network module 230, and an accumulation module 240 process the pulse signal to obtain an amplitude value. Multiple amplitude values ​​and a reset signal (EN) are then input into a decoder 250, which outputs a response function.

[0095] Figure 6A The diagram schematically illustrates a simulation waveform of a hyperbolic response model of a signal processing circuit according to an embodiment of the present disclosure.

[0096] Figure 6B The diagram schematically illustrates a simulation waveform of a ramp-up leak-free model of a signal processing circuit according to an embodiment of the present disclosure.

[0097] Figure 6C The diagram schematically illustrates a simulation waveform of a piecewise linear model of a signal processing circuit according to an embodiment of the present disclosure.

[0098] According to embodiments of this disclosure, the signal processing circuit was simulated as a whole. The signal processing circuit can generate different impulse response models by setting different preset configuration signals to meet the needs of different application scenarios and spiking neural networks of varying complexity. Figure 6A , Figure 6B and Figure 6C Simulation results for several typical impulse response models obtained under different preset signal configurations are presented. Specifically, the maximum time parameter in the fan-out network used to generate the discrete impulse response function is selected as 16.

[0099] According to embodiments of this disclosure, such as Figure 6A As shown, when the preset configuration signals are "010" and "010", the simulated response function corresponding to the discrete hyperbolic response model (Biexponential) in the figure can be obtained. In the hyperbolic response model, the horizontal axis represents time, and the vertical axis represents amplitude. The horizontal axis of the simulated response function is also time, and the vertical axis represents the corresponding output amplitude value (SRM_OUT).

[0100] According to embodiments of this disclosure, such as Figure 6B As shown, when the preset configuration signals are "100" and "010", the simulation response function corresponding to the ramp-up leak-proof model (Linear SRM) in the figure can be obtained. In the ramp-up leak-proof model, the horizontal axis represents time, and the vertical axis represents amplitude. The horizontal axis of the simulation response function is also time, and the vertical axis represents the corresponding output amplitude value (SRM_OUT).

[0101] According to embodiments of this disclosure, such as Figure 6C As shown, when the preset configuration signals are "100" and "010", the simulation response function corresponding to the discrete piecewise linear model in the ramp-up leak-proof model can be obtained. In the piecewise linear model, the horizontal axis represents time, and the vertical axis represents amplitude. The horizontal axis of the simulation response function is also time, and the vertical axis represents the corresponding output amplitude value (SRM_OUT).

[0102] According to embodiments of this disclosure, the power consumption of the signal processing circuit as a whole was evaluated using Cadence Virtuoso (a complete suite of EDA tools for integrated circuit design), and its energy consumption for a single impulse response was reduced by 57.4% compared to an SRM neuron using a D flip-flop.

[0103] According to embodiments of this disclosure, at least one of the delay unit 310, impulse response configuration module 320, network module 330, and accumulator module 340 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), programmable logic array (PLA), system-on-a-chip, system-on-a-substrate, system-on-package, application-specific integrated circuit (ASIC), or any other reasonable method of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three methods. Alternatively, at least one of the delay unit 310, impulse response configuration module 320, network module 330, and accumulator module 340 can be at least partially implemented as a computer program module, which, when run, can perform corresponding functions.

[0104] Figure 7 A block diagram schematically illustrates an electronic device suitable for implementing a signal processing method according to an embodiment of the present disclosure.

[0105] like Figure 7 As shown, an electronic device 700 according to an embodiment of this disclosure includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a random access memory (RAM) 702. The electronic device 700 may also include an input / output (I / O) interface 704, which is also connected to a bus 703.

[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0107] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0108] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A signal processing method, comprising: In response to a received pulse signal, the pulse signal is converted using multiple delay units in the delay unit to obtain multiple delayed signals; For each of the delayed signals, multiple multiplexers are used to select the delayed signals based on a preset configuration signal to obtain a preset number of selection signals; The transformed amplitude corresponding to the delayed signal is determined based on the number of amplitudes corresponding to each of the gating signals; The amplitude value corresponding to the delayed signal is determined based on the transformed amplitude and the historical amplitude value, wherein the historical amplitude value is the amplitude value corresponding to the historical moment, and the time interval between the historical moment and the current moment is a preset time step; Based on multiple amplitude values ​​of the pulse signal, the potential change state of the neuron cell body connected to the target synapse is determined to simulate the potential change of the neuron, wherein the target synapse is the synapse affected by the pulse signal; The step of determining the transformed amplitude corresponding to the delayed signal based on the number of amplitudes corresponding to each of the gating signals includes: Each of the gating signals is added bit by bit to obtain the preset number of amplitude values; the preset number of amplitude values ​​are assigned to network types to obtain the number of rising amplitude values ​​corresponding to the rising network and the number of falling amplitude values ​​corresponding to the falling network; the difference between the number of rising amplitude values ​​and the number of falling amplitude values ​​is used to obtain the transformed amplitude. Determining the amplitude value corresponding to the delayed signal based on the transformed amplitude value and the historical amplitude value includes: summing the transformed amplitude value and the historical amplitude value to obtain the amplitude value corresponding to the delayed signal.

2. The method according to claim 1, wherein, The delay unit is composed of multiple cascaded inverters. The pulse signal is converted using the multiple delay units in the delay unit to obtain multiple delayed signals, including: Based on the connection order of the multiple delay units in the delay unit, a first delay unit and multiple second delay units are determined; The pulse signal is input into the first delay unit, and the pulse signal is sequentially level-converted using multiple inverters in the first delay unit to obtain the first delay signal. The size of the starting inverter and the ending inverter among the multiple inverters is larger than the size of the remaining inverters. Based on the connection sequence, multiple second delay units are used to continuously perform level conversion on the first delay signal to obtain multiple second delay signals.

3. The method according to claim 1, wherein, The method of using multiple multiplexers to select the delayed signal based on a preset configuration signal to obtain a preset number of selection signals includes: For each of the multiplexers, based on the delay signal or the logic signal, multiple data signals are determined to be input to the multiplexer, wherein the logic signal is obtained by connecting the multiplexer to ground; The control signal input to the multiplexer is determined based on the preset configuration signal; Based on the control signal, the multiplexer is used to select multiple data signals or logic signals to obtain the selection signal.

4. The method according to claim 1, wherein, Determining the potential change state of the neuronal cell body connected to the target synapse based on multiple amplitude values ​​of the pulse signal includes: Determine the weights of the target synapse; The current response amplitude is obtained by multiplying the weights and the amplitude value corresponding to the current moment. The change amplitude is obtained by summing the current response amplitude and the historical response amplitude, wherein the historical response amplitude is obtained by producting the weight with the historical amplitude values ​​corresponding to multiple historical moments and summing them sequentially; The potential change state of the neuron cell body is determined based on the magnitude of the change.

5. The method according to claim 1, wherein, Determining the potential change state of the neuronal cell body based on the magnitude of the change includes: Determine the variation amplitude of multiple remaining synapses connected to the neuron cell body, wherein the remaining synapses are synapses connected to the neuron cell body other than the target synapse; The target amplitude is obtained by summing the change amplitude of the target synapse and the change amplitude of the multiple remaining synapses; When the target amplitude reaches the preset amplitude, the potential change state is determined to be a change in membrane potential; If the target amplitude does not reach the preset amplitude, the potential change state is determined to be that the membrane potential has not changed.

6. The method according to claim 1, wherein, After determining the amplitude value corresponding to the delayed signal based on the transformed amplitude and the historical amplitude value, the method further includes: The amplitude value is converted into an amplitude output value of a preset byte, so that the potential change state of the neuron cell body connected to the target synapse can be determined based on the amplitude output value.

7. A signal processing circuit, comprising: A delay unit is used to respond to a received pulse signal by using multiple delay units in the delay unit to convert the pulse signal into multiple delayed signals. An impulse response configuration module, connected to the delay unit, is used to select each delay signal based on a preset configuration signal using multiple multiplexers to obtain a preset number of selection signals. The network module includes a rising network module and a falling network module, which are respectively connected to the impulse response configuration module, and are used to determine the transformation amplitude corresponding to the delay signal based on the number of amplitudes corresponding to each of the gating signals; An accumulation module, connected to the network module, is used to determine the amplitude value corresponding to the delayed signal based on the transformed amplitude value and the historical amplitude value, wherein the historical amplitude value is the amplitude value corresponding to a historical moment, and the time interval between the historical moment and the current moment is a preset time step; The pulse signal contains multiple amplitude values ​​used to determine the potential change state of the neuron cell body connected to the target synapse, so as to simulate the potential change of the neuron. The target synapse is the synapse to which the pulse signal acts. The network module is further configured to: add each of the gating signals bit by bit to obtain the preset number of amplitude values; assign network types to the preset number of amplitude values ​​to obtain the number of rising amplitude values ​​corresponding to the rising network and the number of falling amplitude values ​​corresponding to the falling network; and subtract the number of rising amplitude values ​​from the number of falling amplitude values ​​to obtain the transformed amplitude. The accumulation module is further used to sum the transformed amplitude and the historical amplitude to obtain the amplitude value corresponding to the delayed signal.

8. The circuit according to claim 7, wherein, The delay unit includes multiple delay units, wherein each delay unit is composed of multiple inverters cascaded together, and the size of the starting inverter and the ending inverter among the multiple inverters is larger than the size of the remaining inverters.

9. The circuit according to claim 7, further comprising: A decoder is used to convert the amplitude value into an amplitude output value of a preset byte, so as to determine the potential change state of the neuron cell body connected to the target synapse based on the amplitude output value; The impulse response configuration module includes a rising configuration unit and a falling configuration unit, wherein both the rising configuration unit and the falling configuration unit include multiple multiplexers.

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