Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, a capacitor structure, a support structure, and an auxiliary layer. The capacitor structure is disposed on the substrate and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. The support structure is disposed between adjacent columnar bottom electrodes and includes a first support layer and a second support layer disposed in sequence from bottom to top. The auxiliary layer is disposed only between each columnar bottom electrode and the support structure and directly contacts the first support layer, the second support layer, and sidewalls of the columnar bottom electrode. Thus, the adhesion between the columnar bottom electrode and the support structure is strengthened by the auxiliary layer, and stress buffering is provided, thereby obtaining a more stable and reliable structure and achieving a relatively optimized device performance.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high aggregation and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells arranged in an array to store information. Each memory cell can be composed of a transistor assembly and a capacitor assembly connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies or structures still need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] One objective of this invention is to provide a method for fabricating a semiconductor device. This method involves forming a sacrificial layer on the sidewall of the opening before forming the columnar bottom electrode to protect the sidewall of the columnar bottom electrode layer. In subsequent fabrication processes, the sacrificial layer is partially removed, forming an auxiliary layer located only between the columnar bottom electrode and the support structure. Thus, the formation of this auxiliary layer not only strengthens the adhesion and stress buffering between the metal (the columnar bottom electrode) and the dielectric (the support structure) materials, but also further increases the distance between the columnar bottom electrodes, thereby expanding the deposition space for the subsequently formed capacitor dielectric layer and top electrode layer. This allows the deposition process of the capacitor dielectric layer and the top electrode layer to proceed more smoothly, achieving a simplified fabrication process.

[0004] One objective of this invention is to provide a semiconductor device in which an auxiliary layer is disposed between a pillar-shaped bottom electrode and a support structure to enhance the adhesion between the pillar-shaped bottom electrode and the support structure, provide stress buffering, and thus jointly support the pillar-shaped bottom electrode. In this way, the semiconductor device can have a more stable and reliable structure and achieve relatively optimized device performance.

[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, a capacitor structure, a support structure, and an auxiliary layer. The capacitor structure is disposed on the substrate and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. The support structure is disposed between adjacent columnar bottom electrodes and includes a first support layer and a second support layer sequentially disposed from bottom to top. The auxiliary layer is sandwiched between each columnar bottom electrode and the support structure, and directly contacts the sidewalls of the first support layer, the second support layer, and the columnar bottom electrodes.

[0006] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: First, a substrate is provided, and a capacitor structure is formed on the substrate. The capacitor structure includes a plurality of pillar-shaped bottom electrodes, a capacitor dielectric layer, and a top electrode layer. Next, a support structure is formed between adjacent pillar-shaped bottom electrodes. The support structure includes a first support layer and a second support layer sequentially disposed from bottom to top. Then, an auxiliary layer is formed between each pillar-shaped bottom electrode and the support structure. The auxiliary layer directly contacts only the sidewalls of the first support layer, the second support layer, and the pillar-shaped bottom electrodes. Attached Figure Description

[0007] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 7 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention is provided, wherein:

[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device of the present invention after the memory node pads have been formed;

[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor device of the present invention after the support layer structure has been formed;

[0011] Figure 3 This is a schematic cross-sectional view of the semiconductor device of the present invention after the bottom electrode layer has been formed;

[0012] Figure 4 This is a schematic cross-sectional view of the semiconductor device of the present invention after the mask layer has been formed;

[0013] Figure 5 This is a schematic cross-sectional view of the semiconductor device of the present invention after the third support material layer has been removed;

[0014] Figure 6 This is a schematic cross-sectional view of the semiconductor device of the present invention after the support material layer has been removed; and

[0015] Figure 7 This is a cross-sectional view of the semiconductor device of the present invention after the capacitor structure has been formed.

[0016] Figure 8 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention is shown.

[0017] Figure 9 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention is shown.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 100 substrate

[0020] 101 Shallow Ditch Isolation

[0021] 103 Active Zone

[0022] 110 dielectric layer

[0023] 111 oxide layer

[0024] 113 Nitride Layer

[0025] 115 oxide layer

[0026] 120-bit line

[0027] 120a line contact

[0028] 121 semiconductor layer

[0029] 123 Barrier Layer

[0030] 125 conductive layer

[0031] 127 cap layer

[0032] 130 plug

[0033] 140 gap wall structure

[0034] 141 First gap wall

[0035] 143 Second gap wall

[0036] 145 Third gap wall

[0037] 150 dielectric layer

[0038] 151 and 551 storage node pads

[0039] 160 insulation layers

[0040] 170 support layer structure

[0041] 171 First Support Material Layer

[0042] 172 opening

[0043] 173 Second Support Material Layer

[0044] 175 Third Support Material Layer

[0045] 177 Fourth Support Material Layer

[0046] 179 Fifth Support Material Layer

[0047] 180 Sacrificial Layer

[0048] 181 auxiliary layer

[0049] 191 bottom electrode layer

[0050] 200 mask patterns

[0051] 270 support structure

[0052] 273 First Support Layer

[0053] 277 Second Support Layer

[0054] 290, 390, 590 capacitor structures

[0055] 291, 591 columnar bottom electrodes

[0056] 293, 393, 593 capacitor dielectric layer

[0057] 295 top electrode layers

[0058] 300, 400, 500 semiconductor devices

[0059] G1 gap

[0060] R1, R2, R3 grooves Detailed Implementation

[0061] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0062] Please refer to Figures 1 to 7 The illustration shows the steps of a method for fabricating a semiconductor device 300 according to the first embodiment of the present invention. First, as... Figure 1As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate. At least one insulating region, such as a shallow trench isolation (STI) 101, is formed within the substrate 100. Multiple active areas (AA) 103 are defined on the substrate 100, so that, from a top view (not shown), the shallow trench isolation 101 surrounds all the active areas 103. In one embodiment, the shallow trench isolation 101 is formed, for example, by first etching multiple trenches (not shown) in the substrate 100, and then filling the trenches with an insulating material (e.g., silicon oxide or silicon oxynitride, etc.) to form a shallow trench isolation 101 with a surface flush with the top surface of the substrate 100, but this is not a limitation.

[0063] Next, a dielectric layer 110 is formed on the substrate 100. The dielectric layer 110 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure consisting of oxide layer 111, nitride layer 113, and oxide layer 115 stacked sequentially from bottom to top, but is not limited thereto. It should be noted that before forming the dielectric layer 110, a plurality of buried gates (not shown) are also formed within the substrate 100, such that the dielectric layer 110 covers the top surface of the buried gates. The buried gates extend parallel to each other along a direction (e.g., the x-direction, not shown) to serve as buried word lines (BWLs, not shown) of the semiconductor device 300. On the other hand, a plurality of bit lines 120 and a plurality of plugs 130 are further formed above the substrate 100, wherein each bit line 120 extends parallel to each other in another direction perpendicular to the stated direction (e.g., the y-direction, not shown). Although the specific extension directions of the active region 103, the buried gate, and the bit line 120 are not shown in the accompanying drawings of this embodiment, those skilled in the art should easily understand that, from a top view (not shown), the bit line 120 should be perpendicular to the buried gate and intersect with the active region 103 and the buried gate.

[0064] In detail, each bit line 120 is arranged alternately with the plug 130 in a specific direction, and includes, but is not limited to, a semiconductor layer (e.g., containing polysilicon) 121, a barrier layer 123 (e.g., containing titanium and / or titanium nitride), a conductive layer 125 (e.g., containing low-resistivity metals such as tungsten, aluminum, or copper), and a capping layer 127 (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride). It should be noted that, in principle, all bit lines 120 are formed on the dielectric layer 110 in a spaced manner and intersect with multiple active regions 103. The bit lines 120 falling on each active region 103 extend further into each active region 103 through corresponding bit line contacts (BLCs) 120a formed below them. Figure 1 As shown. That is to say, in this embodiment, each bit line plug 120a is integrally formed with the semiconductor layer 121 of the bit line 120 and directly contacts the corresponding active region 103, but is not limited thereto.

[0065] The plugs 130 are also formed on the substrate 100 in a spaced manner and directly contact the underlying substrate 100 (including the active region 103 and the shallow trench isolation 101). Thus, each plug 130 can serve as a storage node contact (SNC) of the semiconductor device 300 to receive or transmit voltage signals from each memory cell. In one embodiment, the plugs 130 are made of low-resistivity metals such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and each plug 130 is insulated from each other by the spacer structure 140. In one embodiment, the spacer structure 140 may selectively have a single-layer structure or a layered structure. Figure 1 The composite layer structure shown may include, for example, a first spacer wall 141 (e.g., containing silicon nitride), a second spacer wall 143 (e.g., containing silicon oxide), and a third spacer wall 145 (e.g., containing silicon nitride) sequentially stacked on the sidewalls of each line 120, but is not limited thereto.

[0066] Please refer to again Figure 1As shown, a dielectric layer 150 and a plurality of storage node pads (SN pads) 151 are formed above. The dielectric layer 150 integrally covers the plug 130 and the bit line 120, while each storage node pad 151 is formed separately within the dielectric layer 150 and has a top surface flush with the top surface of the dielectric layer 150. Each storage node pad 151 contacts the plug 130 below and is electrically connected to it. In one embodiment, the storage node pad 151 also comprises a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, for example, a metal material different from that of the plug 130, while the dielectric layer 150 comprises a dielectric material such as silicon nitride, but is not limited thereto. In another embodiment, the storage node pad may also be integrally formed with the plug and may comprise the same material.

[0067] like Figure 2 As shown, an insulating layer 160 and a support layer structure 170 are sequentially formed on the dielectric layer 150. The insulating layer 160 includes, for example, an insulating material such as silicon oxide or silicon oxynitride, while the support layer structure 170 includes at least one oxide layer and at least one nitride layer stacked alternately. In this embodiment, the support layer structure 170 may include, for example, a first support material layer 171 (e.g., including silicon oxide), a second support material layer 173 (e.g., including silicon nitride or silicon carbonitride), a third support material layer 175 (e.g., including silicon oxide), a fourth support material layer 177 (e.g., including silicon nitride or silicon carbonitride), and a fifth support material layer 179 (e.g., including silicon oxide) stacked sequentially from bottom to top, but is not limited thereto. Then, multiple openings 172 are formed in the support layer structure 170, sequentially penetrating the fifth support material layer 179, the fourth support material layer 177, the third support material layer 175, the second support material layer 173, the first support material layer 171 and the insulating layer 160, and aligned with the pads 151 of each storage node below, so that the top surface of each pad 151 of the storage node can be exposed from each opening 172.

[0068] Preferably, the oxide layer (e.g., including a first support material layer 171 and a third support material layer 175) may have a relatively large thickness, for example, approximately 5 to 10 times or more the thickness of the nitride layer (e.g., including a second support material layer 173 or a fourth support material layer 177), and the thickness of the nitride layer (e.g., the fourth support material layer 177) disposed away from the substrate 100 is preferably greater than the thickness of the nitride layer (e.g., the second support material layer 173) disposed adjacent to the substrate 100. Figure 2As shown, but not limited thereto. In this embodiment, the overall thickness of the support layer structure 170 is approximately 1600 to 2000 angstroms, but not limited thereto. Those skilled in the art will understand that the specific number of oxide layers (such as the first support material layer 171, or the third support material layer 175, or the fifth support material layer 179) and nitride layers (such as the second support material layer 173 or the fourth support material layer 177) stacked together is not limited to the aforementioned number, but can be adjusted according to actual needs, for example, 4 layers, 5 layers, or other numbers.

[0069] Next, as Figure 3 As shown, a sacrificial layer 180 and a bottom electrode layer 191 are formed within each opening 172. Specifically, the sacrificial layer 180 may be a general dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, and is applied to the surface of the sidewalls of each opening 172, while the multiple bottom electrode layers 191 fill each opening 172. In this embodiment, the formation of the sacrificial layer 180 and the bottom electrode layer 191 includes, but is not limited to, the following steps: First, a deposition process is performed to form a sacrificial material layer (not shown) on the substrate 100, covering the exposed surfaces of the support layer structure 170 and each opening 172. Then, an etching process is performed to form the sacrificial layer 180 located only on the sidewalls of each opening 172. Then, another deposition process and another etching process are performed to form a bottom electrode layer 191 that fills each opening 172. Each bottom electrode layer 191 may have a symmetrical vertical columnar structure, and the top surface of the bottom electrode layer 191 is flush with the top surface of the fifth support material layer 179. Figure 3 As shown. In one embodiment, the bottom electrode layer 191 comprises a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, preferably titanium, but not limited thereto.

[0070] Next, as Figure 4As shown, multiple mask patterns 200 are formed on the substrate 100, covering a portion of the fifth support material layer 179 and a portion of the bottom electrode layer 191, and partially removing the support layer structure 170 through the mask patterns 200. Specifically, each mask pattern 200 covers the support layer structure 170 by simultaneously covering the fifth support material layer 179 between two adjacent bottom electrode layers 191 and approximately one-third of the top surface of the two adjacent bottom electrode layers 191. Thus, by sequentially performing a first etching process (e.g., a dry etching process) and a second etching process (e.g., an isotropic wet etching process) through the mask patterns 200, the fifth support material layer 179 and the third support material layer 175 of the support layer structure 170 can be completely removed, while a portion of the fourth support material layer 177, i.e., the portion not covered by the mask patterns 200, is removed, exposing a portion of the sidewalls of the sacrificial layer 180. It should be specifically noted that, in one embodiment, during the first etching process, the bottom electrode layer 191 and sacrificial layer 180 not covered by the mask pattern 200 are further etched. Thus, a groove R1 is etched on the top of each bottom electrode layer 191 and sacrificial layer 180, with the groove facing away from the fourth support material layer 177 or the fifth support material layer 179. The lowest bottom surface of the groove R1 is higher than the top surface of the fourth support material layer 177 and lower than the top surface of the bottom electrode layer 191. Figure 4 As shown.

[0071] like Figure 5 As shown, by sequentially performing a third etching process (e.g., a dry etching process) and a fourth etching process (e.g., an isotropic wet etching process) through the mask pattern 200, the first support material layer 171 of the support layer structure 170 can be completely removed, while a portion of the second support material layer 173, i.e., the part not covered by the mask pattern 200, is also removed, further exposing part of the sidewalls of the sacrificial layer 180. In one embodiment, the fourth etching process and the second etching process involve, for example, the introduction of an etchant such as tetramethylammonium hydroxide (TMAH), but are not limited thereto. Furthermore, it should be noted that because the sacrificial layer 180 covers and protects the sidewalls of each bottom electrode layer 191, the sidewalls of each bottom electrode layer 191 are effectively prevented from being affected by the first etching process, the second etching process, the third etching process, and the fourth etching process.

[0072] like Figure 6As shown, after completely removing the mask pattern 200, a fifth etching process, such as an isotropic wet etching process, is performed, using an etchant such as tetramethylammonium hydroxide to remove the sacrificial layer 180. It should be noted that during the fifth etching process, the top of the fourth support material layer 177 is also removed to reduce its thickness, so that the remaining fourth support material layer 177 and the remaining second support material layer 173 form a second support layer 277 and a first support layer 273 arranged sequentially from top to bottom, respectively. Preferably, the second support layer 277 and the first support layer 273 have substantially the same thickness, but this is not a limitation.

[0073] Simultaneously, during the fifth etching process, the top of the bottom electrode layer 191 is also removed, reducing the height of the bottom electrode layer 191 and forming multiple columnar bottom electrodes 291. Under this operation, the sacrificial layer 180 formed between each columnar bottom electrode 291 and the second support layer 277, and between each columnar bottom electrode 291 and the first support layer 273, will be simultaneously subjected to stress from both the metal (columnar bottom electrode 291) and the dielectric (second support layer 277, first support layer 273) materials and will not be removed. This forms multiple auxiliary layers 181 that are only sandwiched between each columnar bottom electrode 291 and the first support layer 273, and between each columnar bottom electrode 291 and the second support layer 277, such as... Figure 6 As shown.

[0074] Thus, for example Figure 6 As shown, the first support layer 273 and the second support layer 277 are only disposed on one side of each columnar bottom electrode 291. The auxiliary layer 181 strengthens the adhesion and stress buffering between the metal (columnar bottom electrode 291) and the dielectric (second support layer 277, first support layer 273) materials, so that the first support layer 273 and the second support layer 277 together form a support structure 270 supporting the columnar bottom electrode 291. The top of each columnar bottom electrode 291 is flush with the top surface of the second support layer 277 and has a groove R2. The groove R2 is oriented away from the support structure 270, so that the grooves R2 on two adjacent columnar bottom electrodes 291 are opposite to each other, or the grooves R2 on two columnar bottom electrodes 291 that are in direct contact with the support structure 270 are opposite to each other, and the lowest surface of the groove R2 is higher than the bottom surface of the second support layer 277. Furthermore, since the sacrificial layer 180 originally positioned between each columnar bottom electrode 291 and the insulating layer 160 was removed during the fifth etching process, the bottom of each columnar bottom electrode 291 does not directly contact the insulating layer 160, but is separated from the insulating layer 160 by a gap G1. With this configuration, adjacent columnar bottom electrodes 291 are mirror-symmetrical to each other, which helps to expand the deposition space for the subsequently formed capacitor dielectric layer and top electrode layer.

[0075] Then, as Figure 7 As shown, a deposition process is performed on the substrate 100 to sequentially form a capacitor dielectric layer 293 and a top electrode layer 295. Thus, the pillar-shaped bottom electrode 291, the capacitor dielectric layer 293, and the top electrode layer 295 together form a capacitor structure 290. Specifically, the capacitor dielectric layer 293 conformally covers the exposed surfaces of the pillar-shaped bottom electrode 291 and the insulating layer 160, covering the surface of the groove R2 and filling the gaps G1. This allows the capacitor dielectric layer 293 to also form corresponding grooves R3 on the pillar-shaped bottom electrode 291. Furthermore, the capacitor dielectric layer 293, filling the gaps G1, is sandwiched between the insulating layer 160 and each pillar-shaped bottom electrode 291. The top electrode layer 295 fills the remaining space between the pillar-shaped bottom electrodes 291. The capacitor dielectric layer 293 and the top electrode layer 295 may be further filled between the second support layer 277 and the first support layer 273, and further filled between the first support layer 273 and the insulating layer 160, so that the capacitor dielectric layer 293 can directly contact the top and bottom surfaces of the auxiliary layer 181. In one embodiment, the capacitor dielectric layer 293 may include a high dielectric constant dielectric material, selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2), and zirconium oxide-aluminum oxide-zirconia (ZAZ), preferably including zirconium oxide-aluminum oxide-zirconia; the top electrode layer 295 may include a low resistivity metal material such as aluminum, titanium, copper, or tungsten, preferably including titanium, but not limited thereto.

[0076] Thus, the fabrication process of capacitor structure 290 is completed. Capacitor structure 290 includes multiple vertically extending capacitors as storage nodes (SN) of semiconductor device 300. These storage nodes are electrically connected to transistor components (not shown) of semiconductor device 300 via storage node pads 151 and storage node plugs (i.e., plugs 130), ensuring good contact between capacitor structure 290 and the storage node plugs disposed on substrate 100. With this configuration, semiconductor device 300 of this embodiment can form a dynamic random access memory (DRAM) device, consisting of at least one transistor component and at least one capacitor constituting the smallest unit (memory cell) in a DRAM array, to receive voltage information from bit line 120 and the buried word line.

[0077] According to the fabrication method in the first embodiment of the present invention, a sacrificial layer 180 and a bottom electrode layer 191 are first formed within the opening 192. The sacrificial layer 180 protects the sidewalls of the bottom electrode layer 191. Then, the sacrificial layer 180 is partially removed by a subsequent etching process, forming an auxiliary layer 181 that is only sandwiched between each columnar bottom electrode 291 and the support structure 270. Thus, the formation of the auxiliary layer 181 not only strengthens the adhesion and stress buffering between the metal (columnar bottom electrode 291) and the dielectric (second support layer 277, first support layer 273) materials, but also further increases the distance between each columnar bottom electrode 291, thereby expanding the deposition space for the subsequently formed capacitor dielectric layer 293 and top electrode layer 295. Therefore, in the fabrication method of this embodiment, the deposition process of the capacitor dielectric layer 293 and top electrode layer 295 can be carried out more smoothly, achieving a simplified fabrication process.

[0078] Furthermore, during the first etching process, the bottom electrode layer 191 and sacrificial layer 180 not covered by the mask pattern 200 can be selectively etched to form a groove R2 on the top of the columnar bottom electrode 291, with the groove facing away from the support structure 270. With this configuration, adjacent columnar bottom electrodes 291 are mirror-symmetrical, further expanding the deposition space for the subsequently formed capacitor dielectric layer 293 and top electrode layer 295. In other words, the fabrication method of this embodiment strengthens the adhesion between the columnar bottom electrode 291 and the second support layer 277 and the first support layer 273 by using the auxiliary layer 181, and provides stress buffering. The auxiliary layer 181 and the support structure 270 jointly support the columnar bottom electrode 291, thus enabling the fabricated semiconductor device 300 to have a more stable and reliable structure and achieve relatively optimized device performance.

[0079] Furthermore, those skilled in the art will readily understand that, to meet actual product requirements, the present invention may also have other forms of forming semiconductor devices and their fabrication methods, and is not limited to the foregoing. For example, in another embodiment, the removal of the sacrificial layer 180 can be integrated into the fabrication process of removing a film layer of similar material. For instance, when the sacrificial layer 180 includes silicon oxide, a portion of the sacrificial layer 180 is removed during the removal of the fifth support material layer 179 and the third support material layer 175 (i.e., the second etching process), and another portion of the sacrificial layer 180 is removed during the removal of the first support material layer 171 (i.e., the fourth etching process). Thus, the fifth etching process can be omitted. Other embodiments or variations of the method for forming semiconductor devices according to the present invention will be further described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same points. In addition, the same components in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0080] Please refer to Figure 8 The diagram illustrates the steps of a method for fabricating a semiconductor device 400 according to a second embodiment of the present invention. The steps for forming the semiconductor device 400 in this embodiment are generally the same as those for forming the semiconductor device 300 in the first embodiment described above, as follows: Figures 1 to 6 As shown, it will not be described again here. The main difference between this embodiment and the first embodiment mentioned above is that in this embodiment, the capacitor dielectric layer 393 fills the groove R2, so that the capacitor dielectric layer 393 has a flat surface as a whole.

[0081] In detail, the capacitor dielectric layer 393 in this embodiment is also selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zinc oxide, titanium oxide, and zirconium oxide-aluminum oxide-zirconia, preferably including a dielectric material with good filling ability to fill the groove R2 at the top of each columnar bottom electrode 291, such as Figure 8 As shown. In this way, the columnar bottom electrode 291, the capacitor dielectric layer 393 and the top electrode layer 295 can also jointly form the capacitor structure 390, and the capacitor dielectric layer 393 filled into the groove R2 can be formed more stably on each columnar bottom electrode 291, avoiding peeling.

[0082] According to the fabrication method in the second embodiment of the present invention, the formation of the auxiliary layer 181 also strengthens the adhesion and stress buffering between the metal (pillared bottom electrode 291) and the dielectric (support structure 270) material, and further increases the distance between each pillared bottom electrode 291, thereby expanding the deposition space of the subsequently formed capacitor dielectric layer 393 and top electrode layer 295, so that the deposition process of capacitor dielectric layer 393 and top electrode layer 295 can be carried out more smoothly. At the same time, the setting of the auxiliary layer 181 can strengthen the adhesion between the pillared bottom electrode 291 and the support structure 270 and provide stress buffering. With the help of the auxiliary layer 181 and the support structure 270, the pillared bottom electrode 291 is supported, so that the semiconductor device 400 can have a more stable and reliable structure and achieve relatively optimized device performance.

[0083] Please refer to Figure 9 The diagram illustrates the steps of a method for fabricating a semiconductor device 500 according to a third embodiment of the present invention. The steps for forming the semiconductor device 500 in this embodiment are generally the same as those for forming the semiconductor device 300 in the first embodiment described above, as follows: Figures 1 to 6 As shown, it will not be described again here. The main difference between this embodiment and the first embodiment described above is that the top of each columnar bottom electrode 591 does not have any groove, and the bottom part of each columnar bottom electrode 591 extends into the storage node pads 551 below.

[0084] In detail, the openings (not shown) in this embodiment are sequentially inserted as follows: Figure 2 The fifth support material layer 179, the fourth support material layer 177, the third support material layer 175, the second support material layer 173, the first support material layer 171, the insulating layer 160, and a portion of the memory node pads 151 are shown, such that each memory node pad 551 has a groove (not shown) recessed downwards from each of the openings. Thus, the sacrificial layer (not shown) and the bottom electrode layer (not shown) subsequently formed in each of the openings can be correspondingly formed in the grooves of the memory node pads 551, forming a columnar bottom electrode 591 that partially extends into the memory node pads 551.

[0085] Subsequently, during the first etching process of this embodiment, the etching selectivity was deliberately adjusted to avoid etched material not being properly selected. Figure 4The sacrificial layer and the bottom electrode layer covered by the mask pattern 200 shown are etched without etching grooves on the top of the sacrificial layer and the bottom electrode layer. In this operation, the top surfaces of each columnar bottom electrode 591 are flat, resulting in a uniformly flat surface for the subsequently formed capacitor dielectric layer 593. Furthermore, each columnar bottom electrode 591 partially extends into the memory node pad 551, and a portion of the capacitor dielectric layer 593 is further sandwiched between the insulating layer 160, each memory node pad 551, and each columnar bottom electrode 591, as shown. Figure 9 As shown. Thus, the columnar bottom electrode 591, the capacitor dielectric layer 593, and the top electrode layer 295 can also jointly form the capacitor structure 590 of this embodiment.

[0086] According to the fabrication method in the third embodiment of the present invention, the formation of the auxiliary layer 181 also strengthens the adhesion and stress buffering between the metal (pillared bottom electrode 591) and the dielectric (support structure 270) material, and further increases the distance between each pillared bottom electrode 591, thereby expanding the deposition space of the subsequently formed capacitor dielectric layer 593 and top electrode layer 595, so that the deposition process of the capacitor dielectric layer 593 and top electrode layer 595 can be carried out more smoothly. At the same time, in this embodiment, each pillared bottom electrode 591 further extends into each memory node pad 551 to increase the contact area between the two and improve performance. Thus, in the semiconductor device 500 of this embodiment, the setting of the auxiliary layer 181 can also strengthen the adhesion between the pillared bottom electrode 591 and the support structure 270 and provide stress buffering, so that the semiconductor device 500 can have a more stable and reliable structure and achieve relatively optimized device performance.

[0087] In general, this invention involves pre-forming a sacrificial layer on the sidewall of the opening before forming the columnar bottom electrode to protect the sidewall of the columnar bottom electrode layer. In subsequent fabrication processes, the sacrificial layer is partially removed, forming an auxiliary layer that exists only between the columnar bottom electrode and the support structure. Thus, the formation of this auxiliary layer not only strengthens the adhesion and stress buffering between the metal (the columnar bottom electrode) and the dielectric (the support structure) materials, but also further increases the distance between the columnar bottom electrodes, thereby expanding the deposition space for the subsequently formed capacitor dielectric layer and top electrode layer. This allows the deposition process of the capacitor dielectric layer and the top electrode layer to proceed more smoothly, achieving a simplified fabrication process.

[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized by include: Substrate; A capacitor structure is disposed on the substrate, the capacitor structure including a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer; A dielectric layer is disposed on the substrate; Multiple memory node pads are disposed within the dielectric layer, spaced apart from each other, and each contacts the columnar bottom electrode; An insulating layer is disposed on the storage node pad, the insulating layer covers and directly contacts the surface of the dielectric layer and a portion of the surface of the storage node pad, a portion of the capacitor dielectric layer is sandwiched between the insulating layer and each of the columnar bottom electrodes, the capacitor dielectric layer directly contacts the top and sidewalls of the insulating layer, and the capacitor dielectric layer is in direct contact with the storage node pad; A support structure is disposed between adjacent columnar bottom electrodes, the support structure comprising a first support layer and a second support layer arranged sequentially from bottom to top; as well as The auxiliary layer is sandwiched between each of the columnar bottom electrodes and the support structure, and directly contacts the sidewalls of the first support layer, the second support layer and the columnar bottom electrodes.

2. The semiconductor device according to claim 1, characterized in that, A portion of each of the columnar bottom electrodes extends into each of the memory node pads.

3. The semiconductor device according to claim 1, characterized in that, Each of the columnar bottom electrodes has a groove at its top, with the opening of the groove facing away from the support structure.

4. The semiconductor device according to claim 3, characterized in that, The capacitor dielectric layer covers the surface of the groove.

5. The semiconductor device according to claim 3, characterized in that, The capacitor dielectric layer fills the groove.

6. The semiconductor device according to claim 3, characterized in that, The lowest surface of each groove is higher than the bottom surface of the second support layer.

7. The semiconductor device according to claim 1, characterized in that, The two adjacent columnar bottom electrodes are mirror images of each other.

8. A method for fabricating a semiconductor device, characterized in that... include: Provide substrate; A dielectric layer is formed on the substrate; Multiple storage node pads are formed and arranged in the dielectric layer with each other separated; An insulating layer is formed on the storage node pads, the insulating layer covering and directly contacting the surface of the dielectric layer and a portion of the surface of the storage node pads; A capacitor structure is formed on the substrate. The capacitor structure includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. The plurality of memory node pads respectively contact each of the columnar bottom electrodes. A portion of the capacitor dielectric layer is sandwiched between the insulating layer and each of the columnar bottom electrodes. The capacitor dielectric layer directly contacts the top and sidewalls of the insulating layer, and the capacitor dielectric layer directly contacts the memory node pads. A support structure is formed between adjacent columnar bottom electrodes, the support structure comprising a first support layer and a second support layer arranged sequentially from bottom to top; as well as An auxiliary layer is formed between each of the columnar bottom electrodes and the support structure, the auxiliary layer being in direct contact only with the first support layer, the second support layer and the sidewall of the columnar bottom electrode.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, Also includes: A first support material layer, a second support material layer, a third support material layer, a fourth support material layer, and a fifth support material layer are formed on the substrate in sequence. Multiple openings are formed, penetrating the fifth support material layer, the fourth support material layer, the third support material layer, the second support material layer, and the first support material layer; A sacrificial layer is formed on the sidewall of the opening; Multiple bottom electrode layers are formed, each filling one of the openings; Multiple mask patterns are formed on the fifth support material layer; The fifth support material layer, a portion of the fourth support material layer, and the third support material layer are removed through the mask pattern; The second support material layer and the first support material layer are removed through the mask pattern; as well as The mask pattern is completely removed to form the support structure.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Also includes: Before removing portions of the second support material layer and the first support material layer, a groove is etched on the top of each of the bottom electrode layers to form the columnar bottom electrode, wherein the notch of the groove faces away from the support structure.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The capacitor dielectric layer covers the surface of the groove.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, The capacitor dielectric layer fills the groove.

13. The method for fabricating a semiconductor device according to claim 9, characterized in that, Also includes: Perform a first wet etching process to remove the fifth support material layer and the third support material layer; as well as A second wet etching process is performed to remove the first support material layer.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, Also includes: After performing the first wet etching process and the second wet etching process, the sacrificial layer is etched to form the auxiliary layer.

15. The method for fabricating a semiconductor device according to claim 13, characterized in that, Also includes: During the first wet etching process and the second wet etching process, the sacrificial layer is etched together to form the auxiliary layer, wherein the auxiliary layer comprises materials identical to the fifth support material layer, the third support material layer and the first support material layer.

16. The method for fabricating a semiconductor device according to claim 14, characterized in that, Also includes: During the etching of the sacrificial layer, a portion of the remaining portion of the fourth support material layer is removed.

17. The method for fabricating a semiconductor device according to claim 9, characterized in that, Also includes: When forming the opening, the pads of each of the storage nodes are partially removed; as well as The sacrificial layer and the columnar bottom electrode are formed in the opening, wherein the sacrificial layer and the columnar bottom electrode partially extend into the pads of each of the memory nodes.

18. The method for fabricating a semiconductor device according to claim 17, characterized in that, Also includes: Remove the sacrificial layer that extends into the pads of each of the storage nodes; as well as The capacitor dielectric layer is formed, wherein the capacitor dielectric layer is partially sandwiched between each of the memory node pads and each of the columnar bottom electrodes.

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