Semiconductor device and method of manufacturing the same

By pre-forming a sacrificial layer on the sidewall of the opening before forming the columnar bottom electrode and removing it in subsequent processes to form an auxiliary layer, the problems of high difficulty in increasing the density of memory cells and complex processes in the fabrication of dynamic random access memory are solved, resulting in a more stable and reliable semiconductor device structure and optimized device performance.

CN116867267BActive Publication Date: 2026-04-14FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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Patent Information

Application Number
CN202310037013.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-01-10
Publication Date
2026-04-14
Estimated Expiration
2043-01-10

AI Technical Summary

Technical Problem

Existing technologies for fabricating dynamic random access memory with recessed gate structures face challenges such as difficulty in increasing storage cell density, complex and unstable manufacturing processes.

Method used

Before the columnar bottom electrode is formed, a sacrificial layer is pre-formed on the opening sidewall to protect the bottom electrode sidewall. In subsequent processes, the sacrificial layer is partially removed to form an auxiliary layer, which strengthens the adhesion and stress buffer between the metal and the dielectric, and expands the deposition space between the capacitor dielectric layer and the top electrode layer.

Benefits of technology

It simplifies the manufacturing process, improves the stability and reliability of semiconductor devices, optimizes device performance, and enhances the adhesion and stress buffering effect of capacitor structures.

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Abstract

Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, a capacitor structure, a support structure, and an auxiliary layer. The capacitor structure is disposed on the substrate and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. The support structure is disposed between adjacent columnar bottom electrodes and includes a first support layer and a second support layer disposed in sequence from bottom to top. The auxiliary layer is disposed only between each columnar bottom electrode and the support structure and directly contacts the first support layer, the second support layer, and sidewalls of the columnar bottom electrode. Thus, the adhesion between the columnar bottom electrode and the support structure is strengthened by the auxiliary layer, and stress buffering is provided, thereby obtaining a more stable and reliable structure and achieving a relatively optimized device performance.
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