A fast adaptive regulation inductive current zero-crossing detection circuit

Abstract

A kind of fast adaptive regulation inductance current zero-crossing detection circuit, can be in the DCM mode when synchronous DC-DC step-down converter works by fast adaptive regulation realizes timely and accurate inductance current zero-crossing detection.In the DCM mode, first by comparison circuit detection SW end voltage judges whether inductance current zero-crossing, after the comparator output of each SW end voltage detection unit flips, then by SW end voltage to produce adaptive delay time, adaptive adjustment voltage is generated in adaptive delay time to adjust the reference voltage VN of comparator in detection circuit, to ensure the accurate zero-crossing detection of next cycle.Wherein still contain DCM CCM mode switching circuit, by zero-crossing detection signal and power tube conducting signal realizes DCM CCM mode stable switching, so that system can be closed adaptive delay unit, adaptive voltage regulation unit in time when CCM mode of large load, to ensure that zero-crossing detection circuit has lower power consumption and under various load conditions stable operation.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a fast adaptive adjustment circuit for zero-crossing detection of inductor current, which can be applied to detect inductor current in synchronous DC-DC buck converters. Background Technology

[0002] like Figure 1 As shown, a synchronous DC-DC buck converter includes power transistors, rectifier diodes, inductors, capacitors, voltage divider resistors, a detection unit, a logic control unit, and a drive unit. When power transistor PM1 is on and rectifier diode NM1 is off, the input voltage charges the inductor L and the capacitor. The on power transistor can be considered as a resistor R with a very small resistance. dson Therefore, the voltage V at the SW terminal is SW =V IN -I L ·R dson With inductor current I L The voltage rises and falls accordingly; after a series of system feedback controls, PM1 closes and NM1 opens. At this time, the inductor current remains in the same direction but decreases in amplitude, and the voltage at the SW terminal becomes negative instantaneously after the switch switching. At this time, V SW =-I L ·R dson Subsequently, with I L It rises slowly as it increases. From the working principle of DC-DC converters, we know that I... L The average value of the inductor current equals the load current. When the load current is large, the inductor current will also be large, so it usually will not drop to zero within one cycle. In this case, the system operates in CCM mode. When the load current is small, the inductor current will also be small and may drop to zero within one cycle. In this case, the system operates in DCM mode. L When the voltage drops to 0, the rectifier tube needs to be shut off accurately and promptly. If it is in I... L If rectifier NM1 is turned off before the voltage drops to 0, the body diode of NM1 will conduct, resulting in unnecessary energy consumption; if I... L If the rectifier diode NM1 is only turned off when the current is already negative, the output capacitor C1 needs to provide additional energy to maintain the current. To ensure system stability and high efficiency, an inductor current zero-crossing detection circuit is needed to turn off the rectifier diode in time when the inductor current drops to zero.

[0003] Existing traditional zero-crossing detection techniques for inductor current sample in parallel with a small sampling diode across the rectifier NM1, or determine the inductor current state by detecting changes in the voltage at the SW terminal. However, due to system delay, comparator offset, and the influence of some parasitic parameters, traditional zero-crossing detection circuits often fail to turn off the synchronous rectifier precisely when the inductor current reaches zero. Some circuits pre-calculate the delay time and adjust the comparator's reference voltage to achieve early rectifier turn-off. This method, due to its fixed delay time, cannot achieve high detection accuracy and timely rectifier turn-off under a wide range of conditions, and it cannot adaptively adjust when detection deviations occur. Other circuits determine the rectifier turn-off time by detecting the state of the voltage at the SW terminal when the zero-crossing detection comparator flips. L The system adjusts the reference voltage of the comparator by adding or subtracting a counter to generate a corresponding digital code, which is then used by a DAC to adjust the reference voltage. However, this method, which uses the counting principle, can only adjust the reference voltage in a certain step size and cannot adjust the reference voltage very precisely to achieve accurate detection. Furthermore, when the deviation is large, it may take several cycles to adjust to the ideal state, resulting in a slow system response. Summary of the Invention

[0004] To address the problems existing in the above-mentioned background technology, a fast adaptive adjustment inductor current zero-crossing detection circuit is proposed. This circuit can achieve adaptive adjustment of the zero-crossing detection circuit and can automatically and stably switch under different load conditions. In CCM state, the adaptive delay unit and adaptive voltage adjustment unit are turned off to reduce the power consumption of the detection circuit.

[0005] A novel fast adaptive adjustment circuit for zero-crossing inductor current detection can achieve timely and accurate zero-crossing detection of inductor current through rapid adaptive adjustment when a synchronous DC-DC buck converter is operating in DCM mode. Figure 2 The circuit shown works as follows: When the system operates in DCM mode, the voltage at the SW terminal is first detected by the comparator circuit to determine whether the inductor current has crossed zero. After each flip of the comparator output of the SW terminal voltage detection unit, an adaptive delay time is generated based on the SW terminal voltage. During the adaptive delay time, an adaptive adjustment voltage is generated to adjust the reference voltage VN of the comparator in the detection circuit, thereby ensuring accurate zero-crossing detection in the next cycle. It also includes a DCM / CCM mode switching circuit, which achieves stable switching between DCM and CCM modes through the zero-crossing detection signal and the power transistor's on signal. This allows the system to promptly shut down the adaptive delay unit and adaptive voltage adjustment unit under heavy load CCM mode, ensuring low power consumption and stable operation of the zero-crossing detection circuit under various load conditions.

[0006] This invention proposes a fast adaptive adjustment circuit for zero-crossing detection of inductor current, which has the following main advantages:

[0007] 1. This invention generates an adaptive delay time and an adaptive adjustment voltage by sampling the voltage at the SW terminal of the zero-crossing detection comparator shortly after its flip, thereby adaptively adjusting the reference voltage of the zero-crossing detection comparator. Since both the delay time and the adjustment voltage are strictly related to the SW voltage, adaptive adjustment of the zero-crossing detection circuit can be achieved. Furthermore, because the adjustment method proposed in this invention is implemented analogally, there is no limitation on the adjustment step size. Even when the deviation in the previous detection cycle is large, it can be quickly adjusted to ensure accurate judgment of the zero-crossing detection comparator in the next cycle and timely shutdown of the rectifier diode.

[0008] 2. The present invention also includes a DCM CCM mode judgment circuit, which can realize that the zero-crossing detection circuit can automatically and stably switch under different load conditions, and turn off the adaptive delay unit and the adaptive voltage adjustment unit to reduce the power consumption of the detection circuit in the CCM state. Attached Figure Description

[0009] Figure 1 This is a system application diagram in the background technology of this invention.

[0010] Figure 2 This is a schematic diagram of the fast adaptive adjustment inductor current zero-crossing detection circuit in an embodiment of the present invention.

[0011] Figure 3 These are three possible scenarios during zero-crossing detection in this embodiment of the invention.

[0012] Figure 4 This is a schematic diagram of the adaptive delay unit circuit in an embodiment of the present invention.

[0013] Figure 5 This is a schematic diagram of the DCM CCM mode determination unit circuit in an embodiment of the present invention.

[0014] Figure 6 This is a timing diagram of the DCM CCM mode determination process in an embodiment of the present invention.

[0015] Figure 7 This is a diagram of key system signals during DCM / CCM switching in an embodiment of the present invention. Detailed Implementation

[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0017] Typical application scenarios of this invention include: Figure 1 As shown, it can be used in a current-mode PWM-PFM type synchronous rectified DC-DC buck converter. The fast adaptive inductor current detection circuit proposed in this invention is as follows: Figure 2As shown, it consists of four units: SW terminal voltage comparison unit, adaptive delay unit, adaptive voltage adjustment unit, and DCM / CCM mode judgment unit.

[0018] like Figure 2 As shown, when the system is set to PFM-PWM mode and the load current is small, the system is in DCM operating mode, all four units are working normally, and the SW terminal voltage detection unit determines I. L Whether it crosses zero, when I is detected L When the comparator crosses zero, it flips, and the adaptive voltage regulation unit adaptively adjusts the comparator reference voltage within the delay time generated by the adaptive delay unit. When the load current is large, the DCM CCM mode judgment circuit causes the DCM signal to flip from high to low to enter the CCM mode and shuts down the adaptive delay unit and the adaptive voltage regulation unit.

[0019] When a stable switching frequency is required for a current-mode PWM-PFM synchronous rectified DC-DC buck converter over a wide load range, the system needs to be set to forced PWM mode. This mode sacrifices conversion efficiency for a more stable switching frequency. In forced PWM mode, the inductor current is allowed to be negative. At this time, the SW terminal voltage comparator unit works normally, while the adaptive delay unit, adaptive voltage regulation unit, and DCM / CCM mode judgment unit do not work. Resistor R4 is shorted through NM10 so that the SW terminal voltage comparator unit functions to detect the minimum current limit of the inductor current.

[0020] The working principle of the entire system will be explained in detail below by describing the specific working principles of the system sub-modules.

[0021] The voltage comparison unit at the SW terminal first obtains VP and VN through a current-to-voltage conversion structure, and then compares VP and VN using comparator COMP. The current bias section employs a cascode structure, using NM3 (NM5) transistors to shield the influence of power supply voltage changes on NM4 (NM6) transistors, reducing the impact of channel length modulation effect on the bias current. When the SW voltage changes, the source voltage of NM4 changes accordingly, thus changing I1. R2 and R3 convert the relationship between I1 and I4 into the relationship between VP and VN. COMP is a gate-input voltage comparator; internally, it determines whether the COMP_out output is high or low by comparing the magnitudes of VP and VN.

[0022] The adaptive delay unit mainly consists of an amplifier composed of NM1, NM2, PM1, and PM2, and an adjustable delay unit composed of NM3, PM5, and C1. NM2 is a common-gate configuration with source input and drain output. I1 and R1 transfer the change in SW voltage to VGATE, which is then amplified by a common-source PMOS transistor (comprising NM1 and PM2) to the load, converting it into the gate voltage of PM4 and thus controlling the change in current I3. By controlling the magnitude of I3, the charging time of C1 by PM5 can be controlled, thereby controlling the delay time.

[0023] The adaptive voltage regulation unit mainly consists of AMP, EA, and capacitors C1 and C2. During the time when IL_zero is high, C1 is charged to obtain V_C1. At the same time, the error amplifier EA amplifies the difference between Vref1 and V_C1 and obtains the output voltage V_tune by charging and discharging C2. When IL_zero is low, NM9 is disconnected and the voltage V_tune is maintained through C2 to regulate the current I3 through PM8. AMP is connected in unity gain form to reset the voltage of V_C1 to Vref1 when the IL_zero signal is low.

[0024] The DCM / CCM mode determination unit implements frequency division counting through the cascading of four D flip-flops with reset function. DFF2-DFF4 output Q1-Q4 respectively, and an AND logic gate checks whether all Q1-Q4 are high, thus determining if the system has entered DCM mode. When the load current increases and the inductor current no longer crosses zero, the reset signal goes low, and all counter outputs Q1-Q4 are pulled low, indicating that the system has exited DCM mode and entered CCM mode.

[0025] like Figure 2 As shown, depending on the given FPWM signal and the load conditions, the SW terminal voltage detection unit has three different operating modes: DCM mode in PFM-PWM mode, CCM mode in PFM-PWM mode, and forced PWM mode.

[0026] like Figure 1 , 2 As shown, when FPWM is 0 and the load is small, the system operates in PFM-PWM mode. When the power transistor is on and the rectifier transistor is off, the inductor current rises, and the voltage V at the SW terminal increases. SW =V IN -I L ·R dson When the power transistor is off and the rectifier transistor is on, the inductor current decreases, and the voltage V at the SW terminal decreases. SW =-I L ·R dson Therefore, in I LWhen the voltage drops to 0, the voltage at terminal SW is also 0. NM1-NM6 form a current mirror bias circuit, providing bias current to the circuit. Since R2 = R3, when I1 = I4, VP = VN, and the comparator flips. When the rectifier diode is on, the voltage at terminal SW rises as IL decreases. By setting appropriate values ​​for R2, R3, R4, R5, and R6, VN can be achieved when the voltage at terminal SW gradually rises from a negative value to 0. GS4 =V GS6 At this point, the current I1 = I4, the voltage across the comparator VP = VN, and the comparator output signal COMP_out flips from low to high. If the comparator output flips before IL reaches 0 due to comparator offset, parasitic parameters of the device, or changes in the operating environment, the voltage at the SW terminal will be less than 0, which may cause the parasitic body diode of the rectifier to conduct and freewheel. If the comparator output flips only after IL has already fallen below 0, reverse current will occur, flowing through the substrate of the synchronous rectifier and causing additional losses.

[0027] When the load is large, the average value of the inductor current is also large, and the inductor current no longer crosses zero. The DCM CCM mode judgment unit outputs CCM at a high level, which, through the OR1 logic gate, makes the AT_off signal high, thus disabling the adaptive delay unit and the adaptive voltage regulation unit. When the system load decreases and triggers the zero-crossing detection signal, the DCM CCM judgment module will cause the CCM output to go low, thus re-enabling the adaptive delay unit and the adaptive voltage regulation unit.

[0028] Whether to select FPWM mode is determined by the manually given mode selection signal FPWM. When FPWM is set to high, the system enters FPWM mode, which allows negative inductor current. When FPWM is high, the AT_off signal is made high through the AND logic gate OR1, which disables the adaptive delay unit and the adaptive voltage regulation unit. At the same time, NM10 shorts resistor R4 so that the voltage comparator unit at the SW terminal functions as a detector for detecting the minimum current limit of the inductor current. The comparator output signal COMP_OUT is ANDed with the FPWM signal to obtain I. L _MIN signal. When I L When the _MIN signal is high, it indicates that the inductor current has reached the minimum current limit.

[0029] The circuit schematic of the adaptive delay time unit is as follows: Figure 4 As shown. When AT_off is high or LSON is low, delay_on is low, PM3 is on and NM2 is off, the circuit does not work; when AT_off is low and LSON is high, delay_on is high, PM3 is off and NM2 is on, the circuit starts working. The rectifier diode's on-state signal LSON is delayed using the principle of capacitor charging and discharging. Figure 4From the capacitor charging formula, we can know that... Delay time can be obtained Delay time Δ t It is inversely proportional to the current I3. Adaptive delay can be achieved by controlling the charging current through the SW voltage. Specifically, V is generated by sampling the SW voltage after LSON flips from high to low. GATE Signal V GATE =I1·R1+V SW +V dsNM2 The magnitude of the control current I2 is determined by the lower the voltage SW. GATE The lower the voltage, the lower I2 becomes as the SW voltage decreases, ensuring that NM1 can conduct. PM2 and PM4 form a current mirror structure. Therefore, I3 also decreases as the SW voltage decreases. When the falling edge of LSON arrives, PM5 turns on to charge the capacitor. As analyzed above, different currents flow through PM5 to charge capacitor C1 under different SW voltages, resulting in different delay times. When the SW voltage is small, the charging current is also small, and the capacitor is charged very slowly to the threshold voltage of the next inverter, thus obtaining a larger delay time. When the SW voltage is large, the charging current is also large, and the capacitor is charged very quickly to the threshold voltage of the next inverter, thus obtaining a smaller delay time. The delay time generated when SW=0 is defined as t0, the delay time obtained when SW is small is t1, and the delay time obtained when SW is large is t2. As analyzed above, t2... <t0<t1。

[0030] SW voltage after shutdown Capacitor charging current Adaptive delay time ideal state 0 I3 <![CDATA[t0]]> Premature rectifier shutdown Less than 0 Less than I3 <![CDATA[t1>t0]]> Rectifier tube turned off too late Greater than 0 Greater than I3 <![CDATA[t2<t0]]>

[0031] Figure 2 The diagram inside the dashed box shows the schematic of the adaptive adjustment unit. The forced PWM signal and the CCM signal are ORed to obtain the switching signal AT_off of the adaptive adjustment unit. When the system is operating in FPWM mode or CCM mode, the adaptive delay unit and the adaptive voltage regulation unit are turned off. When the system is operating in DCM mode, the AT_off signal is low, and PM4 and PM5 are turned on, that is, the adaptive voltage regulation unit is turned on.

[0032] The circuit works as follows: During each detection cycle, the comparator's output COMP_out flips from low to high, causing the LSON signal to flip from high to low. First, the LSON signal is delayed by t using an adaptive delay unit to obtain the LSON_delay signal. Then, the LSON_delay signal and COMP_out are ANDed through a logic gate to obtain the IL_zero pulse signal. When IL_zero is high (i.e., during the delay period), NM8 is open and PM7 is closed. Current I2 charges capacitor C1 under the control of voltage SW. Simultaneously, error amplifier EA amplifies the voltages V_C1 and Vref1 on the upper plate of C1 to obtain the adaptive adjustment voltage V_tune. V_tune then controls the gate of PM8 to generate an adjustment current I3, which adjusts the comparator's reference voltage VN for the next cycle. When IL_zero is low (i.e., during the non-delay period), PM7 is open, and AMP resets the voltage of capacitor C1, ensuring that the capacitor voltage rises from Vref1 each time it is charged. NM9 is closed to ensure that the adjustment voltage V_tune is unaffected during the voltage reset of C1.

[0033] like Figure 2 , 3 As shown, in an ideal state, the comparator flips precisely when SW=0. The comparator output signal COMP_out and the LSON_delay signal generated by the adaptive delay unit are ANDed to generate an IL_zero pulse signal with a pulse width equal to the delay time t0. During time t0, PM7 is off and NM8 is on. The current I20 generated under the control of the SW voltage charges capacitor C1, raising the capacitor voltage from Vref1 to VC10. VC10 passes through the error amplifier EA to obtain the V_tune0 signal. Under the control of this signal, I30 and I4 are obtained together to obtain the ideal reference point VN0 of the comparator. The ideal reference point VN0 ensures that the rectifier is turned off in a timely and accurate manner during each detection. When IL_zero is low, i.e., during the non-delay time, PM7 is on and uses AMP to reset the voltage of capacitor C1, ensuring that the voltage of capacitor C1 rises from Vref1 during the next charging. At the same time, NM9 is off to ensure that the voltage adjustment voltage V_tune0 is not affected when resetting the voltage of C1.

[0034] like Figure 2 , 3As shown, if the comparator flips too early, that is, it flips when SW is less than 0, at a relatively small SW voltage, a relatively large delay time t1 is generated at the falling edge of LSON, and a relatively large charging current I21. During the relatively long high-level signal time t1 of the IL_zero pulse, PM7 is turned off and NM8 is turned on. The relatively large charging current I21 charges the capacitor C1, causing the capacitor voltage to rise to VC11 based on Vref1. VC11 passes through the error amplifier EA to obtain a relatively small V_tune1 signal. Under the control of this signal, I31 and I4 together obtain the comparator reference point VN1. Since VN1 > VN0, the relatively large VN1 enables the comparator to flip later during the next cycle detection to achieve the adaptive adjustment function. When IL_zero is at a low level, that is, during the non-delay time, PM7 is turned on to reset the voltage of the capacitor C1 through AMP to ensure that the capacitor C1 voltage starts to rise from Vref1 during the next charging; at the same time, NM9 is disconnected to ensure that the adjustment voltage V_tune1 is not affected when resetting the voltage of C1.

[0035] As Figure 2 , 3 shown, if the comparator flips too late, that is, it flips after SW is greater than 0, at a relatively large SW voltage, a relatively small delay time t2 is generated at the falling edge of LSON, and a relatively small charging current I22. Then during the relatively short high-level signal time t2 of the IL_zero pulse, PM7 is turned off and NM8 is turned on. The relatively small charging current I22 charges the capacitor C1, causing the capacitor voltage to rise to VC12 based on Vref1. VC12 passes through the error amplifier EA to obtain a relatively large V_tune2 signal. Under the control of this signal, a relatively small I32 and I4 together obtain a relatively small comparator reference point VN2. Since VN2 < VN0, the relatively small VN2 enables the comparator to flip earlier during the next cycle detection to achieve the adaptive adjustment function. When IL_zero is at a low level, that is, during the non-delay time, PM7 is turned on to reset the voltage of the capacitor C1 through AMP to ensure that the capacitor C1 voltage starts to rise from Vref1 during the next charging; at the same time, NM9 is disconnected to ensure that the adjustment voltage V_tune2 is not affected when resetting the voltage of C1.

[0036]

[0037] Figure 5 is the schematic diagram of the adaptive adjustment unit, Figure 6 is the working timing diagram of this unit, Figure 7This diagram illustrates the key system signals during DCM / CCM switching. When the zero-crossing detection comparator receives an IL_zero pulse signal, it passes through the SR latch, causing Q to go high. After a period of time, the power transistor turn-on signal HSON arrives, causing Q to go low. After passing through DFF1, the high level of HSON is captured as the high level of Q_delay, resulting in a high-level reset signal that causes DFF2-DFF4 to start counting. After a counting cycle, when Q1-Q4 are all 1, EN_CNT toggles from high to low, stopping the counting. Then, after passing through INV4, the DCM signal toggles from low to high, and the system enters DCM mode. Later, when the load current is low, an IL_zero pulse signal will be generated in each cycle, keeping the reset signal high and EN_CNT low. When the load current increases, the inductor current no longer crosses zero and no longer generates the IL_zero pulse signal. Q is pulled low by HSON and will not be pulled high again. Q remains at a low level. When the HSON signal arrives in the next cycle, DFF1 makes the reset signal low, and the counter outputs Q1-Q4 are all pulled low, causing EN_CNT to flip from low to high and DCM to flip from high to low. The system exits DCM mode and enters CCM mode.

[0038] The above description is only a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A fast adaptive adjustment circuit for zero-crossing detection of inductor current, characterized in that: The circuit includes a voltage comparison unit at the SW terminal, an adaptive delay unit, an adaptive voltage adjustment unit, and a DCM / CCM mode determination unit. The adaptive voltage regulation unit mainly consists of AMP, error amplifier EA, and capacitors C1 and C2. During the time when IL_zero is high, C1 is charged to obtain V_C1. At the same time, error amplifier EA amplifies the difference between Vref1 and V_C1 and obtains the output voltage V_tune by charging and discharging C2. When IL_zero is low, NM9 is disconnected and the voltage V_tune is held through C2 to regulate the current I3 through PM8. AMP is connected in unity gain form to reset the voltage of V_C1 to Vref1 when the IL_zero signal is low. When set to PFM-PWM mode and the load current is small, the circuit is in non-continuous conduction DCM operating mode, four units are normal work, SW end voltage detection unit to determine I L zero, when detecting I L zero, the comparator flips, and the adaptive voltage regulation unit adaptively adjusts the reference voltage of the comparator within the delay time generated by the adaptive delay unit; When the load current is large, the DCM CCM mode judgment circuit causes the DCM signal to flip from high to low and enter the continuous conduction CCM mode, while turning off the adaptive delay unit and the adaptive voltage regulation unit. When the switching frequency of the current-mode PWM-PFM synchronous rectifier DC-DC buck converter is stable, the circuit is set to forced PWM mode. In forced PWM mode, the inductor current is allowed to be negative. At this time, the voltage comparison unit at the SW terminal works normally, while the adaptive delay unit, adaptive voltage regulation unit, and DCM CCM mode judgment unit do not work. The resistor is shorted through the MOSFET, so that the function of the voltage comparison unit at the SW terminal becomes detecting the minimum current limit value of the inductor current.

2. The fast adaptive adjustment inductor current zero-crossing detection circuit according to claim 1, characterized in that: The SW terminal voltage detection unit has three different operating modes depending on the given FPWM signal and the load conditions: DCM mode in PFM-PWM mode, CCM mode in PFM-PWM mode, and forced PWM mode.

3. The fast adaptive adjustment inductor current zero-crossing detection circuit according to claim 1, characterized in that: When the load is large, the average value of the inductor current is large, and the inductor current no longer crosses zero. The DCM CCM mode judgment unit outputs CCM at a high level, and at this time, the adaptive delay unit and the adaptive voltage regulation unit are turned off. When the system load triggers the zero-crossing detection signal, the DCM CCM judgment module makes the CCM output low level, and the adaptive delay unit and the adaptive voltage regulation unit are turned back on.

4. The fast adaptive adjustment inductor current zero-crossing detection circuit according to claim 1, characterized in that: The mode selection signal FPWM, which is given by the user, determines whether to select FPWM mode. When FPWM is set to a high level, FPWM mode is entered.

5. The fast adaptive adjustment inductor current zero-crossing detection circuit according to claim 1, characterized in that: The voltage comparison unit at the SW terminal first obtains VP and VN through a current-to-voltage structure, and then compares VP and VN through the comparator COMP. The current bias section adopts a cascode structure, using NM3 and NM5 transistors to shield the influence of power supply voltage changes on NM4 and NM6 transistors, reducing the influence of channel length modulation effect on bias current. When the SW voltage changes, the source voltage of NM4 will change accordingly, thus causing I1 to change. The relationship between I1 and I4 is converted into the relationship between VP and VN through R2 and R3. COMP is a gate input voltage comparator. The comparator internally determines whether the output of COMP_out is high or low by comparing the magnitudes of VP and VN.

6. The fast adaptive adjustment inductor current zero-crossing detection circuit according to claim 1, characterized in that: The adaptive delay unit mainly consists of an amplifier composed of NM1, NM2, PM1, and PM2, and an adjustable delay unit composed of NM3, PM5, and C1. NM2 is a common-gate type with source input and drain output. I1 and R1 transfer the change of SW voltage to VGATE, and then the common-source amplification of the load through the PMOS in diode configuration composed of NM1 and PM2 is converted into the gate voltage of PM4, thereby controlling the change of current I3. By controlling the magnitude of I3, the charging time of PM5 to C1 is controlled, thereby controlling the delay time.

7. The fast adaptive adjustment inductor current zero-crossing detection circuit according to claim 1, characterized in that: The DCM / CCM mode determination unit implements frequency division counting through the cascading of four D flip-flops with reset function. DFF2-DFF4 output Q1-Q4 respectively, and then the AND logic gate identifies whether Q1-Q4 are all high level, thus determining that the system has entered DCM mode. When the load current increases, the inductor current no longer crosses zero, the reset signal is low level, and the counter outputs Q1-Q4 are all pulled low, thus determining that the system has exited DCM mode and entered CCM mode.

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