A data sending method and device, a data receiving method and device, an electronic device and a medium

Abstract

Embodiments of the present application disclose a data sending method and device, a data receiving method and device, electronic equipment and a medium, comprising: obtaining original to-be-sent data and unique mark data; wherein the original to-be-sent data comprises valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format; determining a first invalid data array of the original to-be-sent data; marking target invalid data in the first invalid data array according to the unique mark data to obtain mark data; and sending the mark data to a data receiving party; wherein the data receiving party is configured to filter all valid data from the mark data according to the unique mark data. The technical solution of the embodiments of the present application can reduce the data cache cost of the sending party and improve the real-time performance and reliability of data transmission.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data transmission and data reception method, apparatus, electronic device and medium. Background Technology

[0002] Currently, parallel data transmission primarily uses CPRI (Common Public Radio Interface) and Ethernet packet formats. CPRI format data transmission is suitable for transmitting data in a continuous fixed frame format in the communications field, while Ethernet packet format data transmission is suitable for transmitting bursty data blocks.

[0003] In the process of developing this invention, the inventors discovered that the data blocks collected by the data acquisition device are often bursty data blocks, which contain both protected data and invalid data. Therefore, there are problems of data processing delay and high data caching overhead costs during data transmission and reception. Summary of the Invention

[0004] This invention provides a data sending and receiving method, apparatus, electronic device, and medium that can reduce the data buffering overhead cost of the sender and improve the real-time performance and reliability of data transmission.

[0005] According to one aspect of the present invention, a data transmission method is provided, comprising:

[0006] Obtain the original data to be sent and the unique identifier data; wherein, the original data to be sent includes valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format;

[0007] Determine the first invalid data array of the original data to be sent;

[0008] The target invalid data in the first invalid data array is marked according to the unique marker data to obtain the marked data;

[0009] The tagging data is sent to a data receiver; wherein the data receiver is used to filter and store all valid data from the tagging data based on the unique tagging data.

[0010] According to another aspect of the present invention, a data receiving method is provided, comprising:

[0011] Receive tag data sent by the data sender; wherein the tag data includes unique tag data, valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format;

[0012] Identify the first invalid data array in the marked data;

[0013] The target invalid data in the first invalid data array is determined based on the unique marker data;

[0014] Based on the target invalid data, filter and store all valid data from the labeled data.

[0015] According to another aspect of the present invention, a data transmission apparatus is provided, comprising:

[0016] The data acquisition module is used to acquire raw data to be sent and unique marker data; wherein, the raw data to be sent includes valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format;

[0017] The first invalid first data array determination module is used to determine the invalid first data array of the original data to be sent.

[0018] The target invalid data marking module is used to mark the target invalid data in the first invalid data array according to the unique marking data, so as to obtain marked data;

[0019] A tag data sending module is used to send the tag data to a data receiver; wherein the data receiver is used to filter and store all valid data from the tag data based on the unique tag data.

[0020] According to another aspect of the present invention, a data receiving device is provided, comprising:

[0021] A tag data receiving module is used to receive tag data sent by a data sender; wherein the tag data includes unique tag data, valid data, and invalid data, and the valid data and the invalid data are arranged in a fixed format;

[0022] The second invalid first-order data array determination module is used to determine the invalid first-order data array in the marked data;

[0023] The target invalid data determination module is used to determine the target invalid data in the first invalid data array based on the unique marker data.

[0024] The effective data storage module is used to filter and store all effective data from the marked data based on the target invalid data.

[0025] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0026] At least one processor; and

[0027] A memory communicatively connected to the at least one processor; wherein,

[0028] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the data transmission method as described in any embodiment of the present invention, or to implement the data reception method as described in the embodiments of the present invention.

[0029] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement the data transmission method as described in any embodiment of the present invention, or to implement the data reception method as described in the embodiments of the present invention.

[0030] The technical solution of this invention involves the data sender acquiring the original data to be sent and unique marker data, determining the first invalid data array of the original data to be sent, and then marking the target invalid data in the first invalid data array according to the unique marker data, thus obtaining marked data and sending it to the data receiver. Upon receiving the marked data, the data receiver determines the first invalid data array in the marked data, identifies the target invalid data in the first invalid data array based on the unique marker data, and then filters and stores all valid data from the marked data based on the target invalid data. This solves the problems of large data caching overhead and high latency during data transmission, reduces the data caching overhead cost for the sender, and improves the real-time performance and reliability of data transmission.

[0031] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of a data transmission method provided in Embodiment 1 of the present invention;

[0034] Figure 2 This is a flowchart of a data transmission method provided in Embodiment 2 of the present invention;

[0035] Figure 3 This is a schematic diagram of a baseband echo data timing diagram provided in Embodiment 2 of the present invention;

[0036] Figure 4 This is a flowchart of a baseband echo data transmission method provided in Embodiment 2 of the present invention;

[0037] Figure 5 This is a schematic diagram of a 10G rate basic frame data format provided in Embodiment 2 of the present invention;

[0038] Figure 6 This is a flowchart of a data receiving method provided in Embodiment 3 of the present invention;

[0039] Figure 7 This is a flowchart of a data receiving method provided in Embodiment 4 of the present invention;

[0040] Figure 8 This is a schematic diagram of a baseband echo data reception method provided in Embodiment 4 of the present invention;

[0041] Figure 9 This is a schematic diagram of a data storage processing flow provided in Embodiment 4 of the present invention;

[0042] Figure 10 This is a schematic diagram of a data transmission device provided in Embodiment 5 of the present invention;

[0043] Figure 11 This is a schematic diagram of a data receiving device provided in Embodiment Six of the present invention;

[0044] Figure 12 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] Example 1

[0048] Figure 1 This is a flowchart of a data transmission method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where raw data to be transmitted is transmitted with a low data buffer size. The method can be executed by a data transmission device, which can be implemented in software and / or hardware, and is generally integrated into an electronic device. This electronic device can be a terminal device or a server device. The present invention does not limit the specific type of electronic device. Correspondingly, as... Figure 1 As shown, the method includes the following operations:

[0049] S110. Obtain the original data to be sent and the unique tag data; wherein, the original data to be sent includes valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format.

[0050] The original data to be transmitted can be communication signal data that requires data transmission processing. The unique identifier data can be identification data used to mark valid data within the original data to be transmitted. It should be noted that the unique identifier data only performs data marking processing and will not be misjudged as valid data by the data receiver. Valid data can be valid transmission data within the original data to be transmitted. Invalid data can be guard interval data within the original data to be transmitted.

[0051] In this embodiment of the invention, the original data to be transmitted and the unique marker data can be obtained through data acquisition or by a data acquisition instrument. The original data to be transmitted can be radio frequency signal data that needs to be processed for data transmission, or baseband echo signal data that needs to be processed for data transmission, etc. This embodiment of the invention does not limit the data type of the original data to be transmitted. Valid data and invalid data in the original data to be transmitted are arranged according to a fixed data length format, forming valid data blocks and invalid data blocks. That is, the distribution of valid data and invalid data follows a certain pattern. Invalid data blocks can be guard intervals between valid data blocks, such as guard intervals between transmitting antennas, guard intervals between frequency switching, or invalid data introduced by crosstalk, etc. The unique marker data can be data that cannot be misjudged as valid data and can uniquely identify valid data. Optionally, the unique marker data can be synchronization signal data. In this embodiment of the invention, the specific data type of the unique marker data is also not limited.

[0052] S120. Determine the first invalid data array of the original data to be sent.

[0053] The first invalid data array can be the first consecutively distributed invalid data in the original data to be sent, collected by the data acquisition device.

[0054] In this embodiment of the invention, the original data to be sent can be composed of alternating valid and invalid data. The first consecutive invalid data block of the original data to be sent can be used as the first invalid data array of the original data to be sent. By determining the first invalid data array, subsequent steps can mark the invalid data, thereby obtaining the target valid data.

[0055] S130. Mark the target invalid data in the first invalid data array according to the unique marker data to obtain the marker data.

[0056] Specifically, the target invalid data can be the invalid data in the first invalid data array that needs to be uniquely marked. The marked data can be the data to be sent that has been marked with marking information after marking processing.

[0057] In this embodiment of the invention, any invalid data point can be selected from the first invalid data array as the target invalid data, and the target invalid data is marked according to the unique marker data to obtain marked data. It should be noted that the relative positions of valid data in the original data to be sent can be determined based on the obtained marked data, and then the data receiver can filter and store all valid data from the marked data based on the unique marker data. Optionally, the last invalid data point in the first invalid data array can be marked as the target invalid data, so that the data receiver can quickly locate the valid data in the marked data.

[0058] S140. The tag data is sent to the data receiver; wherein the data receiver is used to filter and store all valid data from the tag data based on the unique tag data.

[0059] In this embodiment of the invention, the data sender can send the tagged data to the data receiver. The data receiver can filter out all the valid data from the received tagged data based on the unique tagged data and store the valid data. This solves the problem of processing delay during data transmission, saves data costs, and improves the efficiency of data transmission.

[0060] The technical solution of this invention involves the data sender obtaining the original data to be sent and the unique marker data, determining the first invalid data array of the original data to be sent, and then marking the target invalid data in the first invalid data array according to the unique marker data, obtaining the marked data and sending it to the data receiver. This solves the problems of large data caching overhead and large latency during data transmission, reduces the data caching overhead cost of the sender, and improves the real-time performance and reliability of data transmission.

[0061] Example 2

[0062] Figure 2 This is a flowchart of a data transmission method provided in Embodiment 2 of the present invention. This embodiment is a specific modification based on the above embodiment, and provides specific optional implementation methods for acquiring and transmitting marker data. Correspondingly, as... Figure 2 As shown, the method in this embodiment may include:

[0063] S210, Obtain the original data to be sent and the unique tag data.

[0064] S220. Determine the first invalid data array of the original data to be sent.

[0065] S230. Determine the target data marker position in the first invalid data array.

[0066] The target data marking location can be used to determine the location of invalid target data that needs to be uniquely marked.

[0067] In this embodiment of the invention, the original data to be sent and unique marker data are first obtained, and the first invalid data array of the original data to be sent is determined. Further, the target data marker position in the first invalid data array is determined, that is, the target data marker position is determined within the first consecutive invalid data block of the original data to be sent. Optionally, any position of invalid data within the first consecutive invalid data block of the original data to be sent can be used as the target data marker position; this embodiment of the invention does not limit the target data marker position.

[0068] S240. The invalid data at the target data mark position in the first invalid data array is taken as the target invalid data.

[0069] S250, Use the unique marker data to mark the target invalid data.

[0070] Optionally, the unique identifier data may include synchronization signal data. When synchronization signal data is used as the unique identifier data, the unique identifier data may be two consecutive 30-bit synchronization sequence signal data.

[0071] Correspondingly, invalid data at the target data marking position determined in the above steps can be used as target invalid data, and the target invalid data can be marked using synchronization signal data, so that the relative position of valid data in the original data to be sent can be determined based on the marked data.

[0072] S260. The marked data is sent to the data receiver.

[0073] In an optional embodiment of the present invention, the original data to be transmitted may include baseband echo data; the step of sending the marked data to the data receiver may include: performing IQ mapping on the marked data to obtain IQ mapped data; performing CPRI framing processing on the IQ mapped data to obtain CPRI framed data; performing clock domain conversion processing on the CPRI framed data to obtain clock converted data; performing SERDES serial processing on the clock converted data to obtain serial processed data; and sending the serial processed data to the data receiver.

[0074] The baseband echo data can be a 0-frequency signal containing both I and Q components. IQ mapping is a mapping process that converts a 30-bit wide data stream into a 32-bit wide data stream. IQ-mapped data can be 32-bit wide data obtained from baseband echo data after IQ mapping processing. CPRI framing processing is a framing method that converts IQ-mapped data into CPRI framing data. CPRI framing data can be framed data obtained from IQ-mapped data after CPRI framing processing. Clock domain conversion processing is a processing method that converts data format transmitted in one clock domain into data format that can be transmitted in another clock domain. Clock-converted data can be signal data obtained from CPRI framing data after clock domain processing. SERDE (serializer) serial processing is a processing method that converts clock-converted data into serial data. Serialized data can be signal data obtained from clock-converted data after SERDE serial processing.

[0075] In this embodiment of the invention, the example of baseband echo data being the original data to be transmitted is provided. First, baseband echo data and synchronization signal data are acquired, and the first invalid data array and the target data marker position within the first invalid data array are determined. Further, the invalid data at the target data marker position in the first invalid data array can be used as the target invalid data, and the synchronization signal data is used to mark the target invalid data, resulting in marked data. Then, IQ mapping processing is performed on the marked data to obtain IQ mapped data. For example, a 30-bit wide marked data stream can be converted to a 32-bit wide IQ mapped data stream. The obtained IQ mapped data is then subjected to CPRI framing processing to obtain framed data, which is essentially a basic frame of one unit length. Further, the obtained framed data undergoes clock domain conversion processing to obtain clock-converted data, and then the clock-converted data is serialized through SERDEs to obtain serially processed data, which can then be sent to the data receiver.

[0076] In a specific example, we will use baseband echo data as the data to be transmitted. Figure 3 This is a schematic diagram of a baseband echo data timing diagram provided in Embodiment 2 of the present invention, as shown below. Figure 3 As shown, CLK (Clock signal) can represent a clock signal with a fixed period. da_syn signal can represent a unique synchronization signal capable of overcoming interference. da_data signal can be a baseband echo data signal, which may include valid and invalid data. Figure 4 This is a flowchart of a baseband echo data transmission method provided in Embodiment 2 of the present invention, as follows: Figure 4As shown, firstly, baseband echo data and synchronization signal data are acquired, and the first invalid data array and the target data marker position within the first invalid data array are determined. Further, the invalid data at the target data marker position in the first invalid data array can be used as the target invalid data, and then the synchronization signal data is used to mark the target invalid data. That is, the synchronization signal data occupies two cycles to obtain the marked data. The obtained marked data undergoes IQ mapping processing to obtain IQ mapped data. Further, the obtained IQ mapped data undergoes CPRI framing processing to obtain framed data. The framed data undergoes clock domain conversion processing to obtain clock-converted data, and then the clock-converted data undergoes SERDES processing to obtain serial processing data.

[0077] Optionally, we will use a 10G optical port rate as an example for explanation. Figure 5 This is a schematic diagram of a 10G rate basic frame data format provided in Embodiment 2 of the present invention. In a specific example, such as... Figure 5 As shown, if the operating clock frequency is 250MHz, a CPRI basic frame needs to transmit 2048 bits of data, which can include 128 bits of control word and 1920 bits of AXC format data. Calculations and analysis show that a 32-bit serial data width is most reasonable for SerDes, therefore requiring 64 cycles for transmission.

[0078] The technical solution of this invention first obtains the original data to be sent and unique marker data, determines the first invalid data array of the original data to be sent and the target data marker position of the first invalid data array, then takes the invalid data at the target data marker position in the first invalid data array as the target invalid data, finally marks the target invalid data with unique marker data, and sends the marked data to the data receiver. This solves the problems of large buffer overhead and large latency during data transmission, reduces data buffer overhead costs, and improves the real-time performance and reliability of data transmission.

[0079] Example 3

[0080] Figure 6 This is a flowchart of a data receiving method provided in Embodiment 3 of the present invention. This embodiment is applicable to the case of low-latency reception of raw data to be sent. The method can be executed by a data receiving device, which can be implemented by software and / or hardware, and is generally integrated into an electronic device. The electronic device can be a terminal device or a server device. The embodiments of the present invention do not limit the specific device type of the electronic device. Accordingly, as... Figure 6 As shown, the method includes the following operations:

[0081] S310. Receive tag data sent by the data sender; wherein the tag data may include unique tag data, valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format.

[0082] When the data sender transmits tagged data to the data receiver, the data receiver can typically receive the tagged data. For example, the tagged data can be baseband echo data tagged with synchronization signal data. The tagged data can consist of valid and invalid data arranged in a fixed format.

[0083] S320. Determine the first invalid data array in the marked data.

[0084] S330. Determine the target invalid data in the first invalid data array based on the unique marker data.

[0085] Correspondingly, the data receiver can receive and inspect the tagged data, and determine the target invalid data among the first invalid data values ​​based on the uniquely tagged data. This allows the receiver to filter out valid data from the tagged data based on the target invalid data. It is understood that the target invalid data contains tagged information, which the data receiver can scan and quickly locate based on.

[0086] S340. Based on the target invalid data, filter and store all valid data from the marked data.

[0087] In this embodiment of the invention, the target invalid data obtained from the above steps can be used to filter the marked data received by the data receiver, obtain all valid data in the marked data and store it, so as to solve the problem of data sending and receiving delay during data transmission, save data transmission costs and improve data transmission reliability.

[0088] The technical solution of this invention involves the data sender obtaining the original data to be sent and unique marker data, determining the first invalid data array of the original data to be sent, and then marking the target invalid data in the first invalid data array according to the unique marker data, thus obtaining marked data and sending it to the data receiver. Upon receiving the marked data, the data receiver determines the first invalid data array in the marked data, identifies the target invalid data in the first invalid data array based on the unique marker data, and then filters and stores all valid data from the marked data based on the target invalid data. This solves the problems of large data caching overhead and high latency during data transmission, reduces data caching costs, and improves the real-time performance and reliability of data transmission.

[0089] Example 4

[0090] Figure 7 This is a flowchart of a data receiving method provided in Embodiment 4 of the present invention. This embodiment is a specific modification of the above embodiments, and provides specific optional implementation methods for filtering and storing valid data based on target invalid data. Correspondingly, as... Figure 7 As shown, the method in this embodiment may include:

[0091] S410, Receive the tag data sent by the data sender.

[0092] In an optional embodiment of the present invention, the marker data may include baseband echo data; after receiving the marker data sent by the data sender, the method may further include: performing SERDEs deserialization on the marker data to obtain deserialized data; performing clock domain inverse conversion on the deserialized data to obtain clock inverse conversion data; performing CPRI synchronization deframe processing on the clock inverse conversion data to obtain CPRI deframed data; and performing IQ demapping on the CPRI deframed data to obtain IQ demapped data.

[0093] SerDes deserialization can be a method for serial-to-parallel conversion. Deserialized data can be signal data obtained by processing marked data through SerDes deserialization. Reverse clock domain conversion can be a method for converting the data format transmitted in the current clock domain to the data format transmitted in the original clock domain. Reverse clock conversion data can be signal data obtained by processing deserialized data through reverse clock domain conversion. CPRI synchronous deframe processing can be a deframe processing method for converting reverse clock conversion data into CPRI deframed data. CPRI deframed data can be signal data obtained by processing reverse clock conversion data through CPRI synchronous deframe processing. IQ demapping can be a demapping processing method for converting CPRI deframed data into IQ demapped data. IQ demapped data can be signal data obtained by processing CPRI deframed data through IQ demapping.

[0094] In this embodiment of the invention, after receiving the marked data, the data receiver can perform serdes deserialization processing on the marked data to obtain deserialized data, then perform clock domain inverse conversion processing on the deserialized data to obtain clock inverse conversion data, then perform CPRI synchronous deframe processing on the clock inverse conversion data to obtain CPRI deframed data, and finally perform IQ demapping on the CPRI deframed data to obtain IQ demapped data.

[0095] Figure 8 This is a schematic diagram of a baseband echo data reception method provided in Embodiment 4 of the present invention. In a specific example, such as... Figure 8As shown, the example illustrates the process using baseband echo data as the marker data. After receiving the baseband echo data from the sender, the receiver can perform SERDES deserialization on the baseband echo data to obtain deserialized data. Then, the deserialized data undergoes clock domain inverse conversion to obtain clock-inverse converted data. Further, the clock-inverse converted data undergoes CPRI synchronization deframe processing to obtain CPRI deframed data, and then the CPRI deframed data undergoes IQ demapping processing to obtain IQ demapped data.

[0096] S420. Determine the first invalid data array in the marked data.

[0097] S430. Determine the target data marker position of the unique marker data in the first invalid data array.

[0098] S440. The invalid data at the target data mark position in the first invalid data array is taken as the target invalid data.

[0099] The target data marker position can represent the position of invalid data within the marker data.

[0100] Accordingly, the data receiver can determine the first invalid data array in the marked data based on the location of the uniquely marked data and the distribution pattern between valid and invalid data, and obtain the position of the invalid data in the marked data as the target data mark position. Further, based on the target data mark position obtained in the above steps, invalid data in the marked data can be determined, and the invalid data at the target data mark position in the first invalid data array can be taken as the target invalid data.

[0101] S450. Based on the target invalid data, filter and store all valid data from the marked data.

[0102] In an optional embodiment of the present invention, filtering and storing all valid data from the marked data based on the target invalid data may include: determining a fixed arrangement format for the valid data and the invalid data; generating a valid bit vector based on the fixed arrangement format and the target invalid data at the target data mark position in the first invalid data array; and filtering and storing all valid data from the marked data based on the valid bit vector.

[0103] The valid bit vector can be an identifier vector used to represent valid data. For example, when the valid bit vector is 0000111100001111, it means that bits 0-3 and 8-11 are invalid data blocks, and bits 4-7 and 12-15 are valid data blocks.

[0104] In this embodiment of the invention, the valid data in the marked data can be a continuous block of valid data with a width of 30 bits, and the invalid data can be a continuous block of invalid data with a width of 30 bits. Valid and invalid data can be interleaved within the marked data. First, a fixed arrangement format of the valid and invalid data in the marked data received by the data receiver can be determined. Then, based on the target invalid data's marker position in the first invalid data array obtained from the above steps and the fixed arrangement format, a valid bit vector can be generated. This valid bit vector can then be used to filter out all valid data from the marked data and store it.

[0105] In a specific example, suppose the valid and invalid data in the marked data are both 4-bit blocks. The marked data can be obtained by interleaving valid and invalid data blocks. Furthermore, suppose the target invalid data's target data marker position in the first invalid data array can be the position preceding the valid data block. Therefore, based on the target invalid data's target data marker position in the first invalid data array and the fixed arrangement format, the value of the valid bit vector can be determined to be 0000111100001111.

[0106] In an optional embodiment of the present invention, generating a valid bit vector based on the fixed arrangement format and the target invalid data at the target data marker position in the first invalid data array may include: generating an initial bit vector based on the length of the marked data; determining the first valid data array of the marked data based on the fixed arrangement format and the target invalid data at the target data marker position in the first invalid data array; determining the remaining valid data array of the marked data based on the fixed arrangement format and the first valid data array; determining the bits corresponding to the first valid data array and the remaining valid data array as target bits; and setting the data at the target bit position in the initial bit vector as the target bit data.

[0107] The initial bit vector can be a bit vector of the same length as the marked data, with all bits set to default values ​​(e.g., 0). The first valid data array can be the first consecutive valid data digits in the marked data. The remaining valid data array can be all valid data in the marked data except for the first valid data digit. The target bit can be the bit representing the remaining valid data array. The target bit data can be the marked data at the target bit position.

[0108] In this embodiment of the invention, an initial bit vector of the same length as the marked data, with all bits set to default values ​​(e.g., 0), can be generated based on the marked data received by the data receiver. The first valid data array of the marked data can be obtained based on the target data marker position of the target invalid data in the first invalid data array and a fixed arrangement format. Then, based on the first valid data array and the fixed arrangement format, all valid data in the marked data except for the first valid data value, i.e., the remaining valid data array, can be obtained. Further, the bit corresponding to the first valid data array and the remaining valid data array can be determined based on the first valid data array and the remaining valid data array, and used as the target bit. Finally, the data at the target bit position in the initial bit vector is set as the target bit data to achieve the filtering and storage of valid data.

[0109] In a specific example, assuming the length of the marked data can be 16 bits, an initial bit vector of size 16 bits can be generated. The first valid data array of the marked data is determined based on the target invalid data's marker position within the first invalid data array. That is, if the target invalid data's marker position is one position before the first valid data array, then the next position of the target invalid data can be determined as the first valid data array. Furthermore, the remaining valid data array of the marked data can be obtained based on the fixed arrangement of valid and invalid data. Since both valid and invalid data are 4 bits long, the last 5 positions of the target invalid data constitute the second valid data array, and so on, determining the remaining valid data array of the marked data. Further, the bits corresponding to the first valid data array and the remaining valid data arrays—that is, all valid data arrays of the marked data—are determined as target bits, and the data at these bits is used as the target bit data. For example, if the valid data array of the marked data has bits 4-7 and bits 12-15, then the data at bits 4-7 and bits 12-15 can be used as the target bit data for transmission and storage.

[0110] Figure 9 This is a schematic diagram of a data storage processing flow provided in Embodiment 4 of the present invention. In a specific example, such as... Figure 9As shown, an initial bit vector with all bits set to 0 of the same length as the marked data can be generated based on the marked data received by the data receiver. The first valid data array of the marked data can be obtained based on the target invalid data's marker position in the first invalid data array and its fixed arrangement. Then, based on the first valid data array and the fixed arrangement, all valid data in the marked data except for the first valid data value can be obtained, i.e., the remaining valid data array. Further, the corresponding bits in the first and remaining valid data arrays can be determined, and the data at the target bit position in the initial bit vector can be set as the target bit data to achieve filtering of valid data. Finally, the valid data can be sent to a FIFO (First Input First Output) for bit width conversion, and the converted valid data can be sent to DDR (Double Data Rate Synchronous Dynamic Random Access Memory) for storage.

[0111] The technical solution of this invention involves the data sender acquiring the original data to be sent and unique marker data, determining the first invalid data array of the original data to be sent, and then marking the target invalid data in the first invalid data array according to the unique marker data, thus obtaining marked data and sending it to the data receiver. Upon receiving the marked data, the data receiver determines the first invalid data array in the marked data, identifies the target invalid data in the first invalid data array based on the unique marker data, and then filters and stores all valid data from the marked data based on the target invalid data. This solves the problems of large data caching overhead and high latency during data transmission, reduces the data caching overhead cost for the sender, and improves the real-time performance and reliability of data transmission.

[0112] Example 5

[0113] Figure 10 This is a schematic diagram of a data transmission device provided in Embodiment 5 of the present invention, as shown below. Figure 10 As shown, the device includes: a data acquisition module 510, a first invalid data array determination module 520, a target invalid data marking module 530, and a marked data sending module 540, wherein:

[0114] The data acquisition module 510 is used to: acquire raw data to be sent and unique marker data; wherein, the raw data to be sent includes valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format;

[0115] The first invalid data array determination module 520 is used to: determine the first invalid data array of the original data to be sent;

[0116] The target invalid data marking module 530 is used to: mark the target invalid data in the first invalid data array according to the unique marking data, and obtain the marked data;

[0117] The tag data sending module 540 is used to: send the tag data to a data receiver; wherein the data receiver is used to filter and store all valid data from the tag data based on the unique tag data.

[0118] The technical solution of this invention involves the data sender obtaining the original data to be sent and the unique marker data, determining the first invalid data array of the original data to be sent, and then marking the target invalid data in the first invalid data array according to the unique marker data, obtaining the marked data and sending it to the data receiver. This solves the problems of large data caching overhead and large latency during data transmission, reduces the data caching overhead cost of the sender, and improves the real-time performance and reliability of data transmission.

[0119] Optionally, the target invalid data marking module 530 is specifically used to: determine the target data marking position in the first invalid data array; take the invalid data at the target data marking position in the first invalid data array as the target invalid data; and mark the target invalid data using the unique marking data.

[0120] Optionally, the original data to be transmitted includes baseband echo data. The marker data transmission module 540 is specifically used for: performing IQ mapping on the marker data to obtain IQ mapped data; performing CPRI framing processing on the IQ mapped data to obtain CPRI framed data; performing clock domain conversion processing on the CPRI framed data to obtain clock converted data; performing SERDES serial processing on the clock converted data to obtain serial processed data; and sending the serial processed data to the data receiver.

[0121] Optionally, the unique marker data may include synchronization signal data.

[0122] The data transmission device described above can execute the data transmission method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the data transmission method provided in any embodiment of the present invention.

[0123] Example 6

[0124] Figure 11 This is a schematic diagram of a data receiving device provided in Embodiment Six of the present invention, as shown below. Figure 11 As shown, the device includes: a marker data receiving module 610, a second invalid first-digit data array determination module 620, a target invalid data determination module 630, and a valid data storage module 640, wherein:

[0125] The tag data receiving module 610 is used to: receive tag data sent by a data sender; wherein the tag data includes unique tag data, valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format;

[0126] The second invalid first data array determination module 620 is used to: determine the invalid first data array in the marked data;

[0127] The target invalid data determination module 630 is used to: determine the target invalid data in the first invalid data array based on the unique marker data;

[0128] The effective data storage module 640 is used to: filter and store all effective data from the marked data based on the target invalid data.

[0129] The technical solution of this invention involves the data sender acquiring the original data to be sent and unique marker data, determining the first invalid data array of the original data to be sent, and then marking the target invalid data in the first invalid data array according to the unique marker data, thus obtaining marked data and sending it to the data receiver. Upon receiving the marked data, the data receiver determines the first invalid data array in the marked data, identifies the target invalid data in the first invalid data array based on the unique marker data, and then filters and stores all valid data from the marked data based on the target invalid data. This solves the problems of large data caching overhead and high latency during data transmission, reduces the data caching overhead cost for the sender, and improves the real-time performance and reliability of data transmission.

[0130] Optionally, the target invalid data determination module 630 is specifically used to: determine the target data mark position of the unique marker data in the first invalid data array; and take the invalid data at the target data mark position in the first invalid data array as the target invalid data.

[0131] Optionally, the effective data storage module 640 is specifically used for: determining a fixed arrangement format for the effective data and the invalid data; generating a valid bit vector based on the fixed arrangement format and the target invalid data in the target data marker position of the first invalid data array; and filtering and storing all the effective data from the marked data based on the valid bit vector.

[0132] Optionally, the effective data storage module 640 is specifically configured to: generate an initial bit vector based on the length of the marked data; determine the first valid data array of the marked data based on the fixed arrangement format and the target data mark position of the target invalid data in the first valid data array; determine the remaining valid data array of the marked data based on the fixed arrangement format and the first valid data array; determine the bit positions corresponding to the first valid data array and the remaining valid data array as target bit positions; and set the data at the target bit position in the initial bit vector as the target bit data.

[0133] Optionally, the data receiving device further includes a deframe processing module, specifically used for: performing serdes deserialization processing on the marked data to obtain deserialized data; performing clock domain inverse conversion processing on the deserialized data to obtain clock inverse conversion data; performing CPRI synchronization deframe processing on the clock inverse conversion data to obtain CPRI deframed data; and performing IQ demapping on the CPRI deframed data to obtain IQ demapped data.

[0134] The above-described data receiving device can execute the data receiving method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the data receiving method provided in any embodiment of the present invention.

[0135] Example 7

[0136] Figure 12 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0137] like Figure 12As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0138] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0139] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as data transmission methods or data reception methods.

[0140] In some embodiments, the data transmission method or data reception method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the data transmission method or data reception method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the data transmission method or data reception method by any other suitable means (e.g., by means of firmware).

[0141] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0142] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0143] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0144] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0145] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0146] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

Claims

1. A data transmission method, characterized in that, Applied to the data sender, including: Obtain the original data to be sent and the unique identifier data; wherein, the original data to be sent includes valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format; Determine the first invalid data array of the original data to be sent; The target invalid data in the first invalid data array is marked according to the unique marker data to obtain the marked data; The tagging data is sent to a data receiver; wherein the data receiver is used to filter and store all valid data from the tagging data based on the unique tagging data.

2. The method according to claim 1, characterized in that, The step of marking the target invalid data in the first invalid data array according to the unique marker data to obtain the marked data includes: Determine the target data marker position in the first invalid data array; The invalid data at the target data marker position in the first invalid data array is taken as the target invalid data; The target invalid data is marked using the unique marker data.

3. The method according to claim 1, characterized in that, The raw data to be transmitted includes baseband echo data in CPRI format; Sending the tagged data to the data receiver includes: Perform IQ mapping on the labeled data to obtain IQ mapped data; The IQ mapping data is subjected to CPRI framing processing to obtain CPRI framing data; The CPRI frame data is subjected to clock domain conversion processing to obtain clock-converted data; The clock conversion data is subjected to SERDE serial processing to obtain serial processed data; The serially processed data is sent to the data receiver.

4. The method according to any one of claims 1-3, characterized in that, The unique marker data includes synchronization signal data.

5. A data receiving method, characterized in that, Applied to the data receiver, including: Receive tag data sent by the data sender; wherein the tag data includes unique tag data, valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format; Identify the first invalid data array in the marked data; The target invalid data in the first invalid data array is determined based on the unique marker data; Based on the target invalid data, filter and store all valid data from the labeled data.

6. The method according to claim 5, characterized in that, The step of determining the target invalid data in the first invalid data array based on the unique marker data includes: Determine the target data marker position of the unique marker data in the first invalid data array; The invalid data at the target data mark position in the first invalid data array is taken as the target invalid data.

7. The method according to claim 5, characterized in that, The step of filtering and storing all valid data from the labeled data based on the target invalid data includes: Determine a fixed arrangement format for the valid and invalid data; A valid bit vector is generated based on the fixed arrangement format and the target invalid data in the first invalid data array, according to the target data marker position of the target invalid data. All valid data are filtered and stored from the marked data based on the valid bit vector.

8. The method according to claim 7, characterized in that, The step of generating a valid bit vector based on the fixed arrangement format and the target invalid data at the target data marker position in the first invalid data array includes: Generate an initial bit vector based on the length of the marked data; The first valid data array of the marked data is determined according to the fixed arrangement format and the target invalid data in the first invalid data array; The remaining valid data array of the marked data is determined based on the fixed arrangement format and the first valid data array. The bits corresponding to the first valid data array and the remaining valid data array are determined as the target bits; Set the data at the target bit position in the initial bit vector as the target bit data.

9. The method according to claim 5, characterized in that, The labeled data includes baseband echo data; Following the marker data sent by the receiving data sender, the following is also included: The marked data is subjected to serdes deserialization processing to obtain deserialized data; The deserialized data is subjected to clock domain inverse conversion to obtain clock inverse converted data; The clock inversion data is subjected to CPRI synchronization deframe processing to obtain CPRI deframed data; The CPRI deframe data is subjected to IQ demapping to obtain IQ demapped data.

10. The method according to any one of claims 5-9, characterized in that, The unique marker data includes synchronization signal data.

11. A data transmission device, characterized in that, include: The data acquisition module is used to acquire raw data to be sent and unique marker data; wherein, the raw data to be sent includes valid data and invalid data, and the valid data and the invalid data are arranged in a fixed format; The first invalid first data array determination module is used to determine the invalid first data array of the original data to be sent. The target invalid data marking module is used to mark the target invalid data in the first invalid data array according to the unique marking data, so as to obtain marked data; A tag data sending module is used to send the tag data to a data receiver; wherein the data receiver is used to filter and store all valid data from the tag data based on the unique tag data.

12. A data receiving device, characterized in that, include: A tag data receiving module is used to receive tag data sent by a data sender; wherein the tag data includes unique tag data, valid data, and invalid data, and the valid data and the invalid data are arranged in a fixed format; The second invalid first-order data array determination module is used to determine the invalid first-order data array in the marked data; The target invalid data determination module is used to determine the target invalid data in the first invalid data array based on the unique marker data. The effective data storage module is used to filter and store all effective data from the marked data based on the target invalid data.

13. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the data transmission method as described in any one of claims 1-4, or to implement the data reception method as described in any one of claims 5-10.

14. A computer storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute and implement the data transmission method as described in any one of claims 1-4, or the data reception method as described in any one of claims 5-10.

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