A montgomery modular multiplier based on parallel structure and encoding

Abstract

The application discloses a Montgomery modular multiplier based on parallel structure and coding, comprising a pre-computation storage unit, a control unit and two groups of iterative computation modules, the iterative computation module comprising an input selection control unit, a multiplexer, a CSA addition unit, an output shift unit and a register group. The Montgomery modular multiplier adds an additional shift compensation operation, decomposes the cyclic iterative computation of the partial product into two groups of parallel computation, realizes two-way parallel of 2-base Montgomery modular multiplication, and reduces the cycle delay of the original 2-base Montgomery modular multiplication to 1 / 2 of the original. In combination with the characteristics of the two-way parallel design, the input data is re-encoded, the additional shift compensation operation and the partial product are pre-computed, the original three additions are converted into a multiplexing and an addition, the additional area overhead caused by the parallel of the circuit module is optimized, the critical path of the overall operation is shortened, and the Montgomery modular multiplier can be better deployed in a lightweight application scenario.

Description

Technical Field

[0001] This invention belongs to the fields of integrated circuit hardware design and implementation and information security, specifically relating to a Montgomery modular multiplier based on parallel structure and encoding. Background Technology

[0002] Cryptography plays a crucial role in information security. Embedded and System-on-Chip (SoC) devices surrounding Internet of Things (IoT) technology and its applications are currently a hot topic in technological development, with the transfer of sensitive data between IoT devices across different fields being a key issue. For public-key cryptography-based security schemes, high throughput requires the use of hardware modules.

[0003] Commonly used public-key encryption algorithms, such as the digital signature algorithms RSA and ECC, are based on elliptic curve cryptography. However, elliptic curve cryptography suffers from high computational complexity, structural inefficiency, and high resource consumption. Furthermore, these operations are typically performed on large numbers, making them very time-consuming.

[0004] The implementation of elliptic curve cryptography relies on scalar operations such as point addition, point multiplication, and point multiplication on the elliptic curve group. All scalar operations can be decomposed into basic operations over finite fields. Among these, modular multiplication is the key to the overall computation.

[0005] The Montgomery modular multiplier, a widely used modular multiplier, is an efficient and high-performance hardware implementation technique for large-operand modular multiplication. This algorithm uses bit shifting instead of costly division, achieving excellent resource utilization in its hardware implementation. Existing Montgomery modular multipliers mainly employ two implementation methods: one is based on a fixed-width multiplier and adder structure, obtaining the final result through multiple calls to multiplication, addition, and shift operations; the other is based on an adder structure, replacing multiplication with iterative addition, calculating the final result through multiple iterations of addition and shifting. The latter implementation has a simple hardware structure, low resource consumption, and high implementation frequency, but it suffers from significant cycle delay.

[0006] Existing research often focuses on accelerating computation time as a design goal, resulting in very high hardware resource consumption. However, this design philosophy conflicts with the lightweight devices in the embedded system form of current IoT technologies and applications. Therefore, achieving a better speed improvement with less resource consumption is the core issue in realizing lightweight encryption systems.

[0007] In summary, as a core unit in a cryptographic module, the computational efficiency and hardware overhead of the modular multiplier directly impact the overall efficiency and performance of the information security solution. For the traditional Montgomery modular multiplier, current technologies, while achieving lightweight design, still face the challenge of insufficient efficiency. Summary of the Invention

[0008] The purpose of this invention is to overcome the problems of existing Montgomery modular multipliers in lightweight applications and resource-constrained environments, such as slow computation speed, difficulty in parallelization, and high computation cycle latency. This invention provides a 2-base, two-path parallel Montgomery modular multiplier. Combining the features of a two-path parallel design, it employs pre-computation and input data encoding to reduce the partial products involved in the computation, optimize the additional area overhead caused by parallel circuit modules, and shorten the critical path. This allows the design to be better deployed in lightweight application scenarios.

[0009] The objective of this invention is achieved through the following technical solution: a Montgomery modular multiplier based on parallel structure and encoding, comprising a pre-computation storage unit, a control unit, and two sets of iterative calculation modules. The iterative calculation modules include an input selection control unit, a multiplexer, a CSA addition unit, an output shift unit, and a register group.

[0010] The pre-computation storage unit performs pre-computation based on the input parameters and stores the corresponding data for subsequent iterative calculation module's multi-channel input data selection and iterative calculation. The control unit controls the enabling, output shifting, and multi-channel input selection control of the calculation module by using a counter value. The iterative calculation module encodes the input data through the selection control unit, completes the multi-channel selection of pre-computation output data, accumulates the selected data through the CSA addition unit, and then passes it through the output shift unit. Through repeated iterations, it achieves parallel iterative calculations on two channels. Finally, the results of the two iterative calculations are added to obtain the final modular multiplication result.

[0011] The inputs to the pre-computation storage unit include: a reset signal and an external clock signal from the outside; a control signal from the control unit for enabling the pre-computation of the Montgomery modular multiplier before each new calculation; and externally sent Montgomery modular multiplication circuit input data, including the multiplier B and the domain parameter M of large prime numbers.

[0012] The output of the pre-calculation storage unit includes: a pre-calculation completion signal sent to the control unit; eight selection data sent to the multiplexer in the two-way calculation module, the values ​​of which are the outputs 0, B, M, 2M, 3M, B+M, B+2M, and B+3M obtained by pre-calculation of the multiplier B and the domain parameter M; and key bit data B[1:0] and M[1] of the multiplier B and the domain parameter M sent to the two-way selection control unit for selection control of the multiplexer.

[0013] The inputs to the control unit include: a reset signal and a clock signal from an external source; a pre-calculation completion signal from the pre-calculation storage unit, used to control the start of data iteration calculation and cycle counting; and an externally transmitted Montgomery modular multiplier circuit input, multiplier A.

[0014] The control unit's output includes: an output a that divides the input signal's multiplier A into two signal bits based on the cycle count value i. (2*i) and a (2*i+1) The outputs of the two signal bits are used as inputs to the selection control units of the two iterative calculation modules respectively; the iteration period count value i and the corresponding control signal sent to the output shift unit of the iterative calculation module are used to control the output shift unit, as well as the start and end of the iteration.

[0015] The two sets of iterative calculation modules are numbered 0 and 1 respectively;

[0016] The inputs to the iterative calculation module include: selection control signals B[1:0], M[1], and a from the pre-calculation storage unit and the control unit. (2*i) a (2*i+1) And the selection control signals Y0[3:2] and Y1[3:2] from the iterative feedback of the internal registers Y0 and Y1; the 8 data inputs from the multiplexer of the pre-computed storage unit; and the iterative count signal i and the corresponding control signal from the control unit;

[0017] The output of the iterative computation module includes: the final computation result P of the Montgomery modular multiplier based on parallel structure and encoding;

[0018] The register group in the iterative calculation module includes: output registers X0 and X1 of the multiplexer, output registers Y0 and Y1 of the CSA adder unit, and output registers Z0 and Z1 of the output shifter unit; these are denoted as X, Y, and Z respectively.

[0019] The selection control units for the two iterative calculation modules are denoted as S0 and S1, and their input control signals are B[1:0], M[1], and a=a. (2*i) or a (2*i+1) And the internal feedback signal Y[3:2]=Y0[3:2]or Y1[3:2]; the output is a coded multiplexed signal S[2:0], where S[2]=a,

[0020] The inputs of the multiplexer include: 8 data outputs from the input pre-computed storage unit, and selection signals S[2:0] from the selection control unit; the output data X is selected as 0, 2M, M, 3M, B, B+2M, B+M, B+3M respectively according to the values ​​of S[2:0] as 3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, and 3'b111.

[0021] The inputs to the CSA adder unit include data from register X and data from register Z, and the output of the sum is passed to register Y.

[0022] The inputs to the output shift unit include: the count signal i and control signal from the control unit, and the data in register Y; according to the control signal, when it is the last iteration, the data Y0 is shifted right by 1, and Y1 is shifted right by 2; during other iterations, the data Y is shifted right by 2 and then output to register Z;

[0023] Finally, based on the control unit signal, if it is the last iteration, the sum P of registers Z0 and Z1 is the final calculation of the Montgomery modular multiplier.

[0024] The beneficial effects of this invention are as follows: The modular multiplier of this invention, by adding additional shift compensation operations, decomposes the iterative calculation of the partial product into two sets of parallel calculations, achieving two-way parallelism for 2-radix Montgomery modular multiplication, thus reducing the cycle delay of the original 2-radix Montgomery modular multiplication to half of its original value. Combining the features of this two-way parallel design, by re-encoding the input data and pre-calculating the added additional shift compensation operations and partial products, the original three additions are transformed into a multiplexer and a single addition, optimizing the additional area overhead caused by parallel circuit modules and shortening the critical path of the overall operation. This allows the circuit of the invention to achieve less cycle delay while shortening the critical path delay of each cycle, and with only a small additional area overhead. This makes this design better suited for lightweight application scenarios. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the Montgomery modular multiplier based on parallel structure and encoding according to the present invention;

[0026] Figure 2 This is a schematic diagram of the selection control unit of the present invention. Detailed Implementation

[0027] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0028] like Figure 1As shown, a Montgomery modular multiplier based on parallel structure and encoding according to the present invention includes a pre-computation storage unit 1, a control unit 2, and two sets of iterative calculation modules 3 and 4. The iterative calculation module 3 includes an input selection control unit 6 (S0), a multiplexer MUX0 7, a CSA adder unit CSA0 9, an output shifter unit 11, and a register group; the iterative calculation module 4 includes an input selection control unit 5 (S1), a multiplexer MUX0 8, a CSA adder unit CSA0 10, an output shifter unit 12, and a register group.

[0029] The pre-computation storage unit performs pre-computation based on the input parameters and stores the corresponding data for subsequent iterative calculation module's multi-channel input data selection and iterative calculation. The control unit controls the enable, output shift, and multi-channel input selection control of the calculation module by using a counter value. The iterative calculation module encodes the input data through the selection control unit, completes the multi-channel selection of pre-computation output data, accumulates the selected data through the CSA addition unit, and then passes it through the output shift unit. Through repeated iterations, it achieves parallel iterative calculations on two channels. Finally, the addition unit 13 adds the results of the two iterative calculations to obtain the final modular multiplication result.

[0030] The inputs to the pre-computation storage unit 1 include: a reset signal and an external clock signal from the outside; a control signal en from the control unit 2, used to enable the pre-computation of the Montgomery modular multiplier before each new calculation; and externally sent Montgomery modular multiplication circuit input data, including the multiplier B and the domain parameter M of the large prime number.

[0031] The output of the pre-calculation storage unit 1 includes: a pre-calculation completion signal sent to the control unit 2; eight selection data sent to the multiplexers 7 and 8 in the two-way calculation module, the values ​​of which are the outputs 0, B, M, 2M, 3M, B+M, B+2M, and B+3M obtained by pre-calculation of the multiplier B and the domain parameter M; and key bit data B[1:0] and M[1] of the multiplier B and the domain parameter M sent to the two-way selection control units 5 and 6 for selection control of the multiplexers.

[0032] The inputs of the control unit 2 include: a reset signal and a clock signal from the outside; a pre-calculation completion signal "done" from the pre-calculation storage unit 1, used to control the start of data iteration calculation and cycle counting; and an externally transmitted Montgomery modular multiplication circuit input, multiplier A.

[0033] The output of control unit 2 includes: an output a that divides the multiplier A of the input signal into two signal bits based on the period count value i. (2*i) and a (2*i+1)The outputs of the two signal bits are used as inputs to the selection control units 5 and 6 of the two iterative calculation modules, respectively; the iteration cycle count value i and the corresponding control signal sent to the output shift units 11 and 12 of the iterative calculation module are used to control the output shift units, as well as the start and end of the iteration.

[0034] The two sets of iterative calculation modules are numbered 0 and 1 respectively;

[0035] The inputs to the iterative calculation modules 3 and 4 include: selection control signals B[1:0], M[1], and a from the pre-calculation storage unit 1 and the control unit 2. (2*i) a (2*i+1) And the selection control signals Y0[3:2] and Y1[3:2] from the iterative feedback of internal registers Y0 and Y1; the eight data inputs from multiplexers 7 and 8 of the pre-calculation storage unit 1; and the iterative count signal i and the corresponding control signal from the control unit 2;

[0036] The output of the iterative computation module includes: the final computation result P of the Montgomery modular multiplier based on parallel structure and encoding;

[0037] The register group in the iterative calculation module includes: output registers X0 and X1 of multiplexers 7 and 8, output registers Y0 and Y1 of CSA adder units 9 and 10, and output registers Z0 and Z1 of output shifter units 11 and 12; these are denoted as X, Y, and Z respectively.

[0038] The selection control units for the two sets of iterative calculation modules are denoted as S0 and S1, and their input control signals are B[1:0] (B[1] and B[0]), M[1], and a = a. (2*i) ora (2*i+1) And the internal feedback signal Y[3:2]=Y0[3:2]orY1[3:2](Y[3]、Y[2]); the output is a code-based multiplexer signal S[2:0], where S[2]=a, Its detailed circuit structure diagram is as follows Figure 2 As shown;

[0039] The inputs of the multiplexer include: 8 data outputs from the input pre-computed storage unit, and selection signals S[2:0] from the selection control unit; the output data X is selected as 0, 2M, M, 3M, B, B+2M, B+M, B+3M respectively according to the values ​​of S[2:0] as 3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, and 3'b111.

[0040] The inputs to the CSA adder unit include data from register X and data from register Z, and the output of the sum is passed to register Y.

[0041] The inputs to the output shift unit include: the count signal i and control signal from the control unit, and the data in register Y; according to the control signal, when it is the last iteration, the data Y0 is shifted right by 1, and Y1 is shifted right by 2; during other iterations, the data Y is shifted right by 2 and then output to register Z;

[0042] Finally, based on the control unit signal, if it is the last iteration, the sum P of registers Z0 and Z1 is the final calculation of the Montgomery modular multiplier.

[0043] Based on the above description, the specific operation process of the Montgomery modular multiplier of the present invention is as follows:

[0044] Input: A={a n-1 ,a n-2 ,,a1,a0},

[0045] B = {b} n-1 ,b n-2 ,b,1b,0,

[0046] M = {m n-1 ,m n-2 ,m,1m,0,radix 2,where 0<A,B<M,gcd(M,2)=1

[0047] Output: P = A·B·2 -n mod M

[0048] 1. If rst = 1, set registers X, Y, Z and pre-computed memory location 1 to 0;

[0049] 2. If the pre-calculated enable signal en = 1, calculate and store the data 2M, 3M, B+M, B+2M, B+3M.

[0050] Iterative calculation module:

[0051] 3.

[0052] 4. Calculate S0 and S1 (corresponding to S0, a = a) (2*i+1) Y = Y0, corresponding to S1, a = a (2*i) ,Y=Y1);

[0053] S[2:0]={s2,s1,s0};

[0054] s2 = a;

[0055] 5. If S0 / S1 = 3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111;

[0056] X0 / X1=0, 2M, M, 3M, B, B+2M, B+M, B+3M;

[0057] 6. Y0=X0+Z0, Y1=X1+Z1;

[0058] 7. Z1 = Y1 >> 2

[0059] else Z0=Y0>>2, Z1=Y1>>2

[0060] 8. end for

[0061] 9. P = Z0 + Z1

[0062] The modular multiplier of this invention reduces the cycle delay of Montgomery modular multiplication by designing a two-base, two-path parallel approach. Simultaneously, combining the features of this two-path parallel design, it employs pre-computation and input data encoding to reduce the partial products involved in the computation, optimize the additional area overhead caused by parallel circuit modules, and shorten the critical path. This allows the design to be better deployed in lightweight application scenarios.

[0063] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A Montgomery modular multiplier based on parallel structure and encoding, characterized in that, It includes a pre-computation storage unit, a control unit, and two sets of iterative calculation modules. The iterative calculation modules include an input selection control unit, a multiplexer, a CSA adder unit, an output shifter unit, and a register set. The pre-calculation storage unit performs pre-calculation based on the input parameters and stores the corresponding data, which is used for the selection of multiple input data and iterative calculation of the subsequent iterative calculation module; the control unit controls the enabling, output shifting, and selection control of multiple inputs of the calculation module in combination with the input through the count value. The iterative calculation module encodes the input data through the selection control unit, completes the multi-way selection of the pre-calculated output data, accumulates the selected data through the CSA addition unit, and then passes it through the output shift unit. Through repeated iterations, it achieves parallel iterative calculations in two paths. Finally, the results of the two iterative calculations are added together to obtain the final modular multiplication result. The two sets of iterative calculation modules are numbered 0 and 1 respectively; The inputs to the iterative calculation module include: selection control signals from the pre-computation storage unit and the control unit. , , , and the selection control signal from the iterative feedback of internal registers Y0 and Y1 , ; 8 data inputs from the multiplexer of the pre-computed storage unit; and the iterative counting signal from the control unit. and the corresponding control signal for the counting signal; The output of the iterative computation module includes: the final computation result P of the Montgomery modular multiplier based on parallel structure and encoding; The register group in the iterative calculation module includes: output registers X0 and X1 of the multiplexer, output registers Y0 and Y1 of the CSA adder unit, and output registers Z0 and Z1 of the output shifter unit; these are denoted as X, Y, and Z respectively. The selection control units for the two iterative calculation modules are denoted as S0 and S1, and their input control signals are: , , or and internal feedback signals or Output coded multiplexed signal ,in , , ; The inputs of the multiplexer include: eight data outputs from the input pre-computed storage unit, and selection signals from the selection control unit. ;according to The value is , , , , , , , Select the output data X as 0, 2M, M, 3M, B, B+2M, B+M, B+3M respectively; The inputs to the CSA adder unit include data from register X and data from register Z, and the output of the sum is passed to register Y. The inputs to the output shift unit include: the counting signal from the control unit. The control signal and the data in register Y are used; according to the control signal, when it is the last iteration, the data Y0 is shifted to the right by 1, and Y1 is shifted to the right by 2; during other iterations, the data Y is shifted to the right by 2 and then output to register Z. Finally, based on the control unit signal, if it is the last iteration, the sum P of registers Z0 and Z1 is the final calculation of the Montgomery modular multiplier.

2. The Montgomery modular multiplier based on parallel structure and encoding according to claim 1, characterized in that, The inputs to the pre-computation storage unit include: a reset signal and an external clock signal from the outside; a control signal from the control unit for enabling the pre-computation of the Montgomery modular multiplier before each new calculation; and externally sent Montgomery modular multiplication circuit input data, including the multiplier B and the domain parameter M of large prime numbers. The outputs of the pre-computation storage unit include: a pre-computation completion signal sent to the control unit; eight selection data sent to the multiplexer in the two-way calculation module, the values ​​of which are the pre-computed outputs 0, B, M, 2M, 3M, B+M, B+2M, and B+3M obtained from the multiplier B and domain parameter M; and key bit data of the multiplier B and domain parameter M sent to the two-way selection control unit. and It is used for selection control of multiplexers.

3. The Montgomery modular multiplier based on parallel structure and encoding according to claim 1, characterized in that, The inputs to the control unit include: a reset signal and a clock signal from an external source; a pre-calculation completion signal from the pre-calculation storage unit, used to control the start of data iteration calculation and cycle counting; and an externally transmitted Montgomery modular multiplier circuit input, multiplier A. The output of the control unit includes: based on the cycle count value The multiplier A of the input signal is split into two signal outputs. as well as The outputs of the two signal bits are used as inputs to the selection control units of the two iterative calculation modules, respectively; the iteration period count value is sent to the output shift unit of the iterative calculation module. And the corresponding control signals, used to control the output shift unit, as well as the start and end of the iteration.

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