Power supply phase multiplication system

Abstract

A power supply phase multiplication system includes a pulse width modulation controller, a first phase multiplication chip, and a second phase multiplication chip. The pulse width modulation controller is configured to output a pulse width modulation signal. The first phase multiplication chip operates at a supply voltage and has a first pulse width modulation output pin configured to generate a first control signal and a second control signal from the pulse width modulation signal, and to generate a first output signal from the first control signal. The second phase multiplication chip operates at the supply voltage and has a second pulse width modulation output pin configured to generate a second output signal from the second control signal. The first phase multiplication chip and the second phase multiplication chip are switched between master and slave modes according to voltage levels of the first pulse width modulation output pin and the second pulse width modulation output pin, respectively.

Description

Technical Field

[0001] This invention relates to a power supply system, and more particularly to a power supply phase doubling system suitable for components on a motherboard. Background Technology

[0002] With advancements in chip manufacturing processes and increased functionality, the power supply requirements for high-power-consuming chips such as the Central Processing Unit (CPU) and Graphics Processing Unit (GPU) are gradually increasing. Consequently, a multi-phase power supply architecture for DC-DC converters employing pulse-width modulation (PWM) control mechanisms has been proposed. This approach reduces output ripple, operating time, and temperature by alternately switching power supplies between different power groups (phases) within a cycle.

[0003] To address situations where the number of power supply phases exceeds the number supported by the pulse width modulation (PWM) controller chip, two designs have emerged to increase the number of phases: phase doubling and parallel power supply. However, phase doubling requires adding a phase doubler between the PWM controller and the driver to double the PWM signal, but this additional component increases the space required. Parallel power supply, on the other hand, causes the two power supply phases to operate completely synchronously, leading to increased output ripple and input ripple current, as well as higher temperature. Summary of the Invention

[0004] This invention provides a power supply phase doubling system, comprising a pulse width modulation (PWM) controller, a first phase doubling chip, and a second phase doubling chip. The PWM controller is configured to output a PWM signal. The first phase doubling chip is coupled to the PWM controller. The first phase doubling chip operates under a power supply voltage and has a first PWM output pin, configured to generate a first control signal and a second control signal based on the PWM signal, and to generate a first output signal based on the first control signal. The second phase doubling chip is coupled to the first phase doubling chip. The second phase doubling chip operates under a power supply voltage and has a second PWM output pin, configured to generate a second output signal based on the second control signal. The first and second phase doubling chips switch between master and slave modes respectively based on the voltage levels of the first and second PWM output pins.

[0005] Based on the above, compared to traditional phase-doubling power supply designs, the power supply phase-doubling system in this case eliminates the need for a phase doubler at the front end of the driver, reducing the space occupied on the motherboard. Compared to traditional parallel power supply designs, it can separate the conduction time of two phases, enabling asynchronous switching of two phases and achieving an interleaved effect with the same number of components, thereby reducing ripple at the output and input terminals.

[0006] To make the above-mentioned features and advantages of this case more apparent and understandable, specific embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a block diagram of a power supply phase doubling system according to an embodiment of the present invention;

[0008] Figure 2 This is a block diagram of the interior of a phase-doubling chip according to an embodiment of the present invention;

[0009] Figure 3 This is a signal timing diagram of a power supply phase doubling system according to an embodiment of the present invention;

[0010] Figure 4 This is a signal timing diagram of a power supply phase doubling system according to an embodiment of the present invention. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0012] Please refer to Figure 1 In this embodiment, the power phase doubling system 100 assists in powering various components, for example, on a motherboard. The power phase doubling system 100 includes a pulse width modulation controller 110, a first phase doubling chip 120, and a second phase doubling chip 130.

[0013] The pulse width modulation controller 110 is configured to output a pulse width modulation signal SPWM. For example, when the pulse width modulation controller 110 is operating normally, the duty cycle of the output pulse width modulation signal SPWM can be maintained at about 5%, and the frequency of the output pulse width modulation signal SPWM can be maintained at about 600 kHz, but the present invention is not limited thereto.

[0014] The first phase doubler chip 120 is coupled to the pulse width modulation controller 110. The first phase doubler chip 120 operates under the power supply voltage VCC and has a first pulse width modulation input pin PWM_IN1, a first pulse width modulation output pin PWM_OUT1, and a first output pin SW1.

[0015] The second phase doubler chip 130 is coupled to the first phase doubler chip 120. The second phase doubler chip 130 also operates at the power supply voltage VCC and has a second pulse width modulation input pin PWM_IN2, a second pulse width modulation output pin PWM_OUT2, and a second output pin SW2.

[0016] The first phase doubler chip 120 and the second phase doubler chip 130 can switch between master mode and slave mode based on the voltage levels of the first pulse width modulation output pin PWM_OUT1 and the second pulse width modulation output pin PWM_OUT2, respectively. Specifically, when the power supply voltage VCC rises to a predetermined operating voltage (e.g., 3 volts), within a predetermined time interval (e.g., 30 microseconds), the first phase doubler chip 120 detects the voltage level of the first pulse width modulation output pin PWM_OUT1, and the second phase doubler chip 130 detects the voltage level of the second pulse width modulation output pin PWM_OUT2. When the voltage level is lower than a threshold value, the corresponding phase doubler chip is set to master mode. When the voltage level is greater than or equal to the threshold value, the corresponding phase doubler chip is set to slave mode.

[0017] In this implementation, such as Figure 1 As shown, the first pulse width modulation (PWM) output pin PWM_OUT1 of the first phase doubler chip 120 is coupled to the second PWM input pin PWM_IN2 of the second phase doubler chip 130. At this time, the first PWM output pin PWM_OUT1 may be in a floating state or at a low voltage level, therefore its voltage level is below the threshold value, and the first phase doubler chip 120 is set to master mode. On the other hand, the second PWM output pin PWM_OUT2 of the second phase doubler chip 130 receives the setting voltage VDD (e.g., 3.3 volts), therefore the voltage level of the second PWM output pin PWM_OUT2 is greater than or equal to the threshold value, and the second phase doubler chip 130 is set to slave mode.

[0018] In this embodiment, the first pulse width modulation (PWM) input pin PWM_IN1 of the first phase doubler chip 120 is coupled to the pulse width modulation controller 110 and receives the pulse width modulation signal SPWM from the pulse width modulation controller 110. In main mode, the first phase doubler chip 120 is configured to generate a first control signal SC1 and a second control signal SC2 based on the pulse width modulation signal SPWM. The first phase doubler chip 120 can generate a first output signal SOUT1 based on the first control signal SC1, and output the first output signal SOUT1 through the first output pin SW1. At the same time, the first phase doubler chip 120 can transmit the second control signal SC2 to the second pulse width modulation input pin PWM_IN2 of the second phase doubler chip 130 through the first pulse width modulation output pin PWM_OUT1.

[0019] The second pulse width modulation input pin PWM_IN2 of the second phase doubler chip 130 is coupled to the first pulse width modulation output pin PWM_OUT1 of the first phase doubler chip 120, and receives the second control signal SC2 from the first pulse width modulation output pin PWM_OUT1. In slave mode, the second phase doubler chip 130 is configured to generate a second output signal SOUT2 according to the second control signal SC2, and outputs the second output signal SOUT2 from the second output pin SW2.

[0020] The internal structures of the first phase doubler chip 120 and the second phase doubler chip 130 are described below. Please refer to... Figure 2 The first phase doubler chip 120 in this embodiment includes a first driver 200 and a first transistor circuit 210. The first driver 200 is coupled to a first pulse width modulation input pin PWM_IN1 and a first pulse width modulation output pin PWM_OUT1. In main mode, the first driver 200 can function as a phase divider, generating a first control signal SC1 containing a first part (e.g., the odd-pulse part) of the pulse width modulation signal SPWM and a second control signal SC2 containing a second part (e.g., the even-pulse part) of the pulse width modulation signal SPWM, and providing the second control signal SC2 to the first pulse width modulation output pin PWM_OUT1.

[0021] For example, Figure 3 The timing diagram of the pulse width modulation signal SPWM, the first control signal SC1, and the second control signal SC2 is shown. Figure 3As shown, the first control signal SC1 is formed by the 1st, 3rd, 5th, and 7th pulses (the odd-numbered pulses) of the pulse width modulation (SPWM) signal. The second control signal SC2 is formed by the 2nd, 4th, and 6th pulses (the even-numbered pulses) of the SPWM signal. The period P1 of the first control signal SC1 is equal to the period P2 of the second control signal SC2, and is twice the period P0 of the SPWM signal. In other words, the frequency of the SPWM signal is twice that of both the first and second control signals SC1 and SC2.

[0022] Please return Figure 2 The first transistor circuit 210 is coupled to the first driver 200. The first transistor circuit 210 can generate a first output signal SOUT1 according to the first control signal SC1, and transmit the first output signal SOUT1 to the first output pin SW1.

[0023] Specifically, the first transistor circuit 210 includes a first upper-bridge transistor 212 and a first lower-bridge transistor 214. The first upper-bridge transistor 212 and the first lower-bridge transistor 214 are both coupled to a first output pin SW1. The control terminals of the first upper-bridge transistor 212 and the first lower-bridge transistor 214 receive a first control signal SC1. When the first control signal SC1 is at a first logic level (e.g., a high logic level), the first upper-bridge transistor 212 is turned on and the first lower-bridge transistor 214 is turned off. When the first control signal SC1 is at a second logic level (e.g., a low logic level), the first upper-bridge transistor 212 is turned off and the first lower-bridge transistor 214 is turned on. In this way, the first transistor circuit 210 can generate a first output signal SOUT1 with the same frequency as the first control signal SC1.

[0024] The second phase doubler chip 130 includes a second driver 300 and a second transistor circuit 310. The second driver 300 is coupled to the second pulse width modulation input pin PWM_IN2 and the second pulse width modulation output pin PWM_OUT2. In slave mode, the second driver 300 does not split the received second control signal SC2 into phases, but directly outputs the second control signal SC2 to the second transistor circuit 310.

[0025] The second transistor circuit 310 is coupled to the second driver 300. The second transistor circuit 310 can generate a second output signal SOUT2 according to the second control signal SC2, and transmit the second output signal SOUT2 to the second output pin SW2.

[0026] Specifically, the second transistor circuit 310 includes a second upper-bridge transistor 312 and a second lower-bridge transistor 314. The second upper-bridge transistor 312 and the second lower-bridge transistor 314 are both coupled to the second output pin SW2. The control terminals of the second upper-bridge transistor 312 and the second lower-bridge transistor 314 receive a second control signal SC2. When the second control signal SC2 is at a first logic level (e.g., a high logic level), the second upper-bridge transistor 312 is turned on and the second lower-bridge transistor 314 is turned off. When the second control signal SC2 is at a second logic level (e.g., a low logic level), the second upper-bridge transistor 312 is turned off and the second lower-bridge transistor 314 is turned on. In this way, the second transistor circuit 310 can generate a second output signal SOUT2 with the same frequency as the second control signal SC2.

[0027] In one embodiment, to achieve power saving, the pulse width modulation controller 110 can make the pulse width modulation signal SPWM include an intermediate level waveform MW with an intermediate level ML. When the first driver 200 receives the intermediate level waveform MW with the intermediate level ML, the first driver 200 adjusts the first control signal SC1 to the intermediate level ML to simultaneously turn off the first upper bridge transistor 212 and the first lower bridge transistor 214, and adjusts the second control signal SC2 to the intermediate level ML. At this time, the voltage level of the first output signal SOUT1 will remain approximately unchanged.

[0028] When the second control signal SC2 is adjusted to the intermediate level ML, the second driver 300 provides the second control signal SC2 to the second transistor circuit 310 to simultaneously turn off the second upper-bridge transistor 312 and the second lower-bridge transistor 314. At this time, the voltage level of the second output signal SOUT2 will remain approximately unchanged.

[0029] For example, Figure 4 The timing diagram of the pulse width modulation signal SPWM, the first control signal SC1, and the second control signal SC2 is shown. Figure 4 As shown, the pulse width modulation signal SPWM includes an intermediate level waveform MW with an intermediate level ML. When the pulse width modulation signal SPWM is adjusted to the intermediate level ML, the first control signal SC1 and the second control signal SC2 are also adjusted to the intermediate level ML.

[0030] like Figure 4As shown, when a pulse waveform PW is interspersed within the intermediate level waveform MW, the first driver 200 reflects the pulse waveform PW onto the first control signal SC1. That is, the first control signal SC1 also contains the corresponding identical waveform. Simultaneously, the first driver 200 continuously maintains the second control signal SC2 at the intermediate level ML. In this way, during the period when the pulse width modulation signal SPWM is at the intermediate level waveform MW, only the first phase doubler chip 120 operates, while the second phase doubler chip 130 remains inactive, thereby reducing the number of operating phases.

[0031] In summary, compared to traditional phase-doubling power supply designs, the power supply phase-doubling system in this case eliminates the need for a phase doubler at the front end of the driver, reducing its footprint on the motherboard. Compared to traditional parallel power supply designs, it can isolate the conduction time of two phases, enabling asynchronous switching of the two phases and thereby reducing ripple at both the output and input terminals. Furthermore, under specific conditions, the power supply phase-doubling system in this case can also disable the phase doubler chip in slave mode, thereby reducing the number of operating phases and achieving power saving.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power supply phase doubling system, characterized in that, include: A pulse width modulation controller, configured to output a pulse width modulation signal; A first phase doubler chip is coupled to the pulse width modulation controller. The first phase doubler chip operates under the power supply voltage and has a first pulse width modulation output pin. It is configured to generate a first control signal and a second control signal according to the pulse width modulation signal, and to generate a first output signal according to the first control signal. as well as A second phase doubler chip, coupled to the first phase doubler chip, operates under the power supply voltage and has a second pulse width modulation output pin, configured to generate a second output signal according to the second control signal. The first phase doubler chip and the second phase doubler chip switch between master mode and slave mode according to the voltage level of the first pulse width modulation output pin and the voltage level of the second pulse width modulation output pin, respectively.

2. The power supply phase doubling system according to claim 1, characterized in that, When the power supply voltage rises to the operating voltage, the first phase doubler chip and the second phase doubler chip respectively detect the voltage level of the first pulse width modulation output pin and the voltage level of the second pulse width modulation output pin within the time interval. When the voltage level is lower than the threshold value, the corresponding phase doubler chip is set to the master mode. When the voltage level is greater than or equal to the threshold value, the corresponding phase doubler chip is set to the slave mode.

3. The power supply phase doubling system according to claim 1, characterized in that, The first phase-doubling chip further has a first pulse width modulation (PWM) input pin coupled to the PWM controller, and receives the PWM signal from the PWM controller. The second phase doubler chip further has a second pulse width modulation input pin coupled to the first pulse width modulation output pin of the first phase doubler chip, and receives the second control signal from the first pulse width modulation output pin, while the second pulse width modulation output pin of the second phase doubler chip receives a set voltage.

4. The power supply phase doubling system according to claim 3, characterized in that, The first phase doubler chip further has a first output pin to output the first output signal. The second phase doubler chip further has a second output pin to output the second output signal.

5. The power supply phase doubling system according to claim 4, characterized in that, The first phase doubler chip is set to the main mode, and the first phase doubler chip includes: A first driver, coupled to the first pulse width modulation (PWM) input pin and the first PWM output pin, generates, in the main mode, a first control signal comprising a first portion of the PWM signal and a second control signal comprising a second portion of the PWM signal, and provides the second control signal to the first PWM output pin; and A first transistor circuit is coupled to the first driver, generates the first output signal according to the first control signal, and transmits the first output signal to the first output pin.

6. The power supply phase doubling system according to claim 5, characterized in that, The first transistor circuit includes a first upper-bridge transistor and a first lower-bridge transistor. The first upper-bridge transistor and the first lower-bridge transistor are coupled to the first output pin. The control terminals of the first upper-bridge transistor and the first lower-bridge transistor receive the first control signal. When the first control signal is at a first logic level, the first upper-bridge transistor is turned on and the first lower-bridge transistor is turned off. When the first control signal is at a second logic level, the first upper-bridge transistor is turned off and the first lower-bridge transistor is turned on.

7. The power supply phase doubling system according to claim 6, characterized in that, The pulse width modulation signal received by the first driver includes an intermediate level waveform with an intermediate level. When the first driver receives the intermediate level waveform with an intermediate level, the first driver adjusts the first control signal to an intermediate level to simultaneously turn off the first upper bridge transistor and the first lower bridge transistor, and adjusts the second control signal to an intermediate level.

8. The power supply phase doubling system according to claim 7, characterized in that, When a pulse waveform is interspersed in the intermediate level waveform, the first driver reflects the pulse waveform onto the first control signal and continuously maintains the second control signal at the intermediate level.

9. The power supply phase doubling system according to claim 4, characterized in that, The second phase doubler chip is set to slave mode, and the second phase doubler chip includes: The second driver, coupled to the second pulse width modulation input pin and the second pulse width modulation output pin, outputs the received second control signal in the slave mode; and The second transistor circuit is coupled to the second driver, generates the second output signal according to the second control signal, and transmits the second output signal to the second output pin.

10. The power supply phase doubling system according to claim 9, characterized in that, The second transistor circuit includes a second upper-bridge transistor and a second lower-bridge transistor, which are coupled together to the second output pin. The control terminals of the second upper-bridge transistor and the second lower-bridge transistor receive the second control signal. When the second control signal is at a first logic level, the second upper-bridge transistor is turned on and the second lower-bridge transistor is turned off. When the second control signal is at a second logic level, the second upper-bridge transistor is turned off and the second lower-bridge transistor is turned on.

11. The power supply phase doubling system according to claim 10, characterized in that, When the second control signal is adjusted to the intermediate level, the second driver provides the second control signal to the second transistor circuit to cause the second upper bridge transistor and the second lower bridge transistor to turn off simultaneously.

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