Fuse block unit, fuse block system, and memory device

Abstract

A fuse block unit, a fuse block system, and a memory device are disclosed. The fuse block unit includes a shared flip-flop. The shared flip-flop includes a first switch, a second switch, a third switch, a fourth switch, a first latch, and a second latch. The first switch selectively couples a first laser latch to a first node based on a first load potential. The second switch selectively couples a second laser latch to the first node based on a second load potential. The third switch selectively couples an input node to the first node based on an inverted shift potential. The first latch is coupled between the first node and a second node. The fourth switch selectively couples the second node to a third node based on a shift potential. The second latch is coupled between the third node and an output node.

Description

Technical Field

[0001] This invention relates to a fuse block unit, and more particularly to a fuse block unit and its memory device. Background Technology

[0002] In traditional designs, fuse blocks are distributed throughout the chip. This requires circuitry and traces to avoid the area occupied by the fuse blocks, resulting in wasted chip space and increased testing costs due to the need for multiple test runs. Therefore, a novel solution is necessary to overcome the problems of existing technologies. Summary of the Invention

[0003] This invention proposes a fuse block unit, comprising: a first laser fuse outputting first data; a first laser latch coupled to the first laser fuse; a second laser fuse outputting second data; a second laser latch coupled to the second laser fuse; and a shared trigger comprising: a first switch selectively coupling the first laser latch to a first node based on a first load potential; a second switch selectively coupling the second laser latch to the first node based on a second load potential; a third switch selectively coupling an input node to the first node based on an inversion shift potential; a first latch coupled between the first and second nodes; a fourth switch selectively coupling the second node to a third node based on a shift potential; and a second latch coupled between the third node and the output node. The high logic pulse of the second load potential does not occur simultaneously with the high logic pulse of the first load potential.

[0004] The present invention proposes a fuse block system, comprising: a plurality of the aforementioned fuse block units; wherein the plurality of shared triggers of the plurality of fuse block units are connected in series with each other.

[0005] The present invention proposes a memory device comprising: a plurality of aforementioned fuse block units connected in series with each other, wherein the plurality of fuse block units operate according to a first load potential, a second load potential, and a transfer potential to generate final output data; a pipeline pulse generator to generate the first load potential and the second load potential; and an oscillator to generate the transfer potential.

[0006] The fuse block unit, fuse block system, and memory device according to the present invention can improve chip space utilization efficiency, reduce the number of traces, shorten testing time, and reduce manufacturing costs. Attached Figure Description

[0007] Figure 1This is a schematic diagram showing a fuse block unit according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram showing a fuse block unit according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram showing a fuse block system according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram showing a conventional memory device.

[0011] Figure 5 This is a schematic diagram showing a memory device according to an embodiment of the present invention.

[0012] Figure 6 This is a signal waveform diagram showing the fuse block system according to an embodiment of the present invention.

[0013] Figure 7 This is a schematic diagram showing a memory device according to an embodiment of the present invention.

[0014] Figure 8 This is a waveform diagram showing the signal waveforms of a memory device according to an embodiment of the present invention.

[0015] Figure label:

[0016] 100, 100-1, 100-2, 100-N, 200, 410-1, 410-2, 410-M: Fuse block unit

[0017] 111: First laser fuse; 261: Third inverter

[0018] 112: Second laser fuse; 262: Fourth inverter

[0019] 121: First laser latch; 300: Fuse block system

[0020] 122: Second laser latch; 400, 500, 700: Memory device

[0021] 130, 130-1, 130-2, 130-N: Shared triggers; 520-1, 520-2, 520-R: Memory bank

[0022] 230: Shared trigger; 530: Peripheral circuitry

[0023] 141,241: First switcher; 710: Pipeline pulse generator

[0024] 142,242: Second switcher; 720: Oscillator

[0025] 143,243: Third switcher; 730: Finite state machine

[0026] 144,244: Fourth switcher; 740: Counter

[0027] 150, 250: First latch; 750: Peripheral circuitry

[0028] 160, 260: Second latch; 760: Main circuit

[0029] 251: First inverter BC: bit

[0030] 252: Second inverter CK: Base clock

[0031] CKD: Split clock; NOUT: Output node

[0032] DA, DA-1, DA-2, DA-N: First data point; T1: First time interval

[0033] DB, DB-1, DB-2, DB-N: Second data; T2: Second time interval

[0034] DF: Final output data VD1: First preparation potential

[0035] MN1: First N-type transistor; VD2: Second preparation potential

[0036] MN2: Second N-type transistor; VE1: First enable potential

[0037] MN3: Third N-type transistor; VE2: Second enable potential

[0038] MN4: Fourth N-type transistor; VE3: Third enable potential

[0039] MP1: First P-type transistor; VL1: First load potential

[0040] MP2: Second P-type transistor; VL1B: Inverting first load potential.

[0041] MP3: Third P-type transistor; VL2: Second loading potential

[0042] MP4: Fourth P-type transistor; VL2B: Inverting second load potential.

[0043] N1: First node VS: Transfer potential

[0044] N2: Second node VSB: Inverting shift potential

[0045] N3: Third node VSE: Set potential

[0046] NIN: Input node VRE: Reset potential Detailed Implementation

[0047] To make the objectives, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below in detail with reference to the accompanying drawings.

[0048] Certain terms are used in this specification and the claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same component. This specification and the claims do not distinguish components by differences in name, but rather by differences in function. Furthermore, the term "coupled" in this specification includes any direct or indirect electrical connection. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

[0049] like Figure 1 As shown, a fuse block unit 100 according to an embodiment of the present invention includes a first laser fuse 111, a second laser fuse 112, a first laser latch 121, a second laser latch 122, and a shared trigger 130. The fuse block unit 100 can be applied, for example, to a memory device, but the present invention is not limited thereto.

[0050] The first laser latch 121 is coupled to the first laser fuse 111 and can receive and store first data DA from the first laser fuse 111. The second laser latch 122 is coupled to the second laser fuse 112 and can receive and store second data DB from the second laser fuse 112. In some embodiments, if either fuse is in a conducting state, it can represent the corresponding data as a high logic level (e.g., logic "1"), and if either fuse is in a blown state, it can represent the corresponding data as a low logic level (e.g., logic "0"). However, the present invention is not limited thereto.

[0051] The shared trigger 130 has an input node NIN and an output node NOUT, and includes a first switch 141, a second switch 142, a third switch 143, a fourth switch 144, a first latch 150, and a second latch 160. Each switch can be independently controlled to operate in an on or off state. In some embodiments, the first switch 141, the second switch 142, the third switch 143, and the fourth switch 144 may be implemented as transmission gates, but the invention is not limited thereto.

[0052] The first switch 141 can selectively couple the first laser latch 121 to the first latch 150 based on the first load potential VL1. For example, if the first load potential VL1 is a high logic level, the first switch 141 can be in a conducting state, which can couple the first laser latch 121 to the first latch 150. Conversely, if the first load potential VL1 is a low logic level, the first switch 141 can be in a de-circuited state, and the first laser latch 121 is not coupled to the first latch 150.

[0053] The second switch 142 can selectively couple the second laser latch 122 to the first latch 150 based on the second load potential VL2. For example, if the second load potential VL2 is a high logic level, the second switch 142 can be in a conducting state, which can couple the second laser latch 122 to the first latch 150. Conversely, if the second load potential VL2 is a low logic level, the second switch 142 can be in a de-circuited state, and the second laser latch 122 is not coupled to the first latch 150.

[0054] It should be noted that the timing of the first load potential VL1 and the second load potential VL2 switching to high logic levels is staggered. That is, the first laser latch 121 and the second laser latch 122 will not be coupled to the first latch 150 simultaneously.

[0055] The third switch 143 can selectively couple the input node NIN to the first latch 150 based on an inverted shift voltage (VSB). For example, if the inverted shift voltage VSB is high, the third switch 143 can be in a conducting state, which couples the input node NIN to the first latch 150. Conversely, if the inverted shift voltage VSB is low, the third switch 143 can be in a de-circuited state, and the input node NIN is not coupled to the first latch 150.

[0056] The fourth switch 144 can selectively couple the first latch 150 to the second latch 160 based on the shift potential VS. The shift potential VS and the inverting shift potential VSB can have complementary logic levels. For example, if the shift potential VS is a high logic level, the fourth switch 144 can be in a conducting state, which can couple the first latch 150 to the second latch 160. Conversely, if the shift potential VS is a low logic level, the fourth switch 144 can be in a de-circuited state, and the first latch 150 is not coupled to the second latch 160. The second latch 160 is coupled between the third node N3 and the output node NOUT.

[0057] According to this embodiment, the first data DA from the first laser fuse 111 or the second data DB from the second laser fuse 112 is received through the shared trigger 130. Therefore, the first laser latch 121 and the second laser latch 122 can jointly use the same shared trigger 130 for data transmission, thereby reducing the number of triggers required for the fuse block unit. Furthermore, the first data DA or the second data DB can be temporarily stored in the first latch 150 and the second latch 160, and then communicated with other shared triggers 130 through the input node NIN and the output node NOUT. Therefore, the fuse block unit 100 provided by this invention not only reduces circuit complexity but also reduces overall manufacturing costs.

[0058] The following embodiments will illustrate various configurations and applications of the fuse block unit 100. It must be understood that these figures and descriptions are merely examples and are not intended to limit the scope of the invention.

[0059] Figure 2 This is a schematic diagram showing the configuration of the shared trigger 230 of the fuse block unit 200 according to an embodiment of the present invention. Figure 2 In the embodiments, with Figure 1 Similar details will not be repeated. The shared trigger 230 includes a first switch 241, a second switch 242, a third switch 243, a fourth switch 244, a first latch 250, and a second latch 260. In this embodiment, the outputs of the first switch 241, the second switch 242, and the third switch 243 are coupled to the input of the first latch 250 via a first node N1. The output of the first latch 250 is coupled to the input of the fourth switch 244 via a second node N2. The output of the fourth switch 244 is coupled to the input of the second latch 260 via a third node N3.

[0060] In detail, the first switch 241 may include a first N-type transistor MN1 and a first P-type transistor MP1. The control terminal of the first N-type transistor MN1 receives a first load potential VL1. The first terminal of the first N-type transistor MN1 is coupled to the first laser latch 121, and the second terminal of the first N-type transistor MN1 is coupled to the first node N1. The control terminal of the first P-type transistor MP1 receives an inverted first load potential VL1B. The first terminal of the first P-type transistor MP1 is coupled to the first laser latch 121, and the second terminal of the first P-type transistor MP1 is coupled to the first node N1. The first load potential VL1 and the inverted first load potential VL1B may have complementary logic levels.

[0061] The second switch 242 may include a second N-type transistor MN2 and a second P-type transistor MP2. The control terminal of the second N-type transistor MN2 receives a second load potential VL2. The first terminal of the second N-type transistor MN2 is coupled to the second laser latch 122, and the second terminal of the second N-type transistor MN2 is coupled to the first node N1. The control terminal of the second P-type transistor MP2 receives an inverted second load potential VL2B. The first terminal of the second P-type transistor MP2 is coupled to the second laser latch 122, and the second terminal of the second P-type transistor MP2 is coupled to the first node N1. The second load potential VL2 and the inverted second load potential VL2B may have complementary logic levels.

[0062] The third switch 243 includes a third N-type transistor MN3 and a third P-type transistor MP3. The control terminal of the third N-type transistor MN3 receives an inverting shift potential VSB. The first terminal of the third N-type transistor MN3 is coupled to the input node NIN, and the second terminal of the third N-type transistor MN3 is coupled to the first node N1. The control terminal of the third P-type transistor MP3 receives a shift potential VS. The first terminal of the third P-type transistor MP3 is coupled to the input node NIN, and the second terminal of the third P-type transistor MP3 is coupled to the first node N1.

[0063] The first latch 250 includes a first inverter 251 and a second inverter 252. The input of the first inverter 251 is coupled to a first node N1, and the output of the first inverter 251 is coupled to a second node N2. The input of the second inverter 252 is coupled to the second node N2, and the output of the second inverter 252 is coupled to the first node N1.

[0064] The fourth switch 244 includes a fourth N-type transistor MN4 and a fourth P-type transistor MP4. The control terminal of the fourth N-type transistor MN4 receives a shift potential VS. The first terminal of the fourth N-type transistor MN4 is coupled to the second node N2, and the second terminal of the fourth N-type transistor MN4 is coupled to the third node N3. The control terminal of the fourth P-type transistor MP4 receives an inverted shift potential VSB. The first terminal of the fourth P-type transistor MP4 is coupled to the second node N2, and the second terminal of the fourth P-type transistor MP4 is coupled to the third node N3.

[0065] The second latch 260 includes a third inverter 261 and a fourth inverter 262. The input of the third inverter 261 is coupled to a third node N3, and its output is coupled to an output node NOUT. The input of the fourth inverter 262 is coupled to an output node NOUT, and its output is coupled to the third node N3.

[0066] In some embodiments, each N-type transistor is an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), and each P-type transistor is a P-type metal-oxide-semiconductor field-effect transistor, but is not limited thereto.

[0067] exist Figure 3 In one embodiment, the fuse block system 300 includes a plurality of fuse block units 100-1, 100-2, ..., 100-N (for example, N may be a positive integer greater than or equal to 2), and its circuit structure may be as previously described. Figure 1 , Figure 2 As described in the embodiments, the plurality of shared triggers 130-1, 130-2, ..., 130-N of the plurality of fuse block units 100-1, 100-2, ..., 100-N are connected in series with each other. For example, the input node NIN of shared trigger 130-2 can be coupled to the output node NOUT of the previous shared trigger 130-1, and so on. This facilitates the miniaturization of the fuse block system 300.

[0068] In some embodiments, the plurality of shared triggers 130-1, 130-2, ..., 130-N have parallel input functionality. In other words, the shared triggers 130-1, 130-2, ..., 130-N can receive data simultaneously. That is, at the same time point, shared trigger 130-1 can receive first data DA-1 or second data DB-1, shared trigger 130-2 can receive first data DA-2 or second data DB-2, ..., while shared trigger 130-N can receive first data DA-N or second data DB-N. In some embodiments, the plurality of shared triggers 130-1, 130-2, ..., 130-N have serial output functionality. That is, the multiple data stored in the plurality of shared triggers 130-1, 130-2, ..., 130-N can be output sequentially according to the shift potential VS and the inverting shift potential VSB to form the final output data DF. Figure 3 The remaining features of the fuse block system 300 are all the same as Figure 1 The fuse block unit 100 is similar, so both embodiments can achieve similar operational effects.

[0069] like Figure 4As shown, in the conventional memory device 400, multiple fuse block units 410-1, 410-2, ..., 410-M are arranged in a dispersed manner, and each laser fuse must be coupled to a dedicated trigger, thus occupying a large area. On the other hand, because the arrangement orientation of these fuse block units 410-1, 410-2, ..., 410-M is also inconsistent, if the conventional memory device 400 is to be tested, the scanning mode of the laser beam needs to be changed multiple times according to the position and arrangement orientation of these fuse block units 410-1, 410-2, ..., 410-M, which requires a lot of testing time and results in high production costs.

[0070] exist Figure 5 In one embodiment of the present invention, the memory device 500 includes a plurality of fuse block units 100-1, 100-2, ..., 100-N, a plurality of memory banks 520-1, 520-2, ..., 520-R (e.g., R can be a positive integer greater than or equal to 2), and peripheral circuitry 530, wherein the plurality of memory banks 520-1, 520-2, ..., 520-R and the peripheral circuitry 530 can all be directly or indirectly controlled by the plurality of fuse block units 100-1, 100-2, ..., 100-N. It should be noted that the plurality of fuse block units 100-1, 100-2, ..., 100-N can be arranged approximately in a straight line. This not only reduces the total area of ​​these fuse block units, making wiring layout easier, but also reduces the number of tests and manufacturing costs of the memory device 500. Figure 5 The remaining features of the memory device 500 are all the same as Figure 3 The fuse block system 300 is similar, so both embodiments can achieve similar operational effects.

[0071] Figure 6 This is a signal waveform diagram illustrating the control method of a fuse block system 300 according to an embodiment of the present invention. Please refer to it as well. Figure 3 , Figure 6In response to a high logic pulse of the first load signal VL1, the plurality of shared flip-flops 130-1, 130-2, ..., 130-N load multiple first data DA-1, DA-2, ..., DA-N in parallel. In response to multiple clock cycles of the shift potential VS, these first data DA-1, DA-2, ..., DA-N can be output one by one to form the final output data DF. Next, in response to a high logic pulse of the second load signal VL2, the plurality of shared flip-flops 130-1, 130-2, ..., 130-N load multiple second data DB-1, DB-2, ..., DB-N in parallel. In response to multiple clock cycles of the shift potential VS, these second data DB-1, DB-2, ..., DB-N can be output one by one to form the final output data DF. This parallel input, serial output design helps reduce the number of connection lines required for the fuse block system 300 to be applied to any memory device, thus facilitating the miniaturization of the memory device.

[0072] exist Figure 7 In one embodiment, the memory device 700 includes a plurality of fuse block units 100-1, 100-2, ..., 100-N, a pipe pulse generator 710, an oscillator 720, a finite state machine (FSM) 730, a counter 740, peripheral circuitry 750, and a main circuitry 760.

[0073] The circuit structure of the multiple fuse block units 100-1, 100-2, ..., 100-N can be as previously described. Figure 1 , Figure 2 As described in the embodiment, the plurality of fuse block units 100-1, 100-2, ..., 100-N are connected in series and can operate according to the first load potential VL1, the second load potential VL2, and the transfer potential VS to generate the final output data DF. Furthermore, the plurality of fuse block units 100-1, 100-2, ..., 100-N can also be selectively set or reset according to the set potential VSE and the reset potential VRE.

[0074] In detail, the peripheral circuitry 750 may include a latch control circuit, an oscillator enable circuit, and a latch latch ready circuit. The latch control circuit is coupled to the laser latches of the plurality of fuse block units 100-1, 100-2, ..., 100-N and is configured to generate a set potential VSE and a reset potential VRE for setting and resetting the laser latches, respectively. The oscillator enable circuit is coupled to the oscillator 720 and is configured to generate a third enable potential VE3 for selectively enabling the oscillator 720. The latch latch ready circuit is coupled to the oscillator 720 and is configured to generate a first ready potential VD1 to indicate that the fuse data in the laser latches is ready. The peripheral circuitry 750 also includes a second ready potential generation circuit coupled to the main circuitry 760, the second ready potential VD2 being used to indicate whether the plurality of fuse block units 100-1, 100-2, ..., 100-N are ready. The main circuit 760 can receive the second preparation potential VD2.

[0075] The finite state machine 730 can control the pipeline pulse generator 710 according to a plurality of bits BC, and the pipeline pulse generator 710 can generate a first load potential VL1 and a second load potential VL2 at different times according to the control of the finite state machine 730. In some embodiments, the finite state machine 730 may include a decoder and a plurality of triggers.

[0076] The oscillator 720 can generate a shift potential VS, a base clock CK, a split clock CKD, and a first enable potential VE1 based on a second enable potential VE2, a third enable potential VE3, and a first preparation potential VD1. The first enable potential VE1 can be used to selectively enable the counter 740.

[0077] Counter 740 can generate the plurality of bits BC and a second enable potential VE2 based on a base clock CK, a split clock CKD, and a first enable potential VE1. The second enable potential VE2 can be used to selectively enable a shared trigger to generate the plurality of clocks. For example, the frequency of the split clock CKD can be half the frequency of the base clock CK, and the total number of the plurality of bits BC can be 8.

[0078] Figure 8 This is a signal waveform diagram showing the operation method of a memory device 700 according to an embodiment of the present invention. Figure 8In one embodiment, during the first time interval T1, after the reset potential VRE changes from a low logic level to a high logic level, the latch control circuit generates a set potential VSE with a high logic pulse, so that the data in the laser fuse is stored in the corresponding laser latch. Next, during the second time interval T2, in response to the set potential VSE of the high logic pulse, the first preparation potential VD1 and the third enable potential VE3 change from low logic level to high logic level, causing the oscillator 720 to generate the base clock CK, the split clock CKD, and the first enable potential VE1. This allows the counter 740 to generate the plurality of bits BC and the second enable potential VE2 based on the base clock CK, the split clock CKD, and the first enable potential VE1. Consequently, the finite state machine 730 controls the pipeline pulse generator 710 to sequentially generate high logic pulses of the first load potential VL1 and the second load potential VL2 based on the plurality of bits BC, so that data is loaded in parallel into the shared flip-flops of the plurality of fuse block units 100-1, 100-2, ..., 100-N. After the second time interval T2 ends, the final output data DF is output in series from the aforementioned shared flip-flops.

[0079] This invention proposes a novel fuse block unit, fuse block system, and memory device. In general, this invention offers advantages such as improved design area utilization, reduced wiring count, shorter testing time, and reduced overall manufacturing costs, making it well-suited for application in a wide variety of electronic devices.

[0080] It is worth noting that the component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The fuse block unit, fuse block system, and memory device of the present invention are not limited to these limitations. Figures 1-8 The state shown. This invention may include only... Figures 1-8 Any one or more features of any one or more embodiments. In other words, not all illustrated features need to be implemented simultaneously in the fuse block unit, fuse block system, and memory device of the present invention. Although the embodiments of the present invention use metal-oxide-semiconductor field-effect transistors as examples, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field-effect transistors or fin field-effect transistors, without affecting the effects of the present invention.

[0081] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A fuse block unit, characterized in that, include: The first laser fuse outputs the first data. A first laser latch is coupled to the first laser fuse; A second laser fuse outputs a second data. A second laser latch is coupled to the second laser fuse; as well as A shared trigger, including: A first switch selectively couples the first laser latch to a first node according to a first load potential; A second switch selectively couples the second laser latch to the first node according to a second load potential, wherein a high logic pulse of the second load potential does not occur simultaneously with a high logic pulse of the first load potential; A third switch selectively couples an input node to the first node based on an inverting phase shift potential; A first latch is coupled between the first node and a second node; A fourth switch selectively couples the second node to a third node based on a transfer potential; and A second latch is coupled between the third node and an output node.

2. The fuse block unit as described in claim 1, characterized in that, The first switch, the second switch, the third switch, and the fourth switch are each implemented using a transmission gate.

3. The fuse block unit as described in claim 1, characterized in that, The first switch includes: A first N-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first N-type transistor is used to receive a first load potential, the first terminal of the first N-type transistor is coupled to the first laser latch, and the second terminal of the first N-type transistor is coupled to the first node; and A first P-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first P-type transistor is used to receive an inverted first load potential, the first terminal of the first P-type transistor is coupled to the first laser latch, and the second terminal of the first P-type transistor is coupled to the first node.

4. The fuse block unit as described in claim 1, characterized in that, The second switch includes: A second N-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second N-type transistor is used to receive the second load potential, the first terminal of the second N-type transistor is coupled to the second laser latch, and the second terminal of the second N-type transistor is coupled to the first node; and A second P-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second P-type transistor is used to receive an inverted second load potential, the first terminal of the second P-type transistor is coupled to the second laser latch, and the second terminal of the second P-type transistor is coupled to the first node.

5. The fuse block unit as described in claim 1, characterized in that, The third switch includes: A third N-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third N-type transistor is used to receive the inverting shift potential, the first terminal of the third N-type transistor is coupled to the input node, and the second terminal of the third N-type transistor is coupled to the first node; and A third P-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third P-type transistor is used to receive the transfer potential, the first terminal of the third P-type transistor is coupled to the input node, and the second terminal of the third P-type transistor is coupled to the first node.

6. The fuse block unit as claimed in claim 1, characterized in that, The fourth switch includes: A fourth N-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth N-type transistor is used to receive the transfer potential, the first terminal of the fourth N-type transistor is coupled to the second node, and the second terminal of the fourth N-type transistor is coupled to the third node; and A fourth P-type transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth P-type transistor is used to receive the inverting shift potential, the first terminal of the fourth P-type transistor is coupled to the second node, and the second terminal of the fourth P-type transistor is coupled to the third node.

7. A fuse block system, characterized in that, include: Multiple fuse block units as described in claim 1; The multiple shared triggers of the plurality of fuse block units are connected in series with each other.

8. The fuse block system as described in claim 7, characterized in that, The multiple fuse block units are arranged in a straight line.

9. The fuse block system as claimed in claim 7, characterized in that, The multiple shared triggers receive the first data or the second data simultaneously.

10. The fuse block system as claimed in claim 7, characterized in that, The plurality of shared triggers output the first data and the second data in sequence.

11. A memory device, characterized in that, include: Multiple fuse block units as described in claim 1 are connected in series with each other, wherein the multiple fuse block units operate according to the first load potential, the second load potential, and the transfer potential to generate a final output data at the output node; as well as A pipeline pulse generator generates the first load potential and the second load potential; as well as An oscillator generates this transfer potential.

12. The memory device as claimed in claim 11, characterized in that, The multiple fuse block units are arranged in a straight line.

13. The memory device as claimed in claim 11, characterized in that, Also includes: A finite state machine controls the pipeline pulse generator based on multiple bits.

14. The memory device as claimed in claim 13, characterized in that, Also includes: A counter generates the plurality of bits and a second enable potential based on a base clock, a segment clock, and a first enable potential.

15. The memory device as claimed in claim 14, characterized in that, The oscillator also generates the transfer potential, the base clock, the split clock, and the first activation potential based on the second activation potential, a third activation potential, and a first preparation potential.

16. The memory device as claimed in claim 15, characterized in that, Also includes: A peripheral circuit generates a set potential, a reset potential, a third enable potential, a first preparation potential, and a second preparation potential.

17. The memory device as claimed in claim 16, characterized in that, The plurality of fuse block units can also be selectively set or reset based on the set potential and the reset potential.

18. The memory device as claimed in claim 16, characterized in that, Also includes: A main circuit receives the second preparation potential.

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