Display device

Abstract

A display device has a display panel (50a) including a base substrate layer (10), a thin film transistor layer (30a), a light emitting element layer (35), and a sealing film (40), a camera portion (60) is provided on the base substrate layer (10) side of a display region (D) of the display panel (50a), a plurality of sub-pixels constituting the display region (D) are divided into a group of normal sub-pixels and a group of sparse sub-pixels, the group of normal sub-pixels is provided in a manner not overlapping the camera portion (60), the group of sparse sub-pixels is provided in a manner overlapping the camera portion (60), and in an inorganic insulating film (20a), an opening portion (Maa) is provided in a manner penetrating the inorganic insulating film (20a) in a camera region (Dc) overlapping the group of sparse sub-pixels.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] In recent years, self-emissive organic EL (OLED) displays using organic electroluminescence (EL) elements have attracted attention as an alternative to liquid crystal displays. In these OLED displays, a structure has been proposed that incorporates a camera unit, such as a camera, within the display area where images are displayed.

[0003] For example, Patent Document 1 discloses a display device in which scanning signal lines and data signal lines extending into the display area are arranged around a light transmission area for imaging within the display area in a manner that avoids the light transmission area.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Text of International Publication No. 2019 / 198163 ( Figure 4 ) Summary of the Invention

[0007] The technical problem to be solved by the present invention

[0008] However, in organic EL display devices with a camera unit inside the display area, the sub-pixels constituting the display area are thinned out in the camera unit to increase transmittance. Therefore, the presence of thinned sub-pixels or their adjacent sub-pixels tends to result in poor illumination.

[0009] The present invention was made in view of the above points, and its object is to suppress the generation of poor illumination in the sparsed sub-pixels and their adjacent sub-pixels.

[0010] Technical solutions for solving technical problems

[0011] To achieve the above objectives, the display device of the present invention has a display panel comprising: a substrate layer; a thin-film transistor layer disposed on the substrate layer, wherein a first wiring layer, a first planarization film, an inorganic insulating film, a second wiring layer, and a second planarization film are sequentially stacked thereon; a light-emitting element layer disposed on the thin-film transistor layer, corresponding to a plurality of sub-pixels constituting a display area, wherein a plurality of first electrodes, a plurality of light-emitting functional layers, and a common second electrode are sequentially stacked thereon; and a sealing film disposed on the light-emitting element layer. An image-capturing portion is disposed on the substrate layer side of the display area of ​​the display panel. The display device is characterized in that the plurality of sub-pixels are divided into a group of ordinary sub-pixels and a group of sparse sub-pixels. The group of ordinary sub-pixels is configured not to overlap with the image-capturing portion, and the group of sparse sub-pixels is configured to overlap with the image-capturing portion and is sparser than the group of ordinary sub-pixels. In the inorganic insulating film, an opening is provided in the image-capturing area overlapping with the group of sparse sub-pixels, penetrating the inorganic insulating film.

[0012] Beneficial effects

[0013] According to the present invention, the occurrence of poor illumination can be suppressed in the sparsed sub-pixels and their adjacent sub-pixels. Attached Figure Description

[0014] Figure 1 This is a top view showing the schematic configuration of an organic EL display device according to the first embodiment of the present invention.

[0015] Figure 2 This is a top view of the display area of ​​the organic EL display panel of the organic EL display device constituting the first embodiment of the present invention.

[0016] Figure 3 It is along Figure 1 A cross-sectional view of the display area of ​​the organic EL display panel along line III-III.

[0017] Figure 4 This is an equivalent circuit diagram of the thin-film transistor layer of the organic EL display panel constituting the organic EL display device of the first embodiment of the present invention.

[0018] Figure 5 This is a cross-sectional view of the organic EL layer of the organic EL display panel constituting the organic EL display device of the first embodiment of the present invention.

[0019] Figure 6 It is along Figure 1 A cross-sectional view of the border area of ​​the organic EL display panel with VI-VI lines.

[0020] Figure 7 It is along Figure 1 A cross-sectional view of the border area of ​​the organic EL display panel along lines VII-VII.

[0021] Figure 8 It is along Figure 1 A cross-sectional view of the border area of ​​the organic EL display panel along lines VIII-VIII.

[0022] Figure 9 This is a top view of the imaging area and its surroundings of the organic EL display panel of the organic EL display device constituting the first embodiment of the present invention.

[0023] Figure 10 It is along Figure 9 A cross-sectional view of the camera area and its surroundings of the organic EL display panel with XX lines in the image.

[0024] Figure 11 This is a top view of the camera area and its surroundings of the organic EL display panel of the organic EL display device constituting the second embodiment of the present invention.

[0025] Figure 12 This is a top view of the camera area and its surroundings of the organic EL display panel of the organic EL display device constituting the third embodiment of the present invention.

[0026] Figure 13 It is along Figure 12 A cross-sectional view of the camera area and its surroundings of the organic EL display panel along the XIII-XIII line. Detailed Implementation

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0028] First Implementation Method

[0029] Figures 1-10 This describes a first embodiment of the display device of the present invention. Furthermore, in the following embodiments, an organic EL display device having an organic EL element layer is exemplified as a display device having a light-emitting element layer. Here, Figure 1 This is a top view showing the schematic configuration of the organic EL display device 70 according to this embodiment. Furthermore, Figure 2 This is a top view of the display area D of the organic EL display panel 50a that constitutes the organic EL display device 70. Furthermore, Figure 3 It is along Figure 1 A cross-sectional view of the display area D of the organic EL display panel 50a along line III-III. Furthermore, Figure 4 This is an equivalent circuit diagram of the thin-film transistor layer 30a that constitutes the organic EL display panel 50a. Furthermore, Figure 5 This is a cross-sectional view of the organic EL layer 33 that constitutes the organic EL display panel 50a. Furthermore, Figure 6 , Figure 7 and Figure 8 It is along Figure 1 A cross-sectional view of the bezel area F of the organic EL display panel 50a containing lines VI-VI, VII-VII, and VIII-VIII. Furthermore, Figure 9 This is a top view of the camera area Dc and its surroundings of the organic EL display panel 50a. Furthermore, Figure 10 It is along Figure 9 A cross-sectional view of the camera area Dc and its surroundings of the organic EL display panel 50a with XX lines in the image.

[0030] like Figure 1 As shown, the organic EL display device 70 includes, for example, a display area D, which is rectangular in shape for displaying images; a camera area Dc, which is rectangular in shape and disposed inside the display area D for displaying images and capturing images; and a border area F, which is a rectangular frame surrounding the display area D. Here, the organic EL display device 70 includes the organic EL display panel 50a (described later), and a camera unit 60 disposed on the resin substrate layer 10 side (back side) of the camera area Dc of the display area D of the organic EL display panel 50a (described later). Figure 1 Furthermore, in this embodiment, a rectangular display area D is illustrated, but this rectangular shape also includes, for example, shapes with rounded edges, rounded corners, or cutouts on a portion of the edges, etc., that are generally rectangular. In addition, in this embodiment, a rectangular imaging area Dc is illustrated, but the imaging area Dc can also be other shapes such as circles, ellipses, or polygons. Furthermore, in this embodiment, a configuration in which one imaging area Dc is provided inside the display area D is illustrated, but multiple imaging areas Dc can also be provided inside the display area D. Furthermore, the imaging unit 60 is, for example, a CMOS (complementary metal oxide semiconductor) camera or a CCD (charge-coupled device) camera. Furthermore, as... Figure 1 As shown, the camera area Dc is located in the middle of the portion of the display area D along the left side of the figure when viewed from above.

[0031] like Figure 2 As shown, in display area D, multiple sub-pixels P are arranged in a matrix. Furthermore, in display area D, as... Figure 2As shown, for example, sub-pixels P having a red emitting area Lr for red display, sub-pixels P having a green emitting area Lg for green display, and sub-pixels P having a blue emitting area Lb for blue display are arranged adjacent to each other. Furthermore, in the display area D, for example, a pixel is formed by three adjacent sub-pixels P having a red emitting area Er, a green emitting area Eg, and a blue emitting area Eb. Here, as... Figure 9 As shown, the multiple sub-pixels P are divided into a group of normal sub-pixels Pa that are arranged in a manner that does not overlap with the camera unit 60, and a group of sparse sub-pixels Pb that are arranged on the imaging area Dc that overlap with the camera unit 60 and are sparser than the group of normal sub-pixels Pa. In addition, the size of the sub-pixels P (normal sub-pixels Pa and sparse sub-pixels Pb) is, for example, about 50μm × 30μm, and the size of the imaging area Dc is, for example, about 3mm × 3mm.

[0032] In the border area F Figure 1 The right end of the portion is configured as a terminal T extending in one direction (vertical in the figure). Furthermore, in the border area F, as... Figure 1 As shown, between the display area D and the terminal portion T, a bending portion B, capable of bending 180° (U-shape), is provided extending in one direction (the longitudinal direction in the figure), with the longitudinal direction as the bending axis. Furthermore, multiple terminals are arranged on the terminal portion T along its extending direction. Additionally, in the frame area F, in the first planarization film 19a and the second planarization film 22a (described later), as... Figure 1 and Figure 6 As shown, a groove G, which is approximately C-shaped when viewed from above, is provided in a manner that penetrates the first planarization film 19a and the second planarization film 22a. Here, as... Figure 1 As shown, the groove G is roughly C-shaped with an opening on the terminal T side when viewed from above.

[0033] like Figure 3 As shown, the organic EL display panel 50a includes: a resin substrate layer 10 disposed as a substrate layer, a thin film transistor (TFT) layer 30a disposed on the resin substrate layer 10, an organic EL element layer 35 disposed on the TFT layer 30a as a light-emitting element layer, and a sealing film 40 disposed on the organic EL element layer 35.

[0034] The resin substrate layer 10 is made of organic resin materials such as polyimide resin.

[0035] like Figure 3As shown, the TFT layer 30a includes an undercoat film 11 disposed on the resin substrate layer 10, a plurality of first TFTs 9a disposed on the undercoat film 11, and a plurality of second TFTs 9b (see reference). Figure 4 ), multiple third TFTs 9c and multiple capacitors 9d. Furthermore, such as Figure 3 As shown, the TFT layer 30a includes a first planarization film 19a, an inorganic insulating film 20a, and a second planarization film 22a sequentially disposed on each of the first TFT 9a, each of the second TFT 9b, each of the third TFT 9c, and each of the capacitors 9d.

[0036] In TFT layer 30a, such as Figure 3 As shown, semiconductor layers 12a and 12b, gate insulating film 13, gates 14a and 14b, lower conductive layer 14c (third wiring layer), first interlayer insulating film 15, upper conductive layer 16a (fourth wiring layer), second interlayer insulating film 17, source electrodes 18a and 18c, drain electrodes 18b and 18d (first wiring layer), first planarization film 19a, inorganic insulating film 20a, power line 21a, relay electrode 21b (second wiring layer), and second planarization film 22a are sequentially stacked on the base coating film 11.

[0037] In TFT layer 30a, in display area D, such as Figure 2 and Figure 4 As shown, multiple gate lines 14d are arranged as a third wiring layer, extending laterally parallel to each other in the figure. Furthermore, in the TFT layer 30a, in the display area D, as... Figure 2 and Figure 4 As shown, multiple light-emitting control lines 14e are arranged as a third wiring layer, extending parallel to each other in the horizontal direction. Furthermore, the gate lines 14d and 14e, along with the gates 14a and 14b and the lower conductive layer 14c, are formed in the same layer using the same material. Additionally, as... Figure 2 As shown, each light-emitting control line 14e is positioned adjacent to each gate line 14d. Furthermore, in the TFT layer 30a, in the display area D, as... Figure 2 and Figure 4 As shown, multiple source lines 18f are arranged as a first wiring layer, extending parallel to each other along the longitudinal direction of the figure. Furthermore, the source lines 18f, source electrodes 18a and 18c, and drain electrodes 18b and 18d are formed of the same material in the same layer. Additionally, in the TFT layer 30a, in the display area D, as... Figure 1 As shown, the power lines 21a are arranged in a grid pattern as the fourth wiring layer. Furthermore, in the TFT layer 30a, as... Figure 4As shown, each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, a third TFT 9c, and a capacitor 9d. Here, in the imaging area Dc, as... Figure 9 As shown, gate line 14d and light-emitting control line 14e are thinned to 1 / 6 by removing 5 out of every 6 lines, and source line 18f is thinned to 1 / 4 by removing 3 out of every 4 lines. Furthermore, in Figure 9 In the top view, the light control line 14e is omitted.

[0038] The base coating film 11, the gate insulating film 13, the first interlayer insulating film 15, the second interlayer insulating film 17, and the inorganic insulating film 20a are, for example, composed of single-layer or multilayer films such as silicon nitride, silicon oxide, and silicon oxynitride.

[0039] like Figure 4 As shown, the first TFT 9a is electrically connected to the corresponding gate line 14d, source line 18f, and second TFT 9b in each sub-pixel P. Furthermore, as... Figure 3 As shown, the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, a source 18a, and a drain 18b, which are sequentially disposed on the base coating film 11. Here, as Figure 3 As shown, semiconductor layer 12a is disposed on the base coating film 11, and as described later, has a channel region, a source region, and a drain region. Furthermore, semiconductor layer 12a and semiconductor layer 12b (described later) are formed, for example, from a low-temperature polycrystalline silicon film, an In-Ga-Zn-O based oxide semiconductor film, etc. Furthermore, as... Figure 3 As shown, the gate insulating film 13 is provided in a manner that covers the semiconductor layer 12a. Furthermore, as... Figure 3 As shown, the gate 14a is disposed on the gate insulating film 13 in a manner that overlaps with the channel region of the semiconductor layer 12a. Furthermore, as... Figure 3 As shown, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed such that they cover the gate 14a. Furthermore, as... Figure 3 As shown, the source 18a and drain 18b are arranged as terminal electrodes in a manner that separates them from each other on the second interlayer insulating film 17. Furthermore, as... Figure 3 As shown, the source 18a and drain 18b are electrically connected to the source region and drain region of the semiconductor layer 12a, respectively, via contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17.

[0040] like Figure 4As shown, the second TFT 9b is electrically connected to the corresponding first TFT 9a, power line 21a, and third TFT 9c in each sub-pixel P. Furthermore, the second TFT 9b has a substantially identical structure to the first TFT 9a and the third TFT 9c, which will be described later.

[0041] like Figure 4 As shown, the third TFT 9c is electrically connected to the corresponding second TFT 9b, power line 21a, and light-emitting control line 14e in each sub-pixel P. Furthermore, as... Figure 3 As shown, the third TFT 9c includes a semiconductor layer 12b, a gate insulating film 13, a gate 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, a source 18c, and a drain 18d, which are sequentially disposed on the base coating film 11. Here, as Figure 3 As shown, semiconductor layer 12b is disposed on the base coating film 11, and like semiconductor layer 12a, has a channel region, a source region, and a drain region. Furthermore, as... Figure 3 As shown, the gate insulating film 13 is provided in a manner that covers the semiconductor layer 12b. Furthermore, as... Figure 3 As shown, the gate 14b is disposed on the gate insulating film 13 in a manner that overlaps with the channel region of the semiconductor layer 12b. Furthermore, as... Figure 3 As shown, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed to cover the gate 14b. Furthermore, as... Figure 3 As shown, the source 18c and drain 18d are arranged as terminal electrodes in a manner that separates them from each other on the second interlayer insulating film 17. Furthermore, as... Figure 3 As shown, the source 18c and drain 18d are electrically connected to the source and drain regions of the semiconductor layer 12b, respectively, via contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Furthermore, as... Figure 3 As shown, the drain 18d is electrically connected to the relay electrode 21b via a contact hole formed on the first planarization film 19a and the inorganic insulating film 20a.

[0042] In addition, in this embodiment, a first TFT 9a, a second TFT 9b, and a third TFT 9c of the top gate type are shown, but the first TFT 9a, the second TFT 9b, and the third TFT 9c may also be of the bottom gate type.

[0043] like Figure 4 As shown, capacitor 9d is electrically connected to the corresponding first TFT 9a and power line 21a in each sub-pixel P. Here, as... Figure 3As shown, the capacitor 9d includes: a lower conductive layer 14c as a first wiring layer; a first interlayer insulating film 15 covering the lower conductive layer 14c; and an upper conductive layer 16a on the first interlayer insulating film 15 as a second wiring layer, overlapping the lower conductive layer 14c. Furthermore, the upper conductive layer 16a is electrically connected to the power line 21a via contact holes (not shown) formed in the second interlayer insulating film 17, the first planarization film 19a, and the inorganic insulating film 20a.

[0044] The first planarization film 19a, the second planarization film 22a, and the edge cover 32a described later are, for example, made of organic resin materials such as polyimide resin, acrylic resin, and phenolic varnish resin.

[0045] The inorganic insulating film 20a is provided to prevent the surface of the first planarization film 19a from being etched and contaminating the chamber of the dry etching apparatus during the patterning of the second wiring layer, such as the power line 21a, by dry etching. Furthermore, as... Figure 9 and Figure 10 As shown, in the inorganic insulating film 20a, in the imaging region Dc that overlaps with the group of sparse sub-pixels Pb, a first opening Maa and a second opening Mab are provided in a dotted manner, penetrating the inorganic insulating film 20a. Here, as... Figure 9 As shown, the first opening Maa is positioned along the boundary between the group of normal sub-pixels Pa and the group of sparse sub-pixels Pb. Furthermore, the center-to-center distance N between the first opening Maa and the contact hole H of the normal sub-pixel Pa closest to the first opening Maa (see reference) when viewed from above. Figure 10 For example, a diameter of 15 μm or more and 50 μm or less allows moisture in the first planarization film 19a to be easily released from the first opening Maa. Furthermore, as... Figure 9 As shown, the second opening Mab is disposed around each of the sparse sub-pixels Pb. In addition, the center-to-center distance between the second opening Mab and the contact hole of the sparse sub-pixel Pb corresponding to the second opening Mab is 15 μm or more and 50 μm or less when viewed from above, so that moisture in the first planarization film 19a can be easily released from the second opening Mab.

[0046] like Figure 3 and Figure 10 As shown, the relay electrode 21b is disposed on the inorganic insulating film 20a as a second wiring layer, and is formed in the same layer as the power line 21a using the same material.

[0047] like Figure 3 As shown, the organic EL element layer 35 includes a plurality of first electrodes 31a, an edge mask 32a, a plurality of organic EL layers 33, and a second electrode 34 disposed sequentially on the TFT layer 30a.

[0048] like Figure 3 As shown, a plurality of first electrodes 31a are arranged in a matrix on the second planarization film 22a in a manner corresponding to a plurality of sub-pixels P. Here, as... Figure 3 As shown, the first electrode 31a is connected via a contact hole H formed in the first planarization film 19a and the inorganic insulating film 20a (see reference). Figure 10 The contact holes formed on the relay electrode 21b and the second planarization film 22a are electrically connected to the drain 18d of each third TFT 9c. Furthermore, the first electrode 31a has the function of injecting holes into the organic EL layer 33. In addition, to improve the efficiency of injecting holes into the organic EL layer 33, it is more preferable to form the first electrode 31a with a high work function. Examples of materials constituting the first electrode 31a include, for example, metallic materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Furthermore, the material constituting the first electrode 31a may also be, for example, an alloy of astatine (At) / astatine oxide (AtO2). Furthermore, the material constituting the first electrode 31a can be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Additionally, the first electrode 31a can be formed by stacking multiple layers composed of the aforementioned materials. Furthermore, compound materials with high work functions can be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0049] like Figure 3 As shown, the edge mask 32a is configured in a grid pattern to cover the periphery of each first electrode 31a in a manner shared by multiple sub-pixels P.

[0050] like Figure 3 As shown, multiple organic EL layers 33 are disposed on multiple first electrodes 31a, arranged in a matrix shape to correspond to multiple sub-pixels P, serving as light-emitting functional layers. Here, as... Figure 5 As shown, each organic EL layer 33 has a hole injection layer 1, a hole transport layer 2, a light emission layer 3, an electron transport layer 4, and an electron injection layer 5 sequentially disposed on the first electrode 31a.

[0051] The hole injection layer 1, also known as the anode buffer layer, functions to bring the energy levels of the first electrode 31a and the organic EL layer 33 closer together, improves the hole injection efficiency from the first electrode 31a to the organic EL layer 33, and serves as a shared light-emitting functional layer for multiple sub-pixels P. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0052] The hole transport layer 2 has the function of improving the hole transport efficiency from the first electrode 31a to the organic EL layer 33, and is provided as a shared light-emitting functional layer shared by multiple sub-pixels P. Here, the materials constituting the hole transport layer 2 can be, for example, porphyrin derivatives, aromatic tertiary amine compounds, styrene-based amine derivatives, polyvinylcarbazole, poly-p-phenylene vinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrene-based anthracene derivatives, fluorenone derivatives, hydrazone derivatives, uranium derivatives, hydrogenated amorphous silicon, amorphous hydrogenated silicon carbide, zinc sulfide, or zinc selenide, etc.

[0053] The light-emitting layer 3 is provided as a separate light-emitting functional layer for each sub-pixel P, and is a region in which holes and electrons are injected from the first electrode 31a and the second electrode 34 respectively when a voltage is applied, and the holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminous efficiency. Furthermore, examples of materials constituting the light-emitting layer 3 include: metal hydroxyquinoline ketone compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bis(Styryl)Benzene derivatives, tristyrylbenzene derivatives, perylene derivatives, pyrene derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly(p-phenylenevinylene), or polysilanes, etc.

[0054] The electron transport layer 4 has the function of efficiently moving electrons to the light-emitting layer 3, and is provided as a shared light-emitting functional layer shared by multiple sub-pixels P. Here, as materials constituting the electron transport layer 4, examples of organic compounds include: diazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinone dimethane derivatives, biphenylquinone derivatives, fluorenone derivatives, thiophene derivatives, metal oxinoid compounds, etc.

[0055] The electron injection layer 5 functions to bring the energy levels of the second electrode 34 and the organic EL layer 33 closer together, thereby improving the efficiency of electron injection from the second electrode 34 into the organic EL layer 33. This function reduces the driving voltage of each organic EL element constituting the organic EL element layer 35. Furthermore, the electron injection layer 5 is also referred to as a cathode buffer layer, and is provided as a shared light-emitting functional layer shared by multiple sub-pixels P. Examples of materials constituting the electron injection layer 5 include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF), as well as alumina (Al2O3) and strontium oxide (SrO).

[0056] like Figure 3As shown, the second electrode 34 is shared by multiple sub-pixels P and is arranged to cover each organic EL layer 33 and the edge mask 32a. Furthermore, the second electrode 34 has the function of injecting electrons into the organic EL layer 33. In order to improve the efficiency of electron injection into the organic EL layer 33, the second electrode 34 is more preferably made of a material with a low work function. Examples of materials constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Furthermore, the second electrode 34 may also be formed from alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Additionally, the second electrode 34 may also be formed from conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Furthermore, the second electrode 34 may also be formed by stacking multiple layers of the above-mentioned materials. In addition, materials with low work functions include, for example, magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc.

[0057] like Figure 3 , Figure 6 , Figure 7 and Figure 10 As shown, the sealing film 40 includes a first inorganic sealing film 36, an organic sealing film 37, and a second inorganic sealing film 38, which are disposed and sequentially stacked on the second electrode 34 to cover it, and have the function of protecting each organic EL layer 33 of the organic EL element layer 35 from moisture and oxygen. Here, the first inorganic sealing film 36 and the second inorganic sealing film 38 are, for example, composed of inorganic insulating films such as silicon nitride film, silicon oxide film, and silicon oxynitride film. In addition, the organic sealing film 37 is, for example, composed of organic resin materials such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin.

[0058] In addition, such as Figure 1 As shown, the organic EL display panel 50a has a first outer outer blocking wall Wa, which is rectangular and surrounds the display area D, in the bezel area F, and a second outer outer blocking wall Wb, which is rectangular and surrounds the first outer outer blocking wall Wa.

[0059] like Figure 6 and Figure 7 As shown, the first outer barrier wall Wa includes: a lower resin layer 22b formed on the same layer as the second planarization film 22a; and an upper resin layer 32b formed on the same layer as the edge cover 32a. Additionally, as... Figure 6 and Figure 7 As shown, the first outer barrier wall Wa is provided in such a way that it overlaps with the outer peripheral end of the organic sealing film 37 of the sealing film 40, in order to suppress the diffusion of ink that becomes the organic sealing film 37 of the sealing film 40.

[0060] like Figure 6 and Figure 7 As shown, the second outer barrier wall Wb includes: a lower resin layer 19b formed on the same layer as the first planarization film 19a; a middle resin layer 22c formed on the same layer as the second planarization film 22a; and an upper resin layer 32c formed on the same layer as the edge cover 32a.

[0061] In addition, such as Figure 1 As shown, the organic EL display panel 50a has a first bezel wiring 18h in the bezel region F. This first bezel wiring 18h is configured as a first wiring layer, extending in a wide strip at the opening of the trench G, extending linearly inside the trench G on the display region D side, and extending to the terminal portion T at both ends opposite to the display region D. Here, the first bezel wiring 18h is configured to be electrically connected to the power line 21a on the display region D side of the bezel region F, and a high power supply voltage (ELVDD) is input at the terminal portion T. Furthermore, as... Figure 6 and Figure 7 As shown, the first border wiring 18h and the second border wiring 18i (described later) include a first metal layer 6, a second metal layer 7, and a third metal layer 8, which are formed on the same layer as the source electrodes 18a and 18c and the drain electrodes 18b and 18d, and are sequentially stacked from the resin substrate layer 10 side to the organic EL element layer 35 side. Here, the first metal layer 6 and the third metal layer 8 are formed, for example, of a titanium film with a thickness of about 100 nm to 200 nm, and the second metal layer 7 is formed, for example, of an aluminum film with a thickness of about 100 nm to 1000 nm. In addition, the source electrodes 18a and 18c, the drain electrodes 18b and 18d, the source line 18f, and the winding wiring 18j (described later) are also third wiring layers, just like the first border wiring 18h and the second border wiring 18i. Therefore, they include the first metal layer 6, the second metal layer 7, and the third metal layer 8 (not shown) sequentially stacked from the resin substrate layer 10 side to the organic EL element layer 35 side.

[0062] In addition, such as Figure 1As shown, the organic EL display panel 50a has a second bezel wiring 18i in the bezel area F. This second bezel wiring 18i is provided as a first wiring layer in a generally C-shape outside the trench G, and extends to the terminal portion T at both ends. Here, as... Figure 6 As shown, the second frame wiring 18i is configured to be electrically connected to the second electrode 34 via the first conductive layer 31b formed in the trench G, and a low power supply voltage (ELVSS) is input at the terminal portion T. Additionally, as... Figure 6 As shown, the first conductive layer 31b and the first electrode 31a are formed in the same layer from the same material. In the frame region F, they are arranged to overlap with the second frame wiring 18i and the second electrode 34, and to electrically connect the second frame wiring 18i and the second electrode 34 to each other.

[0063] In addition, such as Figure 8 As shown, the organic EL display panel 50a includes: a filling resin layer 25, which is disposed at the bend B in the bezel region F such that it fills the slit S formed in the undercoat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17; a plurality of lead-wound wires 18j disposed on the filling resin layer 25 and the second interlayer insulating film 17; and a covering resin layer 19c disposed such that it covers each lead-wound wire 18j. Additionally, as... Figure 8 As shown, the slit S is configured as a groove extending along the extension direction of the bend B, such that the surface of the resin substrate layer 10 is exposed by penetrating the undercoat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Furthermore, the filling resin layer 25 is made of an organic resin material such as polyimide resin. Additionally, multiple lead-wound wires 18j are arranged to extend parallel to each other in a direction orthogonal to the extension direction of the bend B. Here, as... Figure 8 As shown, the two ends of each lead-in wiring 18j are electrically connected to the first gate conductive layer 14f and the second gate conductive layer 14g respectively through contact holes formed in the laminated film of the first interlayer insulating film 15 and the second interlayer insulating film 17. Furthermore, as described above, the lead-in wiring 18j is provided as a first wiring layer and is formed in the same layer as the source electrodes 18a and 18c and the drain electrodes 18b and 18d, using the same material. Moreover, as... Figure 8 As shown, the first gate conductive layer 14f is disposed between the gate insulating film 13 and the first interlayer insulating film 15, and is electrically connected to the signal wiring (source line 18f, gate line 14d, etc.) extending in the display area D. Furthermore, as... Figure 8 As shown, the second gate conductive layer 14g is disposed between the gate insulating film 13 and the first interlayer insulating film 15, and is electrically connected to the terminal of the terminal portion T, for example. Furthermore, the covering resin layer 19c and the first planarization film 19a are formed of the same material in the same layer.

[0064] In the above-described organic EL display device 70, in each sub-pixel P, when a gate signal is input to the first TFT 9a via the gate line 14d, the first TFT 9a becomes conductive. When a predetermined voltage corresponding to the source signal is written to the gate 14b of the second TFT 9b and the capacitor 9d via the source line 18f, and a light emission control signal is input to the third TFT 9c via the light emission control line 14e, the third TFT 9c becomes conductive. Current corresponding to the gate voltage of the second TFT 9b is supplied from the power supply line 21a to the organic EL layer 33, and the light emitting layer 3 of the organic EL layer 33 emits light to perform image display. Further, in the organic EL display device 70, even when the first TFT 9a becomes non-conductive, the gate voltage of the second TFT 9b is held by the capacitor 9d, so that the light emission of the light emitting layer 3 is maintained in each sub-pixel P until the gate signal of the next frame is input. In addition, the organic EL display device 70 is configured to capture an image on the front side of the organic EL display panel 50a through the imaging unit 60 provided on the back side of the organic EL display panel 50a,隔着有机EL显示面板50a拍摄有机EL显示面板50a的正面侧的图像。

[0065] Next, a method for manufacturing the organic EL display device 70 of the present embodiment will be described. Here, the method for manufacturing the organic EL display device 70 of the present embodiment includes a TFT layer formation process, an organic EL element layer formation process, and a sealing film formation process.

[0066] <TFT layer formation process>

[0067] First, for example, a non-photosensitive polyimide resin (about 6 μm thick) is coated on a glass substrate, and the coated film is pre-baked and post-baked to form a resin substrate layer 10.

[0068] Next, for example, a silicon oxide film (about 500 nm thick) and a silicon nitride film (about 100 nm thick) are sequentially formed on the surface of the substrate on which the resin substrate layer 10 is formed by plasma CVD (chemical vapor deposition) to form a bottom coating film 11.

[0069] Then, by using plasma CVD, a semiconductor film such as an amorphous silicon film (about 30 nm to 100 nm thick) is formed on the surface of the substrate on which the bottom coating film 11 is formed. After the amorphous silicon film is crystallized by laser annealing or the like to form a polycrystalline silicon film, the semiconductor film is patterned to form semiconductor layers 12a, 12b, etc.

[0070] Furthermore, on the surface of the substrate on which the semiconductor layer 12a, etc. is formed, an inorganic insulating film such as a silicon oxide film (about 100 nm thick) is formed by, for example, plasma CVD to form a gate insulating film 13 so as to cover the semiconductor layer 12a, etc.

[0071] Next, on the substrate surface where the gate insulating film 13 is formed, a molybdenum film (with a thickness of about 100 nm to 400 nm) is formed, for example by sputtering, and the molybdenum film is patterned to form the third wiring layers such as gate 14a and 14b.

[0072] Then, using gates 14a and 14b as masks, impurity ions are doped, thereby conductorting a portion of semiconductor layers 12a and 12b.

[0073] Furthermore, for example, a silicon nitride film (with a thickness of about 50 nm to 200 nm) is formed on the surface of a substrate where a portion of the semiconductor layer 12a is conductive by plasma CVD, thereby forming a first interlayer insulating film 15.

[0074] Next, on the substrate surface where the first interlayer insulating film 15 is formed, a molybdenum film (with a thickness of about 100 nm to 400 nm) is formed, for example by sputtering, and the molybdenum film is patterned to form the fourth wiring layer, such as the upper conductive layer 16a.

[0075] Then, a silicon oxide film (thickness of about 100 nm to 500 nm) and a silicon nitride film (thickness of about 100 nm to 300 nm) are sequentially formed on the substrate surface on which the above-mentioned fourth wiring layer is formed by, for example, plasma CVD, thereby forming a second interlayer insulating film 17.

[0076] Then, a contact hole is formed by appropriately patterning the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.

[0077] Next, for example, by sputtering, titanium film (thickness about 50 nm), aluminum film (thickness about 600 nm), and titanium film (thickness about 50 nm) are sequentially formed on the surface of the substrate with the above-mentioned contact holes. These metal stacked films are then patterned to form the first wiring layers such as source 18a and 18c, drain 18b and 18d.

[0078] Then, using, for example, spin coating or slot coating, a photosensitive polyimide resin (approximately 2.5 μm thick) is coated on the substrate surface where the first wiring layer is formed. The coated film is then pre-baked, exposed, developed, and post-baked to form the first planarization film 19a.

[0079] Furthermore, on the substrate surface on which the first planarization film 19a is formed, for example, a silicon nitride film (thickness of about 100nm to 500nm) is sequentially formed by plasma CVD, and then an inorganic insulating film 20a is formed by patterning, which has an upper part with a contact hole H, a first opening Maa and a second opening Mab.

[0080] Furthermore, on the substrate surface where the inorganic insulating film 20a is formed, after forming a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 600 nm), and another titanium film (thickness of about 50 nm) sequentially by sputtering, these metal stacked films are patterned to form a second wiring layer such as power line 21a and relay electrode 21b.

[0081] Finally, by using, for example, spin coating or slot coating, a photosensitive polyimide resin (approximately 2.5 μm thick) is coated on the substrate surface on which the second wiring layer is formed, and then the coated film is pre-baked, exposed, developed and post-baked to form a second planarization film 22a.

[0082] As described above, a TFT layer 30a can be formed.

[0083] <Organic EL Component Layer Formation Process>

[0084] On the second planarization film 22a of the TFT layer 30a formed in the above-mentioned TFT layer formation process, a first electrode 31a, an edge mask 32a, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light emission layer 3, electron transport layer 4, electron injection layer 5), and a second electrode 34 are formed using known methods to form an organic EL element layer 35.

[0085] <Sealing film formation process>

[0086] First, on the surface of the substrate on which the organic EL element layer 35 is formed in the above-mentioned organic EL element layer formation process, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask, thereby forming a first inorganic sealing film 36.

[0087] Next, for example, an organic resin material such as acrylic resin is formed on the surface of the substrate on which the first inorganic sealing film 36 is formed by inkjet printing to form an organic sealing film 37.

[0088] Then, for the substrate on which the organic sealing film 37 is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask, thereby forming a second inorganic sealing film 38, and thus forming a sealing film 40.

[0089] As described above, the organic EL display panel 50a of this embodiment can be manufactured.

[0090] Furthermore, when the manufactured organic EL display panel 50a is fixed inside the frame, for example, an organic EL display device 70 can be manufactured by providing a camera unit 60 on the back side of the camera area Dc of the organic EL display panel 50a.

[0091] As described above, in the organic EL display device 70 according to this embodiment, the inorganic insulating film 20a on the first planarization film 19a has a first opening Maa and a second opening Mab provided in the imaging area Dc overlapping with the group of sparse sub-pixels Pb, penetrating the inorganic insulating film 20a. Here, the first opening Maa is provided along the boundary between the group of normal sub-pixels Pa and the group of sparse sub-pixels Pb, so that moisture in the first planarization film 19a can be released from the first opening Maa in the normal sub-pixel Pa adjacent to the sparse sub-pixels Pb. As a result, oxidation of the relay electrode 21b can be suppressed in the normal sub-pixel Pa adjacent to the sparse sub-pixels Pb, and the electrical connection between the relay electrode 21b and the first electrode 31a is good, thus suppressing poor illumination. Furthermore, the second opening Mab is disposed around each of the sparse sub-pixels Pb, so that moisture in the first planarization film 19a can be released from the second opening Mab in the sparse sub-pixels Pb. Therefore, oxidation of the relay electrode 21b can be suppressed in the sparse sub-pixels Pb, and the electrical connection between the relay electrode 21b and the first electrode 31a is good, suppressing poor illumination. Thus, the occurrence of poor illumination can be suppressed in the sparse sub-pixels Pb and the adjacent normal sub-pixels Pa.

[0092] Furthermore, in the organic EL display device 70 according to this embodiment, since an inorganic insulating film 20a is provided on the first planarization film 19a, when the second wiring layer such as the power line 21a is patterned by dry etching, the etching of the surface of the first planarization film 19a is suppressed, and contamination in the chamber of the dry etching device can be suppressed.

[0093] Second Implementation Method

[0094] Figure 11 This illustrates a second embodiment of the display device of the present invention. Here, Figure 11 This is a top view of the imaging area Dc and its surroundings of the organic EL display panel 50b, which constitutes the organic EL display device of this embodiment. Furthermore, in the following embodiments, [the following text refers to...]. Figures 1-10 Identical parts are labeled with the same reference numerals, and their detailed descriptions are omitted.

[0095] In the first embodiment described above, an organic EL display device 70 is illustrated, which has an organic EL display panel 50a having a first opening Maa and a second opening Mab provided in a dotted pattern in an inorganic insulating film 20a. However, in this embodiment, an organic EL display device is illustrated, which has an organic EL display panel 50b having a first opening Mba and a second opening Mbb provided in a strip pattern in an inorganic insulating film 20a.

[0096] The organic EL display device of this embodiment is similar to the organic EL display device 70 of the first embodiment described above, including: a display area D, which is rectangular and displays images; a camera area Dc, which is rectangularly arranged inside the display area D and displays images and captures images; and a border area F, which is rectangularly arranged around the display area D. Furthermore, the organic EL display device of this embodiment includes the organic EL display panel 50b described later and a camera unit 60 disposed on the resin substrate layer 10 side (back side) of the camera area Dc of the organic EL display panel 50b.

[0097] In the organic EL display panel 50b, such as Figure 11 As shown, in the inorganic insulating film 20a, in the imaging region Dc overlapping with the sparse sub-pixels Pb, a first opening Mba and a second opening Mbb are provided in a strip-like manner, penetrating the inorganic insulating film 20a. Here, as... Figure 11 As shown, the first opening Mba is U-shaped along the boundary between the group of normal sub-pixels Pa and the group of sparse sub-pixels Pb. Furthermore, as... Figure 11 As shown, the second opening Mb is arranged in a frame shape around each of the sparse sub-pixels Pb. Furthermore, the organic EL display panel 50b is otherwise substantially the same as the organic EL display panel 50a of the first embodiment described above.

[0098] The organic EL display device equipped with the organic EL display panel 50b, like the organic EL display device 70 of the first embodiment described above, is flexible. In each sub-pixel P, the light-emitting layer 3 of the organic EL layer 33 emits light appropriately via the first TFT 9a, the second TFT 9b, and the third TFT 9c, thereby displaying an image. Furthermore, the organic EL display device equipped with the organic EL display panel 50b is configured such that an image sensor 60 disposed on the back side of the organic EL display panel 50b captures an image of the front side of the organic EL display panel 50b through the organic EL display panel 50b.

[0099] An organic EL display device equipped with the organic EL display panel 50b of this embodiment can be manufactured by changing the pattern shape of the inorganic insulating film 20a in the manufacturing method of the organic EL display device 70 of the first embodiment described above.

[0100] As described above, in the organic EL display device according to this embodiment, the inorganic insulating film 20a on the first planarization film 19a has a first opening Mba and a second opening Mbb in the imaging region Dc overlapping with the group of sparse sub-pixels Pb, extending through the inorganic insulating film 20a. Here, the first opening Mba is U-shaped along the boundary between the group of normal sub-pixels Pa and the group of sparse sub-pixels Pb, thus allowing moisture in the first planarization film 19a to be further released from the first opening Mba in the normal sub-pixel Pa adjacent to the sparse sub-pixels Pb. Consequently, oxidation of the relay electrode 21b can be further suppressed in the normal sub-pixel Pa adjacent to the sparse sub-pixels Pb, ensuring good electrical connection between the relay electrode 21b and the first electrode 31a, further suppressing poor illumination. Furthermore, the second opening Mbb is arranged in a frame shape around each sparse sub-pixel Pb, thus allowing moisture in the first planarization film 19a to be further released from the second opening Mbb in the sparse sub-pixels Pb. Consequently, oxidation of the relay electrode 21b can be further suppressed in the sparse sub-pixels Pb, and the electrical connection between the relay electrode 21b and the first electrode 31a is good, further suppressing poor illumination. Therefore, poor illumination can be further suppressed in the sparse sub-pixels Pb and the adjacent normal sub-pixels Pa.

[0101] Furthermore, in the organic EL display device according to this embodiment, an inorganic insulating film 20a is provided on the first planarization film 19a. Therefore, when the second wiring layer such as the power line 21a is patterned by dry etching, the etching of the surface of the first planarization film 19a is suppressed, and contamination in the chamber of the dry etching device can be suppressed.

[0102] Third Implementation Method

[0103] Figure 12 and Figure 13 This illustrates a third embodiment of the display device of the present invention. Here, Figure 12 This is a top view of the imaging area Dc and its surroundings of the organic EL display panel 50c, which constitutes the organic EL display device of this embodiment. Furthermore, Figure 13 It is along Figure 12 A cross-sectional view of the camera area Dc and its surroundings of the organic EL display panel 50c along the XIII-XIII line.

[0104] In the first and second embodiments described above, an organic EL display device having organic EL display panels 50a and 50b having multiple openings in an inorganic insulating film 20a is exemplified. However, in this embodiment, an organic EL display device having an organic EL display panel 50c having a single opening Mc in an inorganic insulating film 20a is exemplified.

[0105] The organic EL display device of this embodiment is similar to the organic EL display device 70 of the first embodiment described above, including: a display area D, which is rectangular in shape and displays images; a camera area Dc, which is rectangular in shape inside the display area D and displays images and captures images; and a border area F, which is rectangular in shape around the display area D. Furthermore, the organic EL display device of this embodiment includes an organic EL display panel 50c (described later) and a camera unit 60 disposed on the resin substrate layer 10 side (back side) of the camera area Dc of the organic EL display panel 50c.

[0106] like Figure 13 As shown, the organic EL display panel 50c includes: a resin substrate layer 10; a TFT layer 30c disposed on the resin substrate layer 10; an organic EL element layer 35 disposed on the TFT layer 30c; and a sealing film 40 disposed on the organic EL element layer 35.

[0107] The TFT substrate 30c is the same as the TFT layer 30a in the first embodiment described above, such as... Figure 13 As shown, it includes an undercoat film 11 disposed on a resin substrate layer 10 and a plurality of first TFTs 9a and a plurality of second TFTs 9b disposed on the undercoat film 11 (see reference). Figure 4 The TFT layer 30c consists of multiple third TFTs 9c and multiple capacitors 9d. Furthermore, the TFT layer 30c is similar to the TFT layer 30a in the first embodiment described above, such as... Figure 13 As shown, it includes a first planarization film 19a, an inorganic insulating film 20a, and a second planarization film 22a sequentially disposed on each of the first TFTs 9a, each of the second TFTs 9b, each of the third TFTs 9c, and each of the capacitors 9d. Furthermore, in the TFT layer 30c, similarly to the TFT layer 30a of the first embodiment described above, as... Figure 13As shown, semiconductor layers 12a and 12b, gate insulating film 13, gate electrodes 14a and 14b, lower conductive layer 14c (third wiring layer), first interlayer insulating film 15, upper conductive layer 16a (fourth wiring layer), second interlayer insulating film 17, source electrodes 18a and 18c, drain electrodes 18b and 18d (first wiring layer), first planarization film 19a, inorganic insulating film 20a, power line 21a, relay electrode 21b (second wiring layer), and second planarization film 22a are sequentially stacked on the base coating film 11. Furthermore, in the TFT layer 30c, similar to the TFT layer 30a of the first embodiment, multiple gate lines 14d, multiple light-emitting control lines 14e, multiple source lines 18f, and power lines 21a are provided in the display area D. Furthermore, in the TFT layer 30c, similarly to the TFT layer 30a in the first embodiment described above, each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, a third TFT 9c, and a capacitor 9d. Here, in the imaging area Dc, as... Figure 12 As shown, gate line 14d and light-emitting control line 14e are thinned to 1 / 6 by removing 5 out of every 6 lines, and source line 18f is thinned to 1 / 4 by removing 3 out of every 4 lines. Additionally, in Figure 12 In the top view, the light control line 14e is omitted.

[0108] In the TFT layer 30c (organic EL display panel 50c), in the inorganic insulating film 20a, such as Figure 12 As shown, in the imaging region Dc that overlaps with the group of sparse sub-pixels Pb, an opening Mc is integrally formed in a manner that penetrates the inorganic insulating film 20a. Here, the opening Mc is as follows: Figure 12 As shown, its outer contour is rectangular, and an island-shaped inorganic insulating film 20a is provided below the relay electrode 21b of each sparse sub-pixel Pb inside it. Furthermore, the TFT layer 30c (organic EL display panel 50c) is otherwise substantially the same as the TFT layer 30a (organic EL display panel 50a) of the first embodiment described above.

[0109] The organic EL display device equipped with the organic EL display panel 50c, like the organic EL display device 70 of the first embodiment described above, is flexible and configured such that in each sub-pixel P, the light-emitting layer 3 of the organic EL layer 33 emits light appropriately via the first TFT 9a, the second TFT 9b, and the third TFT 9c, thereby displaying an image. Furthermore, the organic EL display device equipped with the organic EL display panel 50c is configured such that an image of the front side of the organic EL display panel 50c is captured through the organic EL display panel 50c by an imaging unit 60 disposed on the back side of the organic EL display panel 50c.

[0110] An organic EL display device equipped with the organic EL display panel 50c of this embodiment can be manufactured by patterning the portion other than the first opening Maa and the second opening Mab during the patterning of the inorganic insulating film 20a in the manufacturing method of the organic EL display device 70 of the first embodiment, forming a second wiring layer, and then patterning the inorganic insulating film 20a again to form the opening Mc.

[0111] As described above, in the organic EL display device according to this embodiment, an opening Mc is provided through the inorganic insulating film 20a on the first planarization film 19a in the imaging region Dc that overlaps with the group of sparse sub-pixels Pb. Here, the opening Mc is integrally provided over approximately the entire area of ​​the imaging region Dc, thus allowing moisture in the first planarization film 19a to be further released from the opening Mc in the sparsely populated sub-pixels Pb and the adjacent normal sub-pixels Pa. Consequently, oxidation of the relay electrode 21b can be further suppressed in the sparsely populated sub-pixels Pb and the adjacent normal sub-pixels Pa, and the electrical connection between the relay electrode 21b and the first electrode 31a is good, further suppressing poor illumination.

[0112] Furthermore, in the organic EL display device according to this embodiment, an inorganic insulating film 20a is provided on the first planarization film 19a. Therefore, when the second wiring layer such as the power line 21a is patterned by dry etching, the etching of the surface of the first planarization film 19a is suppressed, and contamination in the chamber of the dry etching device can be suppressed.

[0113] Other Implementation Methods

[0114] In the above embodiments, an organic EL layer with a five-layer stacked structure of hole injection layer, hole transport layer, light emission layer, electron transport layer and electron injection layer is exemplified. However, the organic EL layer may also be a three-layer stacked structure of hole injection layer as hole transport layer, light emission layer and electron transport layer as electron injection layer.

[0115] Furthermore, in the above embodiments, an organic EL display device with the first electrode as the anode and the second electrode as the cathode was illustrated. However, the present invention can also be applied to an organic EL display device with the stacked structure of the organic EL layer reversed, with the first electrode as the cathode and the second electrode as the anode.

[0116] Furthermore, in the above embodiments, an organic EL display device is illustrated in which the electrode of the TFT connected to the first electrode is used as the drain electrode. However, the present invention can also be applied to organic EL display devices in which the electrode of the TFT connected to the first electrode is used as the source electrode.

[0117] Furthermore, in the above embodiments, an organic EL display device was described as an example of a display device, but the present invention can be applied to display devices having multiple light-emitting elements driven by current, for example, to display devices having light-emitting elements having a layer of quantum dots, i.e., QLED (Quantum-dot light emiTFTing diode).

[0118] Industrial availability

[0119] As described above, the present invention is useful for flexible display devices.

[0120] Explanation of reference numerals in the attached figures

[0121] D: Display area

[0122] Dc: Camera area

[0123] H: Contact hole

[0124] Maa, Mba: First opening

[0125] Mab, Mbb: Second opening

[0126] Mc: Opening

[0127] P: Subpixel

[0128] Pa: Typically a subpixel

[0129] Pb: Sparse subpixel

[0130] 10: Resin substrate layer (base substrate layer)

[0131] 12a, 12b: Semiconductor layers

[0132] 13: Gate insulating film

[0133] 14a, 14b: Gate (third wiring layer)

[0134] 14c: Lower conductive layer (third wiring layer)

[0135] 15: First interlayer insulating film

[0136] 16a: Upper conductive layer (fourth wiring layer)

[0137] 17: Second interlayer insulating film

[0138] 18a, 18c: Source (first wiring layer)

[0139] 18b, 18d: Drain electrode (first wiring layer, terminal electrode)

[0140] 19a: First planarization film

[0141] 20a: Inorganic insulating film

[0142] 21a: Power cable (second wiring layer)

[0143] 21b: Relay electrode (second wiring layer)

[0144] 22a: Second planarization film

[0145] 30a, 30c: TFT layer (thin-film transistor layer)

[0146] 31a: First electrode

[0147] 33: Organic EL layer (organic electroluminescent layer, light-emitting functional layer)

[0148] 34: Second electrode

[0149] 35: Organic EL element layer (light-emitting element layer)

[0150] 40: Sealing film

[0151] 50a, 50b, 50c: Organic EL display panels

[0152] 60: Camera Department

[0153] 70: Organic EL display device

Claims

1. A display device having a display panel, the display panel comprising: Substrate layer; A thin-film transistor layer is disposed on the substrate layer and has a first wiring layer, a first planarization film, an inorganic insulating film, a second wiring layer, and a second planarization film stacked sequentially. The light-emitting element layer is disposed on the thin-film transistor layer, corresponding to multiple sub-pixels constituting the display area, and is sequentially stacked with multiple first electrodes, multiple light-emitting functional layers and a common second electrode; as well as A sealing film is disposed on the light-emitting element layer. A camera unit is provided on the substrate layer side of the display area of ​​the display panel, and the display device is characterized in that... The plurality of sub-pixels are divided into groups of normal sub-pixels and groups of sparse sub-pixels. The groups of normal sub-pixels are configured not to overlap with the camera unit, while the groups of sparse sub-pixels are configured to overlap with the camera unit and are sparsified compared to the groups of normal sub-pixels. In the inorganic insulating film, an opening is provided in the imaging area that overlaps with the group of sparse sub-pixels, penetrating the inorganic insulating film. The openings are arranged in a dotted pattern. The opening includes: Multiple first openings are provided along the boundary between the group of normal sub-pixels and the group of sparse sub-pixels; as well as Multiple second openings are disposed around each of the sparse sub-pixels.

2. The display device according to claim 1, characterized in that, The thin-film transistor layer includes: terminal electrodes of the thin-film transistor disposed as the first wiring layer; and relay electrodes disposed as the second wiring layer. The relay electrode is electrically connected to the corresponding first electrode in each sub-pixel.

3. The display device according to claim 2, characterized in that, In each of the general sub-pixels, a contact hole is formed in the first planarization film and the inorganic insulating film. The contact hole is used for electrically connecting the terminal electrode and the relay electrode. The center-to-center distance between each first opening and the contact hole of the ordinary sub-pixel closest to each first opening is less than 50 μm when viewed from above.

4. The display device according to claim 2, characterized in that, In each of the sparse sub-pixels, contact holes are formed in the first planarization film and the inorganic insulating film. These contact holes are used to electrically connect the terminal electrode and the relay electrode. The center-to-center distance between each of the second openings and the contact holes of the sparse sub-pixels corresponding to each of the second openings is less than 50 μm when viewed from above.

5. The display device according to claim 1, characterized in that, include: The thin-film transistor layer, on the substrate layer side of the first wiring layer, includes a semiconductor layer, a gate insulating film, a third wiring layer, a first interlayer insulating film, a fourth wiring layer, and a second interlayer insulating film, which are sequentially stacked from the substrate layer side to the first wiring layer side.

6. The display device according to claim 1, characterized in that, The display area is set to a rectangular shape. The camera area is located in the middle of a portion along one side of the display area.

7. The display device according to claim 1, characterized in that, Each of the light-emitting functional layers is an organic electroluminescent layer.

8. A display device having a display panel, the display panel comprising: Substrate layer; A thin-film transistor layer is disposed on the substrate layer and has a first wiring layer, a first planarization film, an inorganic insulating film, a second wiring layer, and a second planarization film stacked sequentially. The light-emitting element layer is disposed on the thin-film transistor layer, corresponding to multiple sub-pixels constituting the display area, and is sequentially stacked with multiple first electrodes, multiple light-emitting functional layers and a common second electrode; as well as A sealing film is disposed on the light-emitting element layer. A camera unit is provided on the substrate layer side of the display area of ​​the display panel, and the display device is characterized in that... The plurality of sub-pixels are divided into groups of normal sub-pixels and groups of sparse sub-pixels. The groups of normal sub-pixels are configured not to overlap with the camera unit, while the groups of sparse sub-pixels are configured to overlap with the camera unit and are sparsified compared to the groups of normal sub-pixels. In the inorganic insulating film, an opening is provided in the imaging area that overlaps with the group of sparse sub-pixels, penetrating the inorganic insulating film. The opening is configured as a strip. The opening includes: The first opening is arranged in a U-shape along the boundary between the group of normal sub-pixels and the group of sparse sub-pixels; as well as Multiple second openings are arranged in a frame shape around each of the sparse sub-pixels.

9. The display device according to claim 8, characterized in that, include: The thin-film transistor layer, on the substrate layer side of the first wiring layer, includes a semiconductor layer, a gate insulating film, a third wiring layer, a first interlayer insulating film, a fourth wiring layer, and a second interlayer insulating film, which are sequentially stacked from the substrate layer side to the first wiring layer side.

10. The display device according to claim 8, characterized in that, The display area is set to a rectangular shape. The camera area is located in the middle of a portion along one side of the display area.

11. The display device according to claim 8, characterized in that, Each of the light-emitting functional layers is an organic electroluminescent layer.

12. A display device having a display panel, the display panel comprising: Substrate layer; A thin-film transistor layer is disposed on the substrate layer and has a first wiring layer, a first planarization film, an inorganic insulating film, a second wiring layer, and a second planarization film stacked sequentially. The light-emitting element layer is disposed on the thin-film transistor layer, corresponding to multiple sub-pixels constituting the display area, and is sequentially stacked with multiple first electrodes, multiple light-emitting functional layers and a common second electrode; as well as A sealing film is disposed on the light-emitting element layer. A camera unit is provided on the substrate layer side of the display area of ​​the display panel, and the display device is characterized in that... The plurality of sub-pixels are divided into groups of normal sub-pixels and groups of sparse sub-pixels. The groups of normal sub-pixels are configured not to overlap with the camera unit, while the groups of sparse sub-pixels are configured to overlap with the camera unit and are sparsified compared to the groups of normal sub-pixels. In the inorganic insulating film, an opening is provided in the imaging area that overlaps with the group of sparse sub-pixels, penetrating the inorganic insulating film. The opening is integrally provided in the camera area.

13. The display device according to claim 12, characterized in that, include: The thin-film transistor layer, on the substrate layer side of the first wiring layer, includes a semiconductor layer, a gate insulating film, a third wiring layer, a first interlayer insulating film, a fourth wiring layer, and a second interlayer insulating film, which are sequentially stacked from the substrate layer side to the first wiring layer side.

14. The display device according to claim 12, characterized in that, The display area is set to a rectangular shape. The camera area is located in the middle of a portion along one side of the display area.

15. The display device according to claim 12, characterized in that, Each of the light-emitting functional layers is an organic electroluminescent layer.

Images