Power switch circuit, electronic product and power generation method

Abstract

The application provides a power switch circuit, an electronic product and a power generation method, which comprise a PMOS tube, a source electrode of which is connected with a battery voltage, and a drain electrode of which is connected with an upper plate of a capacitor; a lower plate of a first capacitor is connected with a ground; a first resistor, a first end of which is connected with a gate electrode of the PMOS tube; a wake-up module, which is connected between the battery voltage and a reference ground, accepts a button control, and has an output end connected with a second end of the first resistor, provides a first voltage for the second end of the first resistor based on the button control, and turns on the PMOS tube to output a wake-up signal; and a power-up module, which is connected between the second end of the first resistor and the reference ground, provides a second voltage for the second end of the first resistor when the wake-up signal is valid, and continuously turns on the PMOS tube to charge the first capacitor; wherein the first voltage is greater than the second voltage. The power switch circuit, the electronic product and the power generation method of the application slow down the opening of the PMOS tube when the button is pressed, increase the Miller platform time of the PMOS tube, and thus reduce the impact voltage of the power supply, and avoid the failure of electronic components.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and in particular to a power switching circuit, electronic products, and a power generation method. Background Technology

[0002] With the development of science and technology, the demand for mobile devices is increasing, especially handheld electronic devices such as fascia guns and electronic thermometers. As a result, the main control boards for these electronic products are becoming smaller and smaller due to the limited size of these devices.

[0003] When designing the main control board, many complex circuits are simplified; however, this simplification process often introduces circuit interference problems. For example, when the PMOS switching circuit of the power supply is turned on, the voltage surge can be too high, causing some electronic components to fail.

[0004] Therefore, how to solve the device failure problem caused by voltage overshoot when the PMOS switching circuit is turned on has become one of the technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power switch circuit, electronic product and power generation method to solve the problem of device failure caused by voltage overshoot when the PMOS switch circuit is turned on in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a power switch circuit, the power switch circuit comprising at least:

[0007] PMOS transistor, first resistor, first capacitor, wake-up module and power-on module;

[0008] The source of the PMOS transistor is connected to the battery voltage, and the drain is connected to the upper plate of the first capacitor; the lower plate of the first capacitor is grounded.

[0009] The first end of the first resistor is connected to the gate of the PMOS transistor;

[0010] The wake-up module is connected between the battery voltage and the reference ground, accepts button control, and its output terminal is connected to the second terminal of the first resistor. Based on the button control, it provides a first voltage to the second terminal of the first resistor to conduct the wake-up power-on signal of the PMOS transistor.

[0011] The power-on module is connected between the second end of the first resistor and the reference ground, receives the power-on signal, and provides a second voltage to the second end of the first resistor when the power-on signal is valid, so as to continuously conduct the PMOS transistor to charge the first capacitor.

[0012] Wherein, the first voltage is greater than the second voltage.

[0013] Alternatively, the wake-up module includes a second resistor, a third resistor, a diode, and a button; the first end of the second resistor is connected to the battery voltage, and the second end is connected to the first end of the third resistor; the second end of the third resistor is connected to the anode of the diode; and the cathode of the diode is connected to the reference ground via the button.

[0014] Alternatively, the wake-up module may further include a second capacitor connected in parallel across the two ends of the second resistor.

[0015] Alternatively, the power-on module includes a fourth resistor and a transistor; the first end of the fourth resistor is connected to the second end of the first resistor, and the second end is connected to the first end of the transistor; the second end of the transistor is connected to the reference ground, and the control terminal receives the power-on signal.

[0016] Alternatively, the power-on module may further include a fifth resistor, through which the power-on signal is connected to the control terminal of the transistor.

[0017] To achieve the above and other related objectives, the present invention also provides an electronic product, which includes at least the above-described power switch circuit.

[0018] To achieve the above and other related objectives, the present invention also provides a power generation method based on the above-described power switching circuit, wherein the power generation method includes at least:

[0019] Press the button to generate a first voltage, charge the gate of the PMOS transistor based on the first voltage, and slow down the charging speed based on the first resistance of the gate of the PMOS transistor to turn on the PMOS transistor.

[0020] The battery voltage charges the first capacitor through the PMOS transistor, generating the working voltage for the wake-up power-on signal.

[0021] After the power-on signal is valid, a second voltage is generated to continuously turn on the PMOS transistor to charge the first capacitor and provide a stable and continuous operating voltage.

[0022] Optionally, pressing the button establishes a voltage divider path from the battery voltage to the reference ground, and the surge voltage is mitigated by the capacitance between the gate and source of the PMOS transistor to obtain the first voltage.

[0023] Alternatively, the first voltage is set to 5V to 8V.

[0024] Alternatively, the second voltage is set to 1V to 3V.

[0025] As described above, the power switch circuit, electronic product, and power generation method of the present invention have the following beneficial effects:

[0026] The power switch circuit, electronic product, and power generation method of the present invention slow down the turn-on of the PMOS transistor when the button is pressed, increase the Miller plateau time of the PMOS transistor, thereby reducing the surge voltage of the power supply and preventing electronic component failure. Attached Figure Description

[0027] Figure 1 The diagram shows the circuit structure of a PMOS power switch circuit.

[0028] Figure 2 The diagram shown is a structural schematic of the power switch circuit of the present invention.

[0029] Figure 3 The diagram shows the test waveforms of a PMOS power switch circuit.

[0030] Figure 4 The diagram shows a test waveform of the power switch circuit of the present invention.

[0031] Component designation explanation

[0032] 1 PMOS power switch circuit

[0033] 2 Power switch circuit

[0034] 21. Wake-up Module

[0035] 22 Power-on module Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content described in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Please see Figures 1-4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] like Figure 1The diagram shows a PMOS power switch circuit 1, including resistors Ra, Rb, Rc, a PMOS transistor Qa, a transistor Qb, a diode Da, a button Sa, and a capacitor Ca. The source of the PMOS transistor Qa is connected to the battery voltage BAT, and its drain is connected to the capacitor Ca. One end of resistor Ra is connected to the battery voltage BAT, and the other end is grounded via the anode of diode Da, the cathode of diode Da, and the button Sa. One end of resistor Rb is connected to the gate of PMOS transistor Qa, and the other end is grounded via the collector and emitter of transistor Qb. The base of transistor Qb is connected to the power-on signal PWR_ON via resistor Rc. The working principle of the PMOS power switch circuit 1 is as follows:

[0039] 11) Press button Sa, button Sa is turned on. The battery voltage BAT is connected to the reference ground through resistor Ra, diode Da and button Sa. At this time, the gate-source voltage of PMOS transistor Qa becomes -12V through the voltage drop of diode Da, and PMOS transistor Qa is turned on.

[0040] 12) The battery voltage BAT is transferred to the upper plate of capacitor Ca through the drain and source of PMOS transistor Qa, charging capacitor Ca and thus providing the working voltage VDD.

[0041] 13) The operating voltage VDD powers the microcontroller. When the microcontroller is awakened, it outputs a power-on signal PWR_ON (output voltage 3.3V), which turns on the transistor Qb through resistor Rc. The battery voltage BAT, divided by resistors Ra and Rb, makes the gate voltage of the PMOS transistor 1.1V and the gate-source voltage 11.5V; the PMOS transistor Qa remains on, supplying power to the operating voltage VDD.

[0042] However, due to pressing the button too quickly, when the button is pressed, the battery voltage immediately flows to ground through resistor Ra, diode Da, and button Sa, and the gate-source voltage of PMOS transistor Qa instantly becomes 12V; this quickly turns on PMOS transistor Qa. Because the turn-on time is too fast, it will instantly create a surge in the operating voltage VDD. The surge voltage was measured to be twice the battery voltage BAT, which in turn will impact the downstream components and cause them to fail.

[0043] For the reasons mentioned above, this invention proposes an optimization scheme to reduce the surge voltage and thus prevent component failure. The specific scheme is as follows:

[0044] like Figure 2 As shown, the present invention provides a power switch circuit 2, the power switch circuit 2 comprising:

[0045] PMOS transistor Q1, first resistor R1, first capacitor C1, wake-up module 21 and power-on module 22.

[0046] like Figure 2As shown, the source of the PMOS transistor Q1 is connected to the battery voltage BAT, and the drain is connected to the upper plate of the capacitor C1; the lower plate of the first capacitor C1 is grounded.

[0047] Specifically, the first capacitor C1 is charged by turning on the PMOS transistor Q1, thereby obtaining the operating voltage VDD. In this embodiment, the battery voltage BAT is set to 12.6V; the operating voltage VDD is set to 12V, but can be set as needed in actual use.

[0048] like Figure 2 As shown, the first end of the first resistor R1 is connected to the gate of the PMOS transistor Q1.

[0049] Specifically, the first resistor R1 is connected to the gate of the PMOS transistor Q1 to slow down the charging rate of the gate charge Qg of the PMOS transistor Q1 and lengthen the Miller plateau time of the PMOS transistor Q1. As an example, the resistance value of the first resistor R1 is set to 1KΩ, but it can be set as needed in actual use.

[0050] like Figure 2 As shown, the wake-up module 21 is connected between the battery voltage BAT and the reference ground, accepts the control of button S1, and its output terminal is connected to the second terminal of the first resistor R1. Based on the control of button S1, it provides a first voltage to the second terminal of the first resistor R1 to conduct the wake-up power-on signal of the PMOS transistor Q1.

[0051] Specifically, the wake-up module 21 turns on the PMOS transistor Q1 based on the pressing of the button S1, and turns off the PMOS transistor Q1 after the pressing of the button S1 ends. The wake-up module 21 briefly turns on the PMOS transistor Q1 (the duration of which is determined by the pressing time of the button S1) to provide the operating voltage VDD to wake up the control module (not shown in the figure) that generates the power-on signal PWR_ON. The control module includes, but is not limited to, a microcontroller.

[0052] Specifically, in this embodiment, the wake-up module 21 includes a second resistor R2, a third resistor R3, a diode D1, and a button S1. The first end of the second resistor R2 is connected to the battery voltage BAT, and the second end is connected to the first end of the third resistor R3. The second end of the third resistor R3 is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the reference ground via the button S1. The second resistor R2 and the third resistor R3 divide the battery voltage BAT to obtain the first voltage, which is then provided to the gate of the PMOS transistor Q1 via the first resistor R1. As an example, the resistance value of the second resistor R2 is set to 10KΩ.

[0053] In another implementation of the present invention, the wake-up module 21 further includes a second capacitor C2, which is connected in parallel across the second resistor R2 to reduce the inrush voltage. As an example, the capacitance of the second capacitor C2 is set to 100nF.

[0054] like Figure 2 As shown, the power-on module 22 is connected between the second terminal of the first resistor R1 and the reference ground, and receives the power-on signal PWR_ON. When the power-on signal PWR_ON is valid, it provides a second voltage to the second terminal of the first resistor R1 to continuously turn on the PMOS transistor Q1 to charge the first capacitor C1.

[0055] Specifically, the power-on module 22 continuously turns on the PMOS transistor Q1 based on the power-on signal PWR_ON to provide a stable voltage (operating voltage VDD) required for circuit operation, thereby achieving continuous power supply.

[0056] Specifically, in this embodiment, the power-on module 22 includes a fourth resistor R4 and a transistor Q2. The first end of the fourth resistor R4 is connected to the second end of the first resistor R1, and the second end is connected to the first end of the transistor Q2. The second end of the transistor Q2 is connected to the reference ground, and its control terminal receives the power-on signal PWR_ON. After the transistor Q2 is turned on, the second resistor R2 and the fourth resistor R4 divide the battery voltage BAT to obtain the second voltage. This second voltage is provided to the gate of the PMOS transistor Q1 via the first resistor R1, wherein the second voltage is less than the first voltage. As an example, the transistor Q2 is an NPN transistor, with its collector as the first terminal, its emitter as the second terminal, and its base as the control terminal. In actual use, the appropriate device type can be selected as needed, and the connection relationships of each port can be adjusted adaptively, which will not be elaborated here. As an example, the resistance value of the fourth resistor R4 is set to 1KΩ.

[0057] In another implementation of the present invention, the power-on module 22 further includes a fifth resistor R5, and the power-on signal PWR_ON is connected to the control terminal of the transistor Q2 via the fifth resistor R5 to limit the current at the control terminal of the transistor Q2. As an example, the resistance value of the fifth resistor R5 is set to 1KΩ.

[0058] The power switch circuit 2 is used to generate power, and its working principle is as follows:

[0059] 21) Press the button to generate a first voltage, charge the gate of the PMOS transistor based on the first voltage, and slow down the charging speed based on the first resistance of the gate of the PMOS transistor to turn on the PMOS transistor.

[0060] Specifically, pressing button S1 establishes a voltage divider path from the battery voltage BAT to the reference ground, and mitigates the surge voltage through the capacitor between the gate and source of the PMOS transistor Q1 (the second capacitor C2), thereby obtaining the first voltage. More specifically, pressing button S1 turns it on; the battery voltage BAT charges the second capacitor C2, and the voltage is connected to the reference ground via the second resistor R2, the third resistor R3, the diode D1, and button S1; the connection node between the second resistor R2 and the third resistor R3 outputs the first voltage. The first voltage charges the gate of the PMOS transistor Q1 via the first resistor R1, turning on the PMOS transistor Q1. Due to the presence of the first resistor R1, the charging speed of the gate of the PMOS transistor Q1 is slowed down.

[0061] Specifically, in this embodiment, the first voltage is set to 5V to 8V, including but not limited to 6V; in actual use, the value of the first voltage can be determined according to the parameter characteristics of the PMOS transistor Q1, and is not limited to this embodiment. As an example, the gate voltage of the PMOS transistor Q1 is 6V, and the gate-source voltage VGS becomes -6V.

[0062] 22) The battery voltage charges the first capacitor through the PMOS transistor, generating the working voltage for the wake-up power-on signal.

[0063] Specifically, in this embodiment, the PMOS transistor Q1 is turned on, and the battery voltage BAT charges the first capacitor C1 via the PMOS transistor Q1, generating the operating voltage for waking up the microcontroller. The microcontroller is then used to generate the power-on signal PWR_ON. In practical use, the method for generating the power-on signal PWR_ON can be set as needed.

[0064] 23) After the power-on signal is valid, a second voltage is generated to continuously turn on the PMOS transistor to charge the first capacitor and provide a stable and continuous operating voltage.

[0065] Specifically, in this embodiment, after the microcontroller is woken up, it generates a 3.3V power-on signal PWR_ON, which turns on the transistor Q2 via the fifth resistor R5. The battery voltage BAT is divided by the second resistor R2 and the fourth resistor R4 to obtain a second voltage. In this embodiment, the second voltage is set to 1V to 3V, including but not limited to 1.1V. In actual use, the value of the second voltage can be determined according to the parameter characteristics of the PMOS transistor Q1, and is not limited to this embodiment. As an example, the gate voltage of the PMOS transistor Q1 is 1.1V, and the gate-source voltage VGS becomes -11.5V. The PMOS transistor Q1 is kept on via the first resistor R1, providing a stable and continuous operating voltage VDD.

[0066] Specifically, when button S1 is pressed, the impact voltage is reduced due to the effect of the second capacitor C2; the gate voltage of the PMOS transistor Q1 is divided into 6V through the series voltage division of the second resistor R2 and the third resistor R3, which reduces the gate-source voltage VGS of the PMOS transistor Q1; at the same time, due to the effect of the first resistor R1, the charging time of the gate charge Qg of the PMOS transistor Q1 is lengthened, the Miller plateau time side of the PMOS transistor Q1 is lengthened, the turn-on time is slowed down, and the impact voltage is reduced.

[0067] Figure 3 The test waveform diagram of PMOS power switch circuit 1 is shown below; Figure 4 The diagram shows the test waveforms of the power switch circuit 2 of this invention. It can be seen that when the PMOS transistor is turned on, the power supply voltage of the PMOS power switch circuit 1 surges to 25.74V, while with the power switch circuit 2 of this invention, the surge voltage drops to 13.86V. Therefore, the power switch circuit 2 of this invention significantly reduces the surge voltage when the PMOS transistor is turned on, greatly reducing the probability of failure of components with lower voltage withstand capability, and improving the reliability and stability of the product.

[0068] The present invention also provides an electronic product, the electronic product including the power switch circuit 2, thereby achieving power stability and reliability of the electronic product.

[0069] In summary, this invention provides a power switch circuit, an electronic product, and a power generation method, comprising: a PMOS transistor, a first resistor, a first capacitor, a wake-up module, and a power-on module; the source of the PMOS transistor is connected to the battery voltage, and the drain is connected to the upper plate of the first capacitor; the lower plate of the first capacitor is grounded; the first end of the first resistor is connected to the gate of the PMOS transistor; the wake-up module is connected between the battery voltage and a reference ground, receives button control, and its output is connected to the second end of the first resistor, providing a first voltage to the second end of the first resistor based on the button control to conduct a wake-up power-on signal for the PMOS transistor; the power-on module is connected between the second end of the first resistor and the reference ground, receives the power-on signal, and provides a second voltage to the second end of the first resistor when the power-on signal is valid, continuously conducting the PMOS transistor to charge the first capacitor; wherein, the first voltage is greater than the second voltage. The power switch circuit, electronic product, and power generation method of this invention slow down the turn-on of the PMOS transistor when a button is pressed, increasing the Miller plateau time of the PMOS transistor, thereby reducing the power supply surge voltage and preventing electronic component failure. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A power switch circuit, characterized in that, The power switch circuit includes at least: PMOS transistor, first resistor, first capacitor, wake-up module and power-on module; The source of the PMOS transistor is connected to the battery voltage, and the drain is connected to the upper plate of the first capacitor; the lower plate of the first capacitor is grounded. The first end of the first resistor is connected to the gate of the PMOS transistor; The wake-up module is connected between the battery voltage and the reference ground, accepts button control, and its output terminal is connected to the second terminal of the first resistor. Based on the button control, it provides a first voltage to the second terminal of the first resistor to conduct the wake-up power-on signal of the PMOS transistor. The power-on module is connected between the second end of the first resistor and the reference ground, receives the power-on signal, and provides a second voltage to the second end of the first resistor when the power-on signal is valid, so as to continuously conduct the PMOS transistor to charge the first capacitor. Wherein, the first voltage is greater than the second voltage.

2. The power switch circuit according to claim 1, characterized in that: The wake-up module includes a second resistor, a third resistor, a diode, and a button; the first end of the second resistor is connected to the battery voltage, and the second end is connected to the first end of the third resistor; the second end of the third resistor is connected to the anode of the diode; the cathode of the diode is connected to the reference ground via the button.

3. The power switch circuit according to claim 2, characterized in that: The wake-up module also includes a second capacitor, which is connected in parallel across the two ends of the second resistor.

4. The power switch circuit according to any one of claims 1-3, characterized in that: The power-on module includes a fourth resistor and a transistor; the first end of the fourth resistor is connected to the second end of the first resistor, and the second end is connected to the first end of the transistor; the second end of the transistor is connected to the reference ground, and the control terminal receives the power-on signal.

5. The power switch circuit according to claim 4, characterized in that: The power-on module also includes a fifth resistor, through which the power-on signal is connected to the control terminal of the transistor.

6. An electronic product, characterized in that, The electronic product includes at least the power switch circuit as described in any one of claims 1-5.

7. A power generation method, implemented based on the power switching circuit according to any one of claims 1-5, characterized in that, The power generation method includes at least: Press the button to generate a first voltage, charge the gate of the PMOS transistor based on the first voltage, and slow down the charging speed based on the first resistance of the gate of the PMOS transistor to turn on the PMOS transistor. The battery voltage charges the first capacitor through the PMOS transistor, generating the working voltage for the wake-up power-on signal. After the power-on signal is valid, a second voltage is generated to continuously turn on the PMOS transistor to charge the first capacitor and provide a stable and continuous operating voltage.

8. The power generation method according to claim 7, characterized in that: Pressing the button establishes a voltage divider path from the battery voltage to the reference ground, and the surge voltage is mitigated by the capacitance between the gate and source of the PMOS transistor to obtain the first voltage.

9. The power generation method according to claim 7 or 8, characterized in that: The first voltage is set to 5V to 8V.

10. The power generation method according to claim 9, characterized in that: The second voltage is set to 1V to 3V.

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