Power supply controller with noise rejection

Abstract

A power supply controller with noise rejection is described. In one embodiment, a controller for a power supply includes a first switching circuit having a first controller; and a second switching circuit having a second controller. The second controller is configured to generate a pattern of transmitted signals UTX. Received signals URX are a pattern of transmitted signals UTX combined with noise. The first controller includes a pattern filter configured for comparing the received signals URX with an expected pattern. When the pattern of received signals URX corresponds to the expected pattern of received signals URX, the pattern filter asserts a first command to initiate a charging cycle.

Description

POWER SUPPLY CONTROLLER WITH NOISE REJECTIONBACKGROUND OF THE INVENTIONField of the Invention

[0001] The present disclosure relates generally to power converters, and more particularly, to controllers for power converters.Discussion of the Related Art

[0002] Electronic devices use power to operate. Switched mode power converters, also referred to as switching power converters, are commonly used to power many of today's electronics due to their high efficiency, small size and low weight. In a switched mode power converter, a high voltage alternating current (ac) or direct current (de) input is converted to provide an output through an energy transfer element. The output is typically a well-regulated direct current (de) voltage or a de current of a power supply that may be included in a power conversion system. The switched mode power conversion system usually provides output regulation by sensing one or more signals representative of one or more output quantities and controlling the output in a closed loop. In operation, a switch is utilized to provide the desired output by varying the duty cycle (typically the ratio of the on time of the switch to the total switching period), varying the switching frequency, or varying the number of pulses per unit time of the switch in a switched mode power converter.

[0003] Power conversion systems generally include one or more controllers which sense the output of the power supply and control the operation of one or more switches to regulate the output. Communication between controller circuits is usually accomplished by sending signals across an isolation barrier through a magnetic, dielectric, or optical coupling. The isolation barrier provides a separation between circuits that are electrically referenced to different voltage potentials, such as circuits referenced to an input return and circuits referenced to an output return. In other words, a de voltage source placed between any node of the input circuit and any node of the output circuit would conduct no current. When the power supply operates in an environment where there is substantial electrical noise, such as13141-P917WO PI.0681.WO.P001for example in an electric vehicle or near industrial equipment, the noise may corrupt the communication signals between the control circuits to the extent that the power supply no longer operates as intended. Communication signals between control circuits in applications that do not require an isolation barrier are also susceptible to corruption from noise that may disrupt the operation of the power supply. Accordingly, systems and methods for operating power converters in a noisy environment are still needed.SUMMARY OF THE DISCLOSURE

[0004] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] In some embodiments of power supplies, a power controller includes two controller circuits: a lower controller and an upper controller, or a first controller and a second controller, depending on different implementations of the power supply. Embodiments of the inventive technology are directed to eliminating noise-corrupted communication signal between the two controllers of the power controller. For example, the signal received by the upper / first controller (URX) may differ from the signal initially transmitted by the lower / second controller (Urx) because of losses that may reduce the amplitude of the signal and the addition of electrical noise (also referred to as “signal noise” or simply as “noise”) to the signal URX. The presence of noise in the communication signal may cause errors in the operation of the controllers. For example, noise may trigger a charging cycle when such charging cycle is not required, or may start a charging cycle when it is not permitted, such as when switch S2 is closed. Improper operation of the switches may affect regulation of the output or may damage components in the power supply.

[0006] In some embodiments, the power controller is configured to reject those communication signals that are corrupted by noise. For example, the Uix signal from the lower / second controller may include a pattern of timed pulses that are passed-through and filtered-by a pattern filter of the upper controller. Therefore, when the Urx signal contains an acceptable amount of noise, timing of the pulses in the pattern is recognized as a valid23141-P917WO PI.0681.WO.P001pattern by the pattern filter of the upper / first controller, and the power controller continues its normal operation by issuing a CHARGE signal. However, when the UTX signal contains an unacceptably high amount of noise, timing of pulses in the pattern are not recognized as a valid pattern by the pattern filter, the power controller stops its operation by issuing an INHIBIT signal for a predetermined blanking time, and waiting is initiated for the next set of the UTX signals. Generally, the pattern of timed UTX pulses may be chosen to reduce the likelihood of accidentally matching the periodicity of common wireless communication frequencies that can be anticipated to come from external sources in order to avoid false positive detection of noise in the system.BRIEF DESCRIPTION OF DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Corresponding reference characters indicate corresponding components throughout the several views of the figures.

[0008] FIG. 1 A is a schematic diagram of a power supply with a controller in accordance with an embodiment of the present technology;

[0009] FIG. IB is a schematic diagram of a power supply with a controller in accordance with an embodiment of the present technology;

[0010] FIG. 2A is a functional block diagram of the upper controller and the lower controller depicted in FIG. 1A;

[0011] FIG. 2B is a functional block diagram of the first controller and the second controller depicted in FIG. IB;

[0012] FIG. 3 is a timing diagram for a transmitted signal UTX, a received signal URX, and a window signal Uw when noise is absent in accordance with an embodiment of the present technology;

[0013] FIGS. 4-8 are timing diagrams of the window signal Uw and the received signal URX for examples where noise is present in accordance with an embodiment of the present technology;33141-P917WO PI.0681.WO.P001

[0014] FIG. 9 is a timing diagram that shows an example of the INHIBIT signal UINH, the CHARGE signal UCH, and the received signal URX for valid and invalid requests to start a charging cycle in accordance with an embodiment of the present technology;

[0015] FIG. 10 is a flow diagram of operation of the upper controller or the first controller in accordance with an embodiment of the present technology; and

[0016] FIG. 11 is a schematic diagram of an example power supply with a power controller that is configured to reject noise in accordance with an embodiment of the present technology.DETAILED DESCRIPTION

[0017] In some embodiments of power supplies, a power controller includes two controller circuits. Communication between the two controller circuits is typically accomplished by sending signals across an isolation barrier through a magnetic, dielectric, or optical coupling. When the power supply operates in an environment where there is substantial electrical noise, such as for example in an electric vehicle or near industrial equipment, the noise may corrupt the communication signals between the control circuits to the extent that the power supply no longer operates as intended.

[0018] In some embodiments, the UTX signal from the lower / second controller includes a pattern of timed pulses that are filtered by a pattern filter in the upper / first controller. The timing of pulses in the pattern can be chosen to reduce the likelihood of matching the periodicity of common wireless communication frequencies as anticipated to come from external sources.

[0019] In operation, the pattern filter compares the received signal URX with timing windows that match a known pattern of valid UTX signals. If the pattern filter determines that the received signal is valid, a CHARGE signal may be asserted for the driver circuit to initiate a charging cycle. A charging cycle in a power supply may refer to any operation that allows energy to be stored in an electrical component, such as an inductor or a capacitor. In some embodiments, such as for example in other power converter topologies, a valid received signal may assert a different command that is not necessarily a CHARGE command, but rather a defined operation of the power supply. For example, to control the operation of a half-bridge power converter the asserted signal may be a COMMUTATE command. In general, such CHARGE, COMMUTATE, and similar commands may be43141-P917WO PI.0681.WO.P001referred to as a first command that initiates a charging cycle of the power supply. If the pattern filter rejects the received signal as invalid (i.e., the received pattern does not correspond to the expected pattern), an INHIBIT signal may block the processing of received signals for a predetermined blanking time. The blanking time is typically significantly longer (e.g., twice as long, several times as long, or an order of magnitude longer) than the duration of a valid UTX signal and the blanking time can be selected to be long enough for anticipated noise events to end, but short enough for an output capacitor to maintain its output voltage within a desired range in the absence of new charging cycles. In general, such INHIBIT or a similar command may be referred to as a second command that acts to delay initiation of the charging cycle of the power supply for a duration of the blanking period.

[0020] FIG. 1A is a schematic diagram of a power supply 10 with a controller 100 in accordance with an embodiment of the present technology. FIG.1 shows elements of an example power supply 10 that is configured to reject noise in the signal sent from a lower controller 114 to an upper controller 112. The circuit topology of the illustrated power supply is referred to in the art as a two-switch buck converter, and is also described as a synchronous buck converter. Illustrated upper switching circuit 120 and lower switching circuit 140 are coupled to an input de voltage source VIN. In some embodiments, a switch SI in the upper switching circuit 120 is coupled to the positive terminal of the input voltage source and a switch S2 in the lower switching circuit 140 is coupled to the negative terminal of the input voltage source.

[0021] The switch SI in the upper switching circuit and the switch S2 in the lower switching circuit may be controlled respectively by circuits in an upper controller 112 and by circuits in a lower controller 114 in order to regulate an output voltage Vo at a load 150. In the illustrated embodiment of FIG. 1, the controlled output is a voltage Vo, however, a person of ordinary skill would understand that in other embodiments the controlled output may be a current to the load 150, or a combination of a voltage and a current at the load.

[0022] In operation, switches SI and S2 close and open at appropriate times to allow an output inductor Lo to conduct current from the input voltage source VIN. A switch that is closed (ON position) may conduct current, whereas a switch that is open (OFF position) does not conduct current. The currents Isi and Is2 in the respective switches SI and S2 are53141-P917WO PI.0681.WO.P001pulsating as illustrated by the switch drive waveforms UD and LD in the drawing. The upper graph of the current Isi through the switch SI shows that it reaches a maximum value ILI IT, and the lower graph of both current Isi through the switch SI (dash line) and current Is2 through the switch S2 (solid line) with the maximum value ILIMIT for both currents.

[0023] Current Io into the inductor Lo is a sum of the currents Isi and Is2. In operation, current from output inductor Lo charges an output capacitor Co that can be selected to be sufficiently large to filter the pulsating current, so that the voltage Vo is kept at substantially a constant regulated value over the period Ts that defines a charging cycle.

[0024] The upper controller 112 receives signal IS representative of the current Isi through switch SI at a CURRENT SENSE terminal. At the beginning of a charging cycle, the switch S2 is open, and the upper controller 112 asserts an UPPER DRIVE signal that closes switch SI. When switch SI is closed, current Isi increases until the upper controller senses that Isi reached a value ILIMIT that may be pre-determined and set by circuits of the upper controller 112 according to a control algorithm. A person of ordinary skill would know how to set a pre-determined threshold value to operate as a current limiter on a controller. When the current Isi reaches the ILIMIT value, the upper controller 112 de-asserts the UPPER DRIVE signal to open the switch SI (i.e., to set the switch SI to OFF position).

[0025] Next, when the switch SI is opened in response to the UPPER DRIVE signal, the lower controller 114 asserts a LOWER DRIVE signal to close switch S2 (i.e., to set switch S2 to ON position), allowing S2 to conduct current Is2. A diode D2 coupled across switch S2 provides a path for current Is2 before switch S2 closes. Therefore, in a practical circuit, closing of the switch S2 reduces the voltage in the path of Is2 to increase efficiency of the power supply. The lower controller 114 monitors the voltage VS across switch S2 at a VOLTAGE SENSE terminal to detect when current Is2 decreases to zero so that switch S2 may be opened (i.e., set to OFF) in preparation for the next charging cycle. A person of ordinary skill would know how to set a pre-determined threshold value to operate as a voltage limiter on a controller.

[0026] In the example of FIG. 1A, the lower controller! 14 also receives the output voltage Vo at its OUTPUT SENSE terminal as signal OS. In operation, the lower controller 114 transmits a communication signal UTX that is received by the upper controller 112 as a received signal URX. The purpose of the transmitted signal UTX from the lower controller63141-P917WO PI.0681.WO.P001114 is to set the upper controller 112 to begin a next charging cycle by closing the switch SI.

[0027] The received signal URX may differ from the transmitted signal UT.X because of the addition of noise to the communication signal. For example, the presence of noise in the communication signal may cause the upper controller 112 to begin a charging cycle when a charging cycle is not required, or to begin a charging cycle when it is not permitted, such as when switch S2 is closed. Improper operation of the switches may cause loss of regulation of the output or may damage components in the power supply. Therefore, it is desirable to configure a controller that rejects communication signals that are corrupted by noise.

[0028] In one example, the switches SI and S2 may be transistors such as a metal-oxide- semiconductor field-effect transistor (MOSFET), bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a gallium nitride (GaN) based transistor or a silicon carbide (SiC) based transistor. The upper controller 112 and lower controller 114 may be included in an integrated circuit that is manufactured as either a hybrid or monolithic integrated circuit. In one example, upper controller 112 is included in a first integrated circuit die and the lower controller 114 is included in a second integrated circuit die that are both disposed in the same integrated circuit package. The switches SI and S2 may be included in a monolithic or hybrid structure in an integrated circuit package that also includes the upper controller 112 and the lower controller 114. In one example, switch SI is disposed on a first integrated circuit die that also includes the upper controller 112 and the lower controller 114 is included in a second integrated circuit die. Further, it should be appreciated that both the upper controller 112, the lower controller 114 and switches SI and S2 need not be included in a single package and may be implemented in separate packages or a combination of combined / separate packages.

[0029] FIG. IB is a schematic diagram of a power supply 20 with a controller 200 in accordance with an embodiment of the present technology. In the illustrated example, the power supply 20 is shown as having a flyback topology. For a flyback power converter, the power switch SI is turned ON and OFF to control the amount of energy transferred to the output of the power supply 20. When the power switch SI is turned ON, current conducts through the input winding 204 and energy is stored by the energy transfer element Tl.73141-P917WO PI.0681.WO.P001When the power switch SI is turned OFF, current conducts through the output winding 204 and energy is stored in the output capacitor Co.

[0030] Further, the input of power converter 200 is galvanically isolated from the output of the power converter 200, such that input return 206 is galvanically isolated from output return 216. Since the input and output of power converter 200 are galvanically isolated, there is no direct current (de) path across the isolation barrier of energy transfer element Tl, or between input winding 202 and output winding 204. It is appreciated that other known topologies and configurations of power converters may also benefit from the teachings of the present disclosure, including configurations that to not require galvanic isolation.

[0031] The power supply 20 provides output power to a load LOAD 150 from an unregulated input voltage YIN. In one example, the input voltage VIN is a rectified and filtered ac line voltage. In another example, the input voltage VIN is a de input voltage. The input voltage VIN is coupled to the energy transfer element Tl. In the example of Fig. IB, the energy transfer element Tl is a coupled inductor. The energy transfer element Tl is shown as including two windings: input winding 202 (also referred to as a primary winding), and output winding 204 (also referred to as a secondary winding). However, in different embodiments, the energy transfer element Tl may have three windings or more than three windings. The input winding 202 of the energy transfer element is further coupled to the power switch SI, and the power switch SI is further coupled to input return 206. Coupled across the input winding 202 is the clamp circuit 208. The clamp circuit 208 limits the maximum voltage on the power switch S 1.

[0032] FIG. IB illustrates a first switching circuit 220 and second switching circuit 240. The power supply 20 includes a clamp circuit 208, energy transfer element Tl, an input winding 202 of the energy transfer element Tl, an output winding 204 of the energy transfer element Tl, a power switch SI, an input return 206, an output switch S2 (also referred to as an output switch / rectifier combination DO), an output capacitor Co, an output return 216, and an output sense circuit 210. The controller 200 includes a first controller 212 and a second controller 214. The first controller 212 may also be referred to as a primary controller while the second controller 214 may also be referred to as a secondary controller. A communication link UTX / URX between the second controller 214 and the first controller 212 is also illustrated in FIG. IB. In the context of this application, the first controller 21283141-P917WO PI.0681.WO.P001and the second controller 214 may be collectively referred to as a power controller 200. Further shown in FIG. IB are an input voltage VIN, a switch current Isw, an output voltage Vo, an output current Io, an output quantity Uo, a feedback signal FB, a primary drive signal DR, a current sense signal ISNS, and a voltage sense signal VSNS.

[0033] In one example, the power switch SI may be a transistor such as a metal-oxide- semiconductor field-effect transistor (MOSFET), bipolar junction transistor (BIT), an insulated-gate bipolar transistor (IGBT), a gallium nitride (GaN) based transistor or a silicon carbide (SiC) based transistor. In another example the power switch may be a cascode switch including a normally-on first switch and a normally-off second switch coupled together in a cascode configuration. The first switch may generally be a GaN or SiC based transistor while the second switch may be a MOSFET, BJT, or IGBT.

[0034] Output winding 204 is coupled to the second switch S2 (also referred to as the output switch / rectifier DO). The second switch S2 is exemplified as a transistor with an integral diode used as a synchronous rectifier. However, the second switch may also be exemplified as a discrete diode and a discrete transistor. Output capacitor Co is shown as being coupled to the second switch S2 and the output return 216. The power supply 20 further includes circuitry to regulate the output quantity Uo, which in one example may be the output voltage Vo, output current Io, or a combination of the two. The output sense circuit 210 is configured to sense the output quantity Uo. The output sense circuit 210 provides the feedback signal FB, representative of the output of the power supply, to the second controller 214.

[0035] The second controller 214 is configured to output signal SR to control the turn ON and the turn OFF of the second switch S2. Furthermore, the second controller 214 is configured to send a transmitted signal UTX to the first controller 212. However, analogously to the noise contamination shown in FIG. 1 A above, the received signal URX (i.e., the signal received by the first controller 212) may differ from the transmitted signal UTX because of the addition of noise 125 to the communication signal. For example, the presence of noise in the communication signal may cause the first controller 212 to begin a charging cycle when a charging cycle is not required, or to begin a charging cycle when it is not permitted. Improper operation of the switches may cause loss of regulation of the output3141-P917WO PI.0681.WO.P001or may damage components in the power supply. Therefore, it is desirable to configure a controller that rejects communication signals that are corrupted by noise.

[0036] First controller 212 and second controller 214 may be included in an integrated circuit that is manufactured as either a hybrid or monolithic integrated circuit. In one example, the first controller 212 is included in a first integrated circuit die and the second controller 214 is included in a second integrated circuit die that are both disposed in the same integrated circuit package. The power switch SI may be included in a monolithic or hybrid structure in an integrated circuit package that also includes the first controller 212 and the second controller 214. In one example, power switch SI is disposed on a first integrated circuit die that also includes the first controller 212 and the second controller 214 is included in a second integrated circuit die. In another example, power switch SI is disposed on a first integrated circuit die, the first controller 212 is included in a second integrated circuit die, and the second controller 214 is included in a third integrated circuit die. Further, it should be appreciated that both the first controller 212, the second controller 214 and power switch SI need not be included in a single package and may be implemented in separate packages or a combination of combined / separate packages. The power switch SI may be a cascode switch including the first switch and the second switch. The first switch and may be disposed in the same integrated circuit die as the second switch. Alternatively, the first switch and the second switch may be disposed on separate integrated circuit dies. The first switch and the second switch may be included in a single package or may be implemented in separate packages.

[0037] The first controller 212 is configured to control the turn ON and turn OFF of the power switch SI. The first controller 212 is coupled to receive a current sense signal ISNS representative of the switch current Isw conducted by power switch SI. In one example, the current sense signal ISNS is representative of the switch current Isw of the power switch SI . The current sense signal ISNS may be a voltage signal or a current signal. The first controller 212 is configured to receive a voltage sense signal VSNS representative of the input voltage VIN of the power supply. The input voltage sense signal VSNS may be a voltage signal or a current signal.

[0038] The first controller 212 outputs the first drive signal DR to the power switch S 1 to control various switching parameters of the power switch SI to control the transfer of103141-P917WO PI.0681.WO.P001energy from the input to the output of the power converter 200 through the energy transfer element Tl. Examples of such parameters include switching frequency fsw (or alternatively switching period Tsw), duty cycle, on-time and off-times, or varying the number of pulses per unit time of the power switch S 1.

[0039] FIGs. 2A and 2B are functional block diagrams of the upper controller 112 and the lower controller 114 depicted in FIG. 1A, and the first controller and the second controller depicted in FIG. IB, respectively. Furthermore, the embodiments of FIGS. 3-10 are presented in the context of both lower and upper controller architecture (FIGs. 1 A and 2A) and first and second controller architecture (FIGS. IB and 2B).

[0040] Referring to FIG. 2A, each controller 112, 114 may include separate clock circuits 308, 408 that provide references for synchronization and timing of events. Each controller includes a driver circuit 302, 402 that open and close switches SI and S2, respectively, in response to internal and / or external signals.

[0041] In some embodiments, the lower controller 114 may include comparators and logic circuits 404 that receive an OUTPUT SENSE signal OS and a timing signal from the clock circuit 408 to determine when the driver circuit 402 will assert and de-assert the lower drive signal LD to close and open switch S2. A transmitter circuit 410 may interpret a signal from the comparators and logic circuits 404 such as to initiate communication with the upper controller 112, thus initiating a charging cycle. The transmitter circuit 410 may generate an UTX signal for communication with the upper controller 112. However, in some situations the transmitted UTX signal may be corrupted by noise before it appears as signal URX at the input to a receiver circuit in the upper controller. The noise contamination is represented symbolically by an adder 130 that receives UTX signal and noise 125 as inputs, and outputs URX signal as a combination of UTX signal and noise (e.g., a sum of UTX and noise).

[0042] In some embodiments, the UTX signal from the lower controller 1 14 may be a pattern of timed pulses that are subsequently filtered by a pattern filter 304 of the upper controller 112. The pattern of timed pulses UTX may be configured to be different from periodic characteristics of anticipated sources of noise, thus reducing possibilities of the noise being interpreting as a valid signal. For example, the timing of pulses in the pattern may be chosen to reduce the likelihood of matching the periodicity of common wireless communication frequencies that can be anticipated to come from external sources.113141-P917WO PI.0681.WO.P001

[0043] In operation, the pattern filter 304 compares the received signal URX with timing windows that match the known pattern of a valid UTX signal. If the pattern filter determines that the received signal is valid, a CHARGE signal may be asserted to the driver circuit 302 to initiate a next charging cycle through switch SI . On the other hand, if the pattern filter 304 rejects the received URX signal as invalid, the pattern filter 304 may issue an INHIBIT signal to block the processing of received UR signals for a predetermined blanking time (the time during which the operation of receiver 310 will be blocked). The blanking time is typically longer than the duration of a valid UTX signal and is chosen to be long enough for anticipated noise events to end, but short enough for the output capacitor Co to maintain the output within a desired range in the absence of the charging cycles.

[0044] FIG. 2B is a functional block diagram of the first controller 212 and the second controller 214 depicted in FIG. IB. For brevity and conciseness purposes, operation of the first controller 212 and the second controller 214 is not discussed in detail, because the operation of these components generally corresponds to that of the upper controller 112 and lower controller 114, respectively. That is, while the operation of the first controller 212 and the second controller 214 relies on different inputs (e.g., output sense FB, current sense ISNS, voltage sense VSNS) and provides different outputs (e.g., primary drive DR, secondary drive SR), communication between the first controller 212 and the second controller 214 still remains susceptible to the noise 125 in a comparable sense to the one described with respect to that of the lower / upper controllers 112 / 114. Namely, the received signal URX (i.e., the signal received by the first controller 212) may differ from the transmitted signal UTX because of the addition of noise 125 to communication signal. Therefore, pattern filter 304 compares the received signal UR with timing windows that match the known pattern of a valid UTX signal. If the pattern filter determines that the received signal is valid, a CHARGE signal may be asserted to the driver circuit 302 to initiate a next charging cycle through switch SI. On the other hand, if the pattern filter 304 rejects the received URX signal as invalid, the pattern filter 304 may issue an INHIBIT signal to block the processing of received URX signals for a predetermined blanking time, during which the operation of receiver 310 will be blocked. Several examples of processing UTX / URX signals are described below with respect to FIGS. 3-9.3141-P917WO PI.0681.WO.P001

[0045] FIG. 3 is a timing diagram for a transmitted signal UTX, a received signal URX, and a window signal Uw when noise is absent in accordance with an embodiment of the present technology. The time axes of the window signal Uw and the received signal URX in the example diagram of FIG. 3 are shown as synchronous, because they are derived from the same clock 308 in the upper / first controller circuit 112 / 212. However, the time axis of the transmitted signal UTX is generally not synchronous with the other two horizontal axes, because the timing of UTX signal is derived from a separate clock 408 of the lower / second controller circuit 114 / 214 that may not necessarily be synchronized with the clock 308 in the upper controller circuit.

[0046] FIG. 3 shows the transmitted signal UT as a pattern of n+1 pulses having leading edges occurring at times tro, tn, through tin. Time tn follows time tro by an interval Txi, time tT2 follows time tn by an interval Tx2, and time tn follows time te by an interval Txn. In practical applications, n is greater than or equal to 2 (n > 2). In one example where n = 2, Txi may be 200 ns and Tx2 may be 500 ns. These interval values effectively block periodic noise at frequencies of 5 MHz (where Txi is 200 ns) and 2 MHz (where Txi is 500 ns), respectively. In some embodiments, 2 MHz and 5 MHz may be expected values of the electrical noise in the environment. The widths of the pulses are typically much smaller than the intervals between the pulses. In some embodiments, the width of pulses in the transmitted signal may be about 5 ns.

[0047] The received signal URX is shown as a pattern of n+1 pulses with leading edges occurring at times tRO, tRi, through tRn, and trailing edges occurring at times tro, tFi, through tFn. In some embodiments, the leading edges of the UTX pulses correspond to the leading edges of the UR pulses. The widths of the pulses in the received signal URX may not be the same as the widths of the respective pulses in the transmitted signal UTX owing to dispersion and distortion from natural limitations in bandwidth along the path from transmitter to receiver.

[0048] In some embodiments, the receiver 310 in the upper / first controller 112 / 212 responds to the received signal URX only when the magnitude of a received signal is equal to or greater than a threshold value UTH. The example of FIG. 3 shows all the received pulses being greater than the threshold value UTH.3141-P917WO PI.0681.WO.P001

[0049] The window signal Uw in FIG. 3 shows pulses of widths Twi, Tw2, through Twn whose leading edges are delayed by the respective times TDI, TD2, through Ton from the respective leading edges of the pulses of the received signal URX at times tRo, tRi, and tR2. In general, the leading edge of a pulse in the window signal Uw can be delayed by a time offset Ton from the leading edge of a received pulse at time tR(n-i). In some embodiments, time offsets TDI, TD2, through Ton are computed from the expected natural variances in the timing parameters of the transmitted signal UTH based on a goal to have time windows Uw be open (e.g., values of Uw being above a certain voltage value) when a pulse from a valid signal is expected to arrive. Therefore, time offsets TDI, TD2, through Ton are generally not of uniform duration.

[0050] In another example (not illustrated in FIG. 3), the delay times for the pulses of the window signal Uw may be measured with respect to the falling edges of the pulses of the received signal URX at times tro, tn, and tF2. In other words, the leading edge of a pulse in the window signal Uw may be delayed by a time Ton from the falling edge of a received pulse at time tF(n-i).

[0051] After the receiver 310 recognizes a first pulse in the received signal URX, the pattern filter 304 may generate a string of window pulses in the window signal Uw for comparison with subsequent pulses in the received signal UR . The pulses in the window signal Uw are timed to coincide with expected pulses from a valid transmitted signal Urx.

[0052] If the pattern filter 304 determines that the received signal UR is a valid request from the lower / second controller 114 / 214 to start a charging cycle, a CHARGE signal is asserted for the driver 302 to close the switch SI. On the other hand, if the pattern filter 304 does not recognize a valid request in the received signal UR , the CHARGE signal is not asserted, and the pattern filter 304 may instead assert an INHIBIT signal to prevent any further processing of received signals for a blanking duration. In one example where n = 2, Txi = 200 ns and Tx2 = 500 ns, the blanking duration is set to 4 ps, because such duration of the blanking time is sufficient for the noise interference to subside, while still maintaining the output voltage Vo within regulation limits. In general, a selection of blanking time includes an engineering trade-off based on effectiveness of noise rejection on one hand and product requirements to keep the output voltage Vo within regulation limits on the other hand.143141-P917WO PI.0681.WO.P001

[0053] FIG. 4 is a timing diagram of the window signal Uw and the received signal URX for an example where electrical noise is present in accordance with an embodiment of the present technology. In the illustrated case, a noise event occurs at the time tNoisr immediately before the transmitter 410 sends a string of pulses UTX to request the start of a charging cycle. Since the magnitude of the noise event exceeds the threshold value UTH, the receiver 310 misinterprets the noise event as a first signal URX in a sequence of transmitted pulses, and the receiver responds by starting the pattern of pulses in window signal Uw after a delay time TDI from the time INOISE. Stated differently, the receiver 310 “concluded” that a first UTH pulse of a valid pattern of UTH pulses was received. However, since the pattern of pulses in window signal Uw did not start from the leading edge of the first pulse UTX from the transmitter at time tRo, none of the subsequent pulses that were received from the receiver 310 fall within the pulses of window signal Uw. As a result, the pattern filter 304 does not recognize a valid UR pattern to start a charging cycle. Therefore, no CHARGE command is issued by the pattern filter 304. Instead, the pattern filter issues an INHIBIT command. As explained above, in some embodiments, even a single misalignment between a window signal Uw and one of the pulses UTX results in issuance of the INHIBIT command, because in many situations it is preferred to reject a received signal that is corrupted by noise, rather than risking starting a charging cycle by a CHARGE command if there is some doubt about the UTX pulses being sufficiently noise-free.

[0054] FIG. 5 is a timing diagram of the window signal Uw and the received signal URX for an example where noise is present in accordance with an embodiment of the present technology. The illustrated noise event at time NOISE again exceeds the threshold value UTH. Therefore, the receiver 310 starts generating pulses of the window signal Uw before the first pulse UTX is received from the transmitter 410. However, the first real first pulse UR that is received from the transmitter 410 occurs within the first window signal Uw. The subsequent pulses UR received from the transmitter 410, however, do not completely fall within the pulses of window signal Uw, and therefore, the pattern filter 304 does not recognize a valid request to start a charging cycle. As explained above, the interrogation of pulses within the window signal Uw may be stopped at the first occurrence of a received pulse URX that does not occur within the time of a corresponding window pulse, since a single mismatch may be sufficient to determine that a request to start a charging cycle is not valid.153141-P917WO PI.0681.WO.P001

[0055] FIG. 6 is another timing diagram of the window signal Uw and the received signal URX for an example where noise is present in accordance with an embodiment of the present technology. In the illustrated example, the noise event at time tNoisr occurs between times tri of the second pulse and tR2 of the third pulse of a series of URX pulses received from the transmitter 410. Although the second received pulse that occurs between times tRi and tn falls within the interval Twi of the pattern filter, and the third received pulse between times tR2 and tF2 falls within the interval Tw2 of the pattern filter, the recognized noise event occurs outside a window of the pattern filter and begins the delay time Ton with respect to a window Twn prematurely, so that the window Twn it does not occur during the time of a transmitted pulse between time tRn and tFn. Therefore, the upper / first controller 112 / 212 does not recognize a valid request to start a charging cycle.

[0056] As explained above, in some embodiments of the inventive technology, the pattern filter 304 of the upper / first controller 112 / 212 is set to reject the series of pulses URX even if only one of the pulses URX falls outside of a corresponding window Tw. Thus, the occurrence of a received pulse URX outside a window pulse Tw of the pattern filter at time tNoisE may be sufficient to determine that a request to start a charging cycle is not valid, and the generation of subsequent pulses in window signal Uw may be stopped. Such scenario causes the pattern filter 304 to assert INHIBIT command to the receiver 310.

[0057] FIG. 7 is another timing diagram of the window signal Uw and the received signal URX for an example where noise is present in accordance with an embodiment of the present technology. The illustrated timing diagram shows a received URX pulse between times tR2 and tF2. However, the received URX pulse has magnitude (amplitude) below the threshold value UTH. Such low magnitude (amplitude) of the received URX pulse may be a result of noise corrupting a pulse transmitted at the correct time in the pattern, such that uncorrupted pulse URX would be within the interval Tw2 of the window signal Uw. However, since the received corrupted URX pulse has insufficient magnitude for the receiver 310 to respond, such pulse is treated as a missing pulse by the pattern filter 304, and the UR pattern is rejected as a valid request to start a charging cycle. Therefore, the upper / first controller 112 / 212 again asserts INHIBIT signal for a predetermined blanking time during which the controller waits for the next set of the Urx signals to be initiated.163141-P917WO PI.0681.WO.P001

[0058] Moreover, even if the generation of pulses in the window signal Uw continues, the failure of the received pulse to start the delay time to the next pulse of the window signal Uw will result in the failure of the subsequent transmitted pulse in the pattern to occur within the interval of the subsequent window, and the controller will not recognize a valid request to start a charging cycle.

[0059] FIG. 8 is another timing diagram of the window signal Uw and the received signal URX for an example where noise is present in accordance with an embodiment of the present technology. The illustrated timing diagram shows periodic noise events occurring at times tNoisEi, tNoisE2, through tNoisEn that are separated by periods TNI. These noise events have amplitudes that are greater than the threshold value UTH; therefore, the receiver 310 generates a pattern of pulses of the window signal Uw. However, if the delay times TDI, TD2, through TDH are distributed such that the window signals Uw do not correspond with the subsequent noise signals, i.e., the delay times TDI, TD2, through Ton are not integer multiples of the period TNI, then the pattern filter 304 does not recognize the periodic noise events as a valid request to start a charging cycle. Therefore, the pattern filter 304 asserts the INHIBIT command.

[0060] FIG. 9 is a timing diagram that shows an example of the INHIBIT signal UINH, the CHARGE signal UCH, and the received signal URX for valid and invalid requests to start a charging cycle in accordance with an embodiment of the present technology. In the illustrated embodiment, valid URX patterns received between times ti and t2, t3 and t4, and t9 and tio produce pulses of the CHARGE signal UCH at the respective times t2, t4, and tio. Stated differently, the abovedisted URX patterns were deemed valid by the pattern filter 304, causing the pattern filter to assert CHARGE command to the driver 202, which starts a pulse UD to the first cascode switch SI that closes the first cascode switch SI. A different scenario takes place with a transmitted pattern beginning at time ts and ending at time te, because this URX pattern is declared invalid at time te. Hence, the pattern filter 304 asserts an INHIBIT signal UINH at time t6 for a duration of blanking time TINH. While the signal UINH is asserted, the pattern filter 304 does not respond to either the valid URX pattern that begins at tine t7 nor to the invalid URX pattern that begins at time ts. After a duration TINH (blanking time) of the INHIBIT signal, the pattern filter 304 is ready to receive a new URX pattern. In the illustrated timing diagram, such new URX pattern begins at time t9 and lasts173141-P917WO PI.0681.WO.P001until time tio. Since this new URX pattern is found valid by the pattern filter 304, the pattern filter asserts a new UCH signal (CHARGE) to start new charging cycle. As explained above, determination about validity of the URX pattern may stop at the first instance of a missed window or at a completion of the entire pattern. In some embodiments, the duration TINH (blanking time) of the INHIBIT signal may be an order of magnitude or more longer than a duration of an individual UR signal or a duration of an entire valid UR pattern.

[0061] FIG. 10 is a flow diagram 1000 of operation of the upper controller or the first controller in accordance with an embodiment of the present technology. A person of ordinary skill would understand that in different embodiments the illustrated method may be executed with additional steps or may omit some steps illustrated in FIG. 10. For example, in some practical scenarios blocks 1004 and 1006 will be skipped during the normal operation of the upper controller, and the illustrated methos will operate within the loop described by the blocks 1008 - 1018.

[0062] The method starts in block 1002. In block 1004, the receiver 310 is set to idle mode, during which the pattern filter 304 is not able to process the incoming URX patterns. In block 1006, the timer 306 initializes the pattern filter 304 to start receiving URX patterns from the receiver 310. In block 1008, a determination is made whether the receiver 310 has detected any URX pulses. As explained above, URX pulses are detected only if their amplitudes exceed the threshold value UTH. AS also explained above, a pattern of URX pulses sets the time offsets TDI, TD2, through Ton that are used to set the starting times of the pulses of the window signal Uw. If the receiver 310 did not detect URX pulses, the method keeps checking for the URX pulses. If the receiver 310 detected URX pulses, the method proceeds to block 1010, where the timer 306 generates time offsets TDI, TD2, through Ton that place pulses (windows) Uw at proper time delays with respect to the corresponding URX pulses.

[0063] In block 1012, the pattern filter 304 processes the received URX signals to verify that the URX pattern properly aligns with the pulses of the window signal Uw. In some embodiments, the UR pattern is deemed properly aligned with the pulses of the window signal Uw if each pulse of the URX pattern is properly aligned within the duration of the corresponding window signal Uw.3141-P917WO PI.0681.WO.P001

[0064] In block 1014, a determination is made whether the URX pattern is valid based on the filtering performed in block 1012. If the URX pattern is found valid, the method proceeds to block 1018, where the CHARGE signal is asserted by the pattern filter 304, and a new charging cycle is started by, for example, the driver 302 asserting a UD signal to the switch51, thus initiating closing the switch SI. Next, the method goes back to block 1008, where a verification is made as to whether new UR pulses are detected.

[0065] If, however, the UR pattern is found invalid in block 1014, the method proceeds to block 1016, where the pattern filter 304 asserts the INHIBIT signal to the receiver 310, and the process stops for a duration of the blanking time TINH. Next, the method returns to block 1008, where a verification is made as to whether new URX pulses are detected.

[0066] FIG. 11 is a schematic diagram of an example power supply 10 with the controller 100 that is configured to reject noise in accordance with an embodiment of the present technology. FIG. 11 generally corresponds to the power supply illustrated in FIG. 1 A, while further illustrating an embodiment of implementing the switches SI, S2, and diode D2 of FIG. 1 A with transistors and diode. A person of ordinary skill would understand that an analogous schematic diagram applies to the power supply illustrated in FIG. IB, such analogous schematic diagram not being repeated here for brevity and conciseness.

[0067] The switch SI is illustrated as a cascode connection of transistors QUHV and QULV, where QUHV may be a normally ON gallium nitride (GaN) high electron mobility transistor (HEMT) and QULV may be a normally OFF silicon (Si) metal oxide semiconductor field effect transistor (MOSFET). In some embodiment, transistors QUHV and QLHV may be relatively high voltage devices with a breakdown voltage of several hundred volts, whereas transistors QULV and QLLV may be a relatively low voltage devices with a breakdown voltage less than 100 volts. The structures of the transistors QULV and QLLV allow these transistors to conduct current Is2 in the positive direction when switch S2 is open (preventing the conduction of current Is2 in the negative direction), effectively absorbing diode D2 into the operation of the transistors. In operation, the upper controller 112 and the lower controller 114 determine voltage and current in the switches SI and S2 by sensing, for example, the current IS at the switch SI and the voltage VS at the switch S2. In other embodiments, the upper controller 112 and the lower controller 114 may sense voltage at the switches SI and52, or may sense current at the switches SI and S2. It is appreciated that the present193141-P917WO PI.0681.WO.P001invention may be applied where communication signals do not necessarily operate switches, such as for example where only an acknowledgement of the occurrence of an event is required as information.

[0068] Numerous specific details are set forth above in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention. For example, skilled artisans will appreciate that elements in the previously described figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well- understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in the figures in order to facilitate a less obstructed view of these various embodiments of the present invention.

[0069] Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality.

[0070] The description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be a limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is203141-P917WO PI.0681.WO.P001appreciated that any specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.

[0071] Although the present invention is defined in the claims, it should be understood that the present invention can alternatively be defined in accordance with the following examples:

[0072] Example 1. A power controller for a power supply, comprising: a first switching circuit comprising a first controller; and a second switching circuit comprising a second controller, wherein the second controller is configured to generate a pattern of transmitted signals Uix, wherein the first controller is configured to receive a pattern of received signals UR comprising the pattern of transmitted signals UTX combined with noise; wherein the first controller comprises a pattern filter configured for: comparing the pattern of received signals URX with an expected pattern of received signals URX, and when the pattern of received signals UR corresponds to the expected pattern of received signals UR , asserting a first command to initiate a charging cycle of the power supply.

[0073] Example 2. The power controller of example 1, wherein the pattern filter is further configured for asserting a second command to delay initiation of the charging cycle of the power supply for a duration of a blanking period when the pattern of received signals URX does not correspond to the expected pattern of received signals URX.

[0074] Example 3. The power controller of example 1, wherein the first command is a CHARGE command that is asserted by the pattern filter to a driver of the first controller.

[0075] Example 4. The power controller of example 2, wherein the second command is an INHIBIT command that is asserted by the pattern filter to a receiver of the first controller.

[0076] Example 5. The power controller of example 1, wherein the first controller is configured to open and close a first switch.

[0077] Example 6. The power controller of example 5, wherein the second controller is configured to open and close a second switch.

[0078] Example 7. The power controller of example 6, wherein:213141-P917WO PI.0681.WO.P001

[0079] the first switch is a cascode switch comprising a normally ON gallium nitride (GaN) high electron mobility transistor (HEMT) and a normally OFF silicon (Si) metal oxide semiconductor field effect transistor (MOSFET);

[0080] the second switch is a cascode switch comprising two transistors.

[0081] Example 8. The power controller of example 1, wherein the pattern filter is configured for generating a sequence of window pulses of a window signal Uw, and wherein the first command to initiate the charging cycle of the power supply is asserted when each received pulse of the pattern of received signals URX takes place within a corresponding window pulse of the window signal Uw.

[0082] Example 9. The power controller of example 2, wherein the pattern filter is configured for generating a sequence of window pulses of a window signal Uw, and wherein the second command to inhibit the charging cycle of the power supply is asserted when at least one pulse of the pattern of received signals URX takes place outside of a corresponding window pulse of the window signal Uw.

[0083] Example 10. The power controller of example 9, wherein the second command to inhibit initiation of the charging cycle of the power supply is at least an order of magnitude longer than a duration of a pulse of received signal UR .

[0084] Example 11. The power controller of example 1, wherein a timer is configured for generating a time offset for a window signal Uw in response to a magnitude of a pulse in received signal UR exceeding a threshold voltage value.

[0085] Example 12. The power controller of example 11, wherein the timer is configured for not generating the time offset in response to the magnitude of a pulse of received signal UR being below the threshold voltage value.

[0086] Example 13. The power controller of example 12, wherein time offsets are applied from a rising edge of each pulse of received signal UR .

[0087] Example 14. The power controller of example 11, wherein time offsets are not uniform for each window pulse of a sequence of window pulses of the window signal Uw.

[0088] Example 15. The power controller of example 1, wherein:

[0089] the first controller comprises a first clock configured for generating time offsets based on the pattern of received signals URX; and3141-P917WO PI.0681.WO.P001

[0090] the second controller comprises a second clock configured for initiating transmission of the pattern of transmitted signals UTX,

[0091] wherein the first clock and the second clock are unsynchronized.

[0092] Example 16. The power controller of example 1, wherein:

[0093] the first controller is configured for sensing a current flowing into the first switch; and

[0094] the second controller is configured for sensing voltage at the second switch.

[0095] Example 17. A power supply comprising the power controller of example 1.

[0096] Example 18. A method for controlling a power supply, the method comprising: sensing current at a first switching circuit by a first controller; sensing voltage at a second switching circuit by a second controller, generating a pattern of transmitted signals UTX by the second controller, receiving a pattern of received signals URX comprising the pattern of transmitted signals UTX combined with noise by the first controller; comparing the pattern of received signals UR with an expected pattern of received signals UR by the first controller; and when the pattern of received signals URX corresponds to the expected pattern of received signals URX, asserting a first command to initiate a charging cycle of the power supply by the first controller.

[0097] Example 19. The method of example 18, further comprising, when the pattern of received signals URX does not correspond to the expected pattern of received signals URX, asserting a second command to delay initiation of the charging cycle of the power supply for a duration of a blanking period by the first controller.

[0098] Example 20. The method of example 18, wherein the first command is a CHARGE command that is asserted by the pattern filter to a driver of the first controller.

[0099] Example 21. The method of example 19, wherein the second command is an INHIBIT command that is asserted by the pattern filter to a receiver of the first controller.

[0100] Example 22. The method of example 18, wherein the first controller is configured to open and close a first switch, and wherein the second controller is configured to open and close a second switch.

[0101] Example 23. The method of example 18, wherein:

[0102] the first controller is configured for sensing a current in the first switch; and

[0103] the second controller is configured for sensing voltage at the second switch.233141-P917WO PI.0681.WO.P001

[0104] Example 24. The method of example 18, further comprising:

[0105] generating a sequence of window pulses of a window signal Uwby the pattern filter, and

[0106] asserting the first command to initiate the charging cycle of the power supply when each received pulse of the pattern of received signals URX takes place within a corresponding window pulse of the window signal Uw.

[0107] Example 25. The method of example 19, further comprising:

[0108] generating a sequence of window pulses in a window signal Uw by the pattern filter, and asserting the second command to inhibit the charging cycle of the power supply when at least one received pulse in the pattern of received signals URX takes place outside of a corresponding window pulse of the window signal Uw.

[0109] Example 26. The method of example 25, wherein the second command to inhibit initiation of the charging cycle of the power supply is at least an order of magnitude longer than a duration of a received signal UR .

[0110] Example 27. The method of example 18, wherein: a timer is configured for generating a time offset for a window signal Uw in response to a received pulse of signal URX exceeding a threshold voltage value; and the timer is configured for not generating the time offset in response to the received pulse of signal URX being below the threshold voltage value.

[0111] Example 28. The method of example 27, wherein time offsets are applied from a rising edge of each received signal URX, and wherein the time offsets are not uniform for each window pulse of a sequence of window pulses of the window signal Uw.3141-P917WO PI.0681.WO.P001

Claims

CLAIMSWhat is claimed is:

1. A power controller for a power supply, comprising: a first switching circuit comprising a first controller; and a second switching circuit comprising a second controller, wherein the second controller is configured to generate a pattern of transmitted signals UTX, wherein the first controller is configured to receive a pattern of received signals URX comprising the pattern of transmitted signals UTX combined with noise; wherein the first controller comprises a pattern filter configured for: comparing the pattern of received signals URX with an expected pattern of received signals URX, and when the pattern of received signals URX corresponds to the expected pattern of received signals UR , asserting a first command to initiate a charging cycle of the power supply.

2. The power controller of claim 1, wherein the pattern filter is further configured for asserting a second command to delay initiation of the charging cycle of the power supply for a duration of a blanking period when the pattern of received signals URX does not correspond to the expected pattern of received signals URX.

3. The power controller of claim 1, wherein the first command is a CHARGE command that is asserted by the pattern filter to a driver of the first controller.

4. The power controller of claim 2, wherein the second command is an INHIBIT command that is asserted by the pattern filter to a receiver of the first controller.

5. The power controller of claim 1, wherein the first controller is configured to open and close a first switch.

6. The power controller of claim 5, wherein the second controller is configured to open and close a second switch.

7. The power controller of claim 6, wherein: the first switch is a cascode switch comprising a normally ON gallium nitride (GaN) high electron mobility transistor (HEMT) and a normally OFF silicon (Si) metal oxide semiconductor field effect transistor (MOSFET); the second switch is a cascode switch comprising two transistors.

8. The power controller of claim 1, wherein the pattern filter is configured for generating a sequence of window pulses of a window signal Uw, and wherein the first command to initiate the charging cycle of the power supply is asserted when each received pulse of the pattern of received signals URX takes place within a corresponding window pulse of the window signal Uw.

9. The power controller of claim 2, wherein the pattern filter is configured for generating a sequence of window pulses of a window signal Uw, and wherein the second command to inhibit the charging cycle of the power supply is asserted when at least one pulse of the pattern of received signals URX takes place outside of a corresponding window pulse of the window signal Uw.

10. The power controller of claim 9, wherein the second command to inhibit initiation of the charging cycle of the power supply is at least an order of magnitude longer than a duration of a pulse of received signal URX.

11. The power controller of claim 1, wherein a timer is configured for generating a time offset for a window signal Uw in response to a magnitude of a pulse in received signal UR exceeding a threshold voltage value.

12. The power controller of claim 11, wherein the timer is configured for not generating the time offset in response to the magnitude of a pulse of received signal UR being below the threshold voltage value.2613. The power controller of claim 12, wherein time offsets are applied from arising edge of each pulse of received signal URX.

14. The power controller of claim 11, wherein time offsets are not uniform for each window pulse of a sequence of window pulses of the window signal Uw.

15. The power controller of claim 1, wherein: the first controller comprises a first clock configured for generating time offsets based on the pattern of received signals URX; and the second controller comprises a second clock configured for initiating transmission of the pattern of transmitted signals UTX, wherein the first clock and the second clock are unsynchronized.

16. The power controller of claim 1, wherein: the first controller is configured for sensing a current flowing into the first switch; and the second controller is configured for sensing voltage at the second switch.

17. A power supply comprising the power controller of claim 1.

18. A method for controlling a power supply, the method comprising: sensing current at a first switching circuit by a first controller; sensing voltage at a second switching circuit by a second controller, generating a pattern of transmitted signals UTX by the second controller, receiving a pattern of received signals URX comprising the pattern of transmitted signals UTX combined with noise by the first controller; comparing the pattern of received signals URX with an expected pattern of received signals URX by the first controller; and27when the pattern of received signals UR corresponds to the expected pattern of received signals UR , asserting a first command to initiate a charging cycle of the power supply by the first controller.

19. The method of claim 18, further comprising, when the pattern of received signals URX does not correspond to the expected pattern of received signals URX, asserting a second command to delay initiation of the charging cycle of the power supply for a duration of a blanking period by the first controller.

20. The method of claim 18, wherein the first command is a CHARGE command that is asserted by the pattern filter to a driver of the first controller.

21. The method of claim 19, wherein the second command is an INHIBIT command that is asserted by the pattern filter to a receiver of the first controller.

22. The method of claim 18, wherein the first controller is configured to open and close a first switch, and wherein the second controller is configured to open and close a second switch.

23. The method of claim 18, wherein: the first controller is configured for sensing a current in the first switch; and the second controller is configured for sensing voltage at the second switch.

24. The method of claim 18, further comprising: generating a sequence of window pulses of a window signal Uwby the pattern filter, and asserting the first command to initiate the charging cycle of the power supply when each received pulse of the pattern of received signals URX takes place within a corresponding window pulse of the window signal Uw.

25. The method of claim 19, further comprising: generating a sequence of window pulses in a window signal Uw by the pattern filter, and28asserting the second command to inhibit the charging cycle of the power supply when at least one received pulse in the pattern of received signals URX takes place outside of a corresponding window pulse of the window signal Uw.

26. The method of claim 25, wherein the second command to inhibit initiation of the charging cycle of the power supply is at least an order of magnitude longer than a duration of a received signal URX.

27. The method of claim 18, wherein: a timer is configured for generating a time offset for a window signal Uw in response to a received pulse of signal URX exceeding a threshold voltage value; and the timer is configured for not generating the time offset in response to the received pulse of signal URX being below the threshold voltage value.

28. The method of claim 27, wherein time offsets are applied from a rising edge of each received signal URX, and wherein the time offsets are not uniform for each window pulse of a sequence of window pulses of the window signal Uw.

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