Multi-detection circuit for circuit breakers

Abstract

Circuit (100A, 100B, 100C, 100D, 100E), comprising: a transistor sub-circuit (106) with several detection nodes and a gate node; a point detector (104) with multiple inputs coupled to the multiple detection nodes of the transistor sub-circuit (106), and one output; and a control circuit (102) with a gate control node, which is coupled to the gate node of the transistor sub-circuit (106), and an overcurrent protection node which is coupled to the output of the peak detector (104), wherein the tip detector (104) comprises several diodes (D1-D4), each diode of the several diodes (D1-D4) having an anode coupled to one of the several inputs of the tip detector (104) and a cathode coupled to the output of the tip detector (104).

Description

Field of invention

[0001] The present invention relates generally to a multi-detection circuit and a method for circuit breakers. General state of the art

[0002] Power transistors are used to switch relatively high power and can carry relatively high currents and / or block relatively high voltages. As a result, the power transistor typically generates heat, even during normal operating conditions. Power transistors typically have a maximum operating temperature, which can be reached and even exceeded when operating in an overcurrent or overvoltage condition for a sufficient duration. Detection circuits are sometimes used to detect the overcurrent or overvoltage condition and generate an output signal that can be used to safely shut down the power transistor before it is permanently damaged.

[0003] JP H09-289442A discloses two or more transistors connected in parallel, each having a detection node via an auxiliary emitter and a measuring resistor. The voltage drops across the measuring resistors are fed to comparators, the outputs of which modify the gate voltages of the transistors to achieve load balancing. Brief description

[0004] A circuit as defined in claim 1 or 8 and a method as defined in claim 13 are provided. The dependent claims define further embodiments. The transistors of claim 9 can be the transistors of any one of claims 2 to 4, and the diodes of claim 9 or 10 can be the diodes of any one of claims 1 to 7.

[0005] In one embodiment, a circuit comprises a transistor sub-circuit with multiple sensing nodes and a gate node; a peak detector with multiple inputs coupled to the multiple sensing nodes of the transistor sub-circuit and an output; and a control sub-circuit with a gate control node coupled to the gate node of the transistor sub-circuit and an overcurrent protection node coupled to the output of the peak detector. The transistor sub-circuit may comprise multiple transistors connected in parallel, each transistor of the multiple parallel-connected transistors having a collector coupled to a first current node of the transistor sub-circuit, an emitter coupled to a second current node of the transistor sub-circuit, and a gate coupled to the gate node of the transistor sub-circuit.Each of the multiple parallel-connected transistors can further include an additional emitter coupled to a respective sensing node of the multiple sensing nodes. Each of the multiple parallel-connected transistors can further include a sensing resistor coupled to a respective sensing node of the multiple sensing nodes. The point detector comprises multiple diodes, each of which has an anode coupled to one of the multiple inputs of the point detector and a cathode coupled to the output of the point detector.The peak detector can further include an additional diode coupled between a ground and a reference output of the peak detector, a first resistor coupled between the output of the peak detector and a voltage source, and a second resistor coupled between the reference output of the peak detector and the voltage source. The voltage source can be a negative voltage source. The reference output of the peak detector can be coupled to an overcurrent protection ground node of the control circuit. The transistor sub-circuit can include multiple transistors, and the peak detector can include multiple diodes, with the multiple transistors and the multiple diodes being integrated together in a single module. The peak detector can include multiple diodes integrated together in a single module.

[0006] In one embodiment, a circuit comprises multiple diodes, each diode having an anode coupled to a corresponding sensing node and a cathode coupled to an overcurrent protection node; multiple resistors, each resistor coupled between the corresponding sensing nodes and ground; a first additional resistor coupled between the overcurrent protection nodes and a negative voltage source; a first additional diode coupled between ground and an overcurrent protection ground node; and a second additional resistor coupled between the overcurrent protection ground nodes and the negative voltage source. The multiple diodes can be coupled to corresponding multiple transistors and integrated together in a module.The circuit may further include a control circuit coupled to the overcurrent protection node and the overcurrent protection ground node. The negative voltage source may include a charging pump.

[0007] In one embodiment, a method for protecting multiple transistors comprises sensing an emitter voltage of each of the multiple transistors; detecting a peak emitter voltage; and using the detected peak emitter voltage to turn off at least one of the multiple transistors. The sensing may include detecting a detection emitter voltage of each of the multiple transistors. The detection includes energizing one of several diodes, each diode of the multiple diodes being associated with a respective transistor of the multiple transistors. The detection may further include coupling several resistors to the respective multiple diodes. The use of the detected peak emitter voltage may include coupling the detected peak emitter voltage to a control circuit in communication with the multiple transistors. Brief description of the drawings

[0008] For a more comprehensive understanding of the present invention and its advantages, reference is now made to the following descriptions in conjunction with the accompanying drawings. These show: Fig. 1 a block diagram of an embodiment of a multi-sensing circuit for circuit breakers; Fig. 2-5 Schematic diagrams of embodiments of a multi-sensing circuit for circuit breakers; Fig. 6 a schematic diagram of an embodiment of an evaluation circuit within the multi-sensing circuit for generating an overcurrent signal; Fig. 7 a schematic diagram of an embodiment of a gate driver circuit within the multi-sensing circuit for controlling the gate of several power switches; Fig. 8 a diagram of a diode module suitable for use in the multi-sensing circuit according to one embodiment; Fig.9 a diagram of a combined transistor and diode module suitable for use in the multi-sensing circuit according to one embodiment; Fig. 10 a diagram of a combined resistor and diode module suitable for use in the multi-sensing circuit according to one embodiment; and Fig. 11 a block diagram of an embodiment method for protecting multiple transistors. Detailed description of illustrative embodiments

[0009] A sensing output can be implemented in a power switch (MOS, IGBT) that provides a small portion of the current through the power switch to an extra pin in a module or integrated circuit. An external sensing resistor can be coupled to the extra pin, and the voltage across the external sensing resistor, which is proportional to the total current flowing through the power switch, can be used to evaluate overload conditions. The voltage across the external sensing resistor is typically evaluated via an overcurrent protection pin (usually referred to as an OCP pin) and perhaps an overcurrent protection ground pin (usually referred to as an OCPG pin) in a power switch driver and / or an integrated control circuit or module.

[0010] A problem can arise when multiple circuit breakers are connected in parallel and only one pin (e.g., the OCP pin) or a set of pins (e.g., the OCP and OCPG pins) of the circuit breaker driver circuit is available for evaluation. For example, if four circuit breakers are connected in parallel, each with its own sensing node, only one of the four circuit breakers can be evaluated. The special case of four circuit breakers connected in parallel is given for illustrative purposes only, and any number of parallel-connected circuit breakers could be considered.

[0011] One circuit solution to the above problem, according to one embodiment, detects the highest current flowing in one of the parallel-connected circuit breakers, since the breaker carrying the highest current will pose the greatest challenge during evaluation. Information from the other circuit breakers is not required to provide the overcurrent information that can be used to trip the failed breaker or an entire module of breakers.

[0012] While one or more additional evaluation pins could be implemented in the integrated driver circuit for each additional parallel power switch, a disadvantage of this solution is the higher cost associated with larger package sizes. If enough additional evaluation pins are required, a sufficiently large package might not even be available.

[0013] Another possible solution is to connect all the sensing resistors for each parallel-connected power transistor to a single evaluation pin or a set of pins. This solution results in the sensing current of the other circuit breakers being distributed in the event of a failure of an individual circuit breaker. In this case, the current through the failed circuit breaker will not increase, and the average current flowing through the remaining circuit breakers will be measured. By sensing the average of the resistance values, the individual maximum current in any one of the circuit breakers can no longer be measured. The higher, unmeasured load current can lead to the destruction of the corresponding circuit breaker, as the evaluation will not detect that a maximum load current has been reached.

[0014] A complete block diagram of the 100A multi-sensing circuit according to one embodiment is shown in Fig. 1 shown. The multi-detection circuit 100A includes a control circuit 102, a peak detector 104 and a power module 106 which includes several power switches.

[0015] The control circuit 102 contains a gate control node (gate controller) for controlling a corresponding gate node (gate) in the power module 106. The control circuit 102 also contains a sensing and logic circuit that is coupled to the OCP and OCPG pins. The control circuit 102 also contains a ground (GND) and a power supply (VEE) pin.

[0016] The peak detector 104 comprises several input nodes D1, D2, D3, and D4, and an output node OUT coupled to the OCP node of the control circuit 102. The peak detector 104 also includes a reference output node REF coupled to the OCPG node of the control circuit 102. The REF output node of the peak detector 104 provides a level-shifting diode dropout voltage from ground, which compensates for another peak detector diode circuit arrangement, as will be discussed in more detail below. The peak detector 104 also includes a ground node GND coupled to the corresponding ground node GND of the control circuit 102. The peak detector 104 also includes a voltage source node VEE coupled to the corresponding voltage source node VEE of the control circuit 102.

[0017] The power module 106 comprises several sensing nodes S1, S2, S3, and S4, which are coupled to the input nodes D1, D2, D3, and D4 of the peak detector 104. The power module 106 includes a gate node, which is coupled to the gate control node of the control circuit 102, as previously discussed. The power module 106 comprises several current input nodes C1, C2, C3, and C4, which are coupled to a first current node 108, and several current output nodes E1, E2, E3, and E4, which are coupled to a second current node 110.

[0018] The internal circuit arrangement consisting of control circuit 102, peak detector 104 and power module 106 is described below with regard to the Fig. 2, Fig. 3, Fig. 4 and Fig. 5 discussed in more detail.

[0019] During a Fig.In the multi-sensing circuit design 100B shown in Figure 2, a bipolar supply voltage is available (both positive VCC and negative VEE voltages are available, which is typical for power switches such as IGBTs, since the gate is negatively biased with respect to the emitter in the event of a disconnection to counteract capacitive coupling, i.e. the Miller effect).

[0020] In Fig.In section 2, the circuit embodiment 100B shown solves the pin availability problem discussed above by using a diode array D1, D2, D3, D4, and D5 with associated bias. The anodes of diodes D1, D2, D3, and D4 form the input nodes of the diode array, as described previously. The input nodes of diodes D1, D2, D3, and D4 are each coupled to the sensing nodes S1, S2, S3, and S4 of the power switches T1, T2, T3, and T4, which are described in more detail below. The coupled cathodes of diodes D1, D2, D3, and D4 form the output node of the diode array, which is coupled to the OCP pin of the control circuit 102, as described previously. The coupled cathodes of diodes D1, D2, D3 and D4 are also coupled to resistor R1, which in turn is coupled to the voltage source node VEE, which in the embodiment of Fig.2 is shown as VEE = -10 volts and is supplied by an external negative voltage source. The anode of diode D5 is coupled to ground, and the cathode of diode D5 is coupled to resistor R2, which in turn is coupled to the voltage source node VEE. The cathode of diode D5 also supplies a level-shifting voltage to the OCPG pin of control circuit 102.

[0021] Four circuit breakers T1, T2, T3 and T4 with corresponding current output nodes E1, E2, E3 and E4 and detection nodes S1, S2, S3 and S4 are connected in parallel. In the Fig.In embodiment 100B 2, the current output nodes E1, E2, E3, and E4 are emitter nodes and carry most of the current output. The sensing nodes S1, S2, S3, and S4 are sensing emitter nodes and carry a small linear proportional portion of the total output current. In one example, the current flowing out of a sensing node will carry 1 / 1000, or 0.1%, of the total current of the corresponding circuit breaker. Other emitter current to sensing emitter current ratios can be used. In the embodiment of Fig. Figure 2 shows IGBTs implementing the power switches T1, T2, T3, and T4, but of course other types of components can be used, such as MOS transistors or silicon carbide transistors, as well as other types of power switches known in engineering. The current input nodes (collectors in the embodiment of Fig.2) C1, C2, C3 and C4 of the circuit breakers T1, T2, T3 and T4 are connected together and to node 108. The current output nodes E1, E2, E3 and E4 (emitters in the embodiment of Fig. 2) are connected together and to node 110. The detection nodes S1, S2, S3, and S4 are connected to the anodes of diodes D1, D2, D3, and D4, and also to the first end of corresponding detection resistors Rs1, Rs2, Rs3, and Rs4. The second end of corresponding detection resistors Rs1, Rs2, Rs3, and Rs4 is connected together and to ground.

[0022] The control circuit 102 includes a gate driver circuit 112, which is coupled to the gates of the power switches T1, T2, T3, and T4 via a gate resistor RG. The control circuit 102 also includes a signal evaluation circuit 114, which is coupled to the nodes OCP and OCPG. The signal evaluation circuit 114 is shown in the schematic diagram of Fig.6 is described in more detail, and the gate driver circuit 112 is described with respect to the schematic diagram of Fig. 7 described in more detail.

[0023] In another multi-sensing circuit design, 100C, in Fig. As shown in Figure 3, only a unipolar supply voltage (VCC) is available. Fig. Circuit 100 solves the pin availability problem discussed above by using the same diode array with appropriate biasing, as discussed above, but also includes a charging pump (CHPU) 116. A corresponding implementation is shown in Fig. Figure 3 shows that four circuit breakers T1, T2, T3 and T4 with corresponding detection outputs are connected in parallel, as previously described. Fig. 2 was discussed.

[0024] In the embodiment of Fig.3. The negative voltage (shown as VEE = -2 volts) required to bias the negative level-shifting voltage of the diodes is provided internally and implemented by a charge pump 116. The charge pump 116 typically includes several stages connected in series to gradually build up a negative voltage, without the negative voltage being supplied externally, as is known in the art. The stages connected in series typically include a diode and a capacitor, or a switch and a capacitor. Many types of charge pump circuits are suitable for use in the charge pump 116. Otherwise, the functionality of circuit 100C is as described above with respect to Fig. 2 discussed.

[0025] Fig. Figure 4 is a schematic diagram of an embodiment of a multi-sensing circuit 100D for circuit breakers, wherein resistors R1 and R2 of an embodiment of the multi-sensing circuit 100B, in Fig. Figure 2 shows that the current sources I1 and I2 are replaced. Current sources I1 and I2 can be dimensioned to provide a current similar to that flowing, for example, through resistor R2 in the multi-sensing circuits 100B and 100C described previously.

[0026] Other lower current values ​​can also be used for current sources I1 and I2. In an embodiment with a multi-output current mirror (in Fig. 4 not shown) can be realized.

[0027] Fig. Figure 5 is a schematic diagram of an embodiment of a multi-sensing circuit 100E for circuit breakers, wherein the resistors R1 and R2 of an embodiment of the multi-sensing circuits 100B and 100C, in Fig. 2 and Fig.Figure 3 shows that the loads are completely eliminated. In the multi-sensing circuit 100E, the only load for diodes D1-D5 is provided by the input impedance of the signal evaluation circuit 114. In some embodiments of the multi-sensing circuit 100E, a filter (such as a small-valued capacitor) may be coupled between nodes OCP and OCPG.

[0028] Fig. Figure 6 shows an evaluation circuit 114 with a comparator 120 having a first input coupled to the OCP pin, a second input coupled to a threshold voltage generator 122, and an output 124 for supplying an overcurrent signal 124. The overcurrent signal 124 is generated by the control circuit 102 or by the control circuit 102 in conjunction with other systems or circuits, in Fig.1-5 (not shown) are used to disconnect at least one of the circuit breakers T1-T4, or otherwise change the operating condition, or to provide a warning signal that at least one of the circuit breakers T1-T4 is in an overcurrent mode. If, during operation, the OCP node voltage (normal operation) is below the threshold voltage (VT) referenced to the OCPG node voltage, then no overcurrent signal is generated and the output 124 of comparator 120 is low. If the OCP node voltage (short circuit or overcurrent condition detected) is above the threshold voltage referenced to the OCPG node voltage, then an overcurrent signal is generated and the output 124 of comparator 120 is high.

[0029] In an example provided below with reference to Tables I and II, the OCPG node voltage is specified as -600 mV. For a maximum allowable current, a corresponding peak OCP node voltage is specified as -500 mV. For an overcurrent current, a corresponding peak OCP node voltage is specified as -300 mV. Thus, a corresponding value of the overcurrent threshold voltage for the threshold voltage generator 122 would be 200 mV. With reference to the OCPG node voltage, the negative input of comparator 120 would provide a midpoint voltage of -400 mV, that is, between the peak voltage generated by the maximum allowable current (-500 mV) and the peak voltage generated by the overcurrent (short-circuit) current (-300 mV). Other threshold voltages are, of course, possible to accommodate other maximum allowable currents in a given application.

[0030] Fig.Figure 6 shows an evaluation circuit that is primarily analog in nature. However, the comparison of the OCP node voltage to a threshold voltage can also be accomplished digitally. For example, an ADW could be used to convert the OCP-OCPG differential voltage into a digital value. This digital value is then compared to another digital value (overcurrent threshold) in the digital domain. If the threshold is reached, the gate driver circuit 112 can be switched off (or put into another safe state). The overcurrent threshold can be a fixed value or programmed by a user via an SPI or CAN interface, as desired.

[0031] Fig.Figure 7 shows an example of a gate driver circuit 112. The gate driver circuit provides a large drive current for short time intervals due to the capacitive nature of the gates of the power switches being driven. An example of a basic drive circuit 112 is shown in Fig.Figure 7 shows an NPN driver transistor T5 with a collector coupled to VCC, an emitter coupled to output driver node 128, and a gate coupled to input node 126. The driver circuit 112 also includes a PNP driver transistor T6 with a collector coupled to VEE, an emitter coupled to output driver node 128, and a gate coupled to input node 126. Of course, the gate driver circuit 112 can also include other supporting input and compensation circuitry (not shown), and many other driver circuits can be used to provide the necessary gate drive circuitry.

[0032] In operation, diodes D1, D2, D3, and D4 implement a level shift with respect to resistor R1, which is coupled to VEE. Fig.Voltage 2 is supplied externally via VEE and is shown as -10 volts. The signal at the common connection of diodes D1, D2, D3, D4 and resistor R1 is routed to the OCP pin. The OCP signal is a peak-detected signal that detects the highest value of the respective signals at the sensing nodes S1, S2, S3, and S4, corresponding to the highest current flowing through each power switch T1, T2, T3, or T4. Diode D5, connected to resistor R2, also implements a level shift that compensates for the voltages and temperature coefficient of diodes D1 through D4 (for differential signal evaluation at the OCP and OCPG pins). Ideally, diodes D1 through D5 should be of the same type and located as close together as possible so that they experience the same operating temperature and their voltages vary in the same way.The level shift can also be pre-tensioned using power sources (ideally in . Fig. (as shown in 4) can be implemented instead of resistors. The diodes can also be replaced by any component with a rectifying effect.

[0033] For a more comprehensive understanding of the peak detection provided by embodiments, Tables I and II below are used to show relevant node voltages, diode states, and the state of the overcurrent signal. The OCP pin voltage, in particular, is shown with respect to the other circuit voltages, so that the operating principle of the embodiment described in Tables I and II is explained. Fig. 2 and Fig. The circuits shown in the 3 diagrams can be understood more easily. The operating principle of the circuits shown in the diagram is explained below. Fig. 4 and Fig. The circuits shown in the 5 diagrams are very similar, although some of the operating currents are different.

[0034] In Table I, an S4 value (the highest detection voltage) of 100 mV reflects an operating condition with a high current in circuit breaker T4, but not one that triggers an overcurrent signal. In Table II, an S4 value (the highest detection voltage) of 300 mV reflects an overcurrent condition in circuit breaker T4 with a high current that triggers an overcurrent signal.

[0035] The following typical values ​​are shown in Tables I and II: R1 = 5 kilohms, R2 = 5 kilohms, Rs1 = 0.5 ohms, Rs2 = 0.5 ohms, Rs3 = 0.5 ohms, Rs4 = 0.5 ohms, VEE = -10 volts or -2 volts. All corresponding circuit breaker currents can be easily found by dividing the given voltages by the resistance values ​​above and multiplying the ratio of the emitter size to the sensing emitter size. Table I illustrates the sensing node voltages, the OCP and OCPG pin voltages, and the state of the overcurrent signal output and diodes in normal operating mode. S1 voltage S2 voltage S3 voltage S4 voltage OCP voltage OCPG voltage OVERCURRENT condition 50 mV 60 mV 80 mV 100 mV -500mV -600mV LOW D1-state d D2 state d D3-state D4-state D5-state d OUT OF OUT OF OUT OF ONE ONE TABLE I - Normal Operation

[0036] In Table I, it is important to note that the overcurrent signal is not triggered because none of the detection node voltages exceeds the example threshold voltage of 200 mV. The threshold voltage is determined by the maximum operating current that any one of the circuit breakers T1 to T4 can tolerate without damage. Since the anode of diode D4 is coupled to the highest detection node voltage, this diode is on, and all the other diodes D1-D3 are off. Diode D5 is always on because it is used to generate a level-shifting voltage to compensate for the diode drop of diodes D1, D2, D3, and D4. Diode D5 also compensates for the temperature coefficient of diodes D1-D4.

[0037] As illustrated in Tables I and II, the most positive voltage is always sent through the corresponding diode to the OCP pin, and all other diodes are fully or partially switched off (in the case where a similar but lower voltage is present at one of the sensing nodes). The voltage at the OCP pin is then evaluated to determine whether a normal operating condition or an overcurrent operating condition exists with respect to the overcurrent threshold voltage.

[0038] Table II illustrates the detection node voltages, the OCP and OCPG pin voltages and the overcurrent output state in an overcurrent operating mode, where at least one (T4) of the circuit breakers supplies more than a maximum allowable current, and thus the overcurrent pin OCP voltage is greater than a maximum overcurrent threshold voltage. S1 voltage S2 voltage S3 voltage S4 voltage OCP voltage OCPG voltage OVERCURRENT condition 50 mV 100 mV 150 mV 300 mV -300mV -600mV HIGH D1-state d D2 state d D3-state D4-state D5-state d OUT OF OUT OF OUT OF ONE ONE TABLE II - Overcurrent operation

[0039] In Table II, it is important to note that the overcurrent signal is triggered because the S4 detection node voltage of 300 mV exceeds the example threshold voltage of 200 mV. Since the anode of diode D4 is coupled to the highest detection node voltage, this diode is analogously switched on, and all the other diodes D1-D3 are switched off. Diode D5 is always switched on because it is used to generate a level-shifting reference voltage, as described above.

[0040] Tables I and II also apply to embodiment 100D, in which resistors R1 and R2 are replaced by current sources I1 and I2, and to embodiment 100E, in which resistors R1 and R2 are eliminated. However, the current flowing through diodes D1-D4 will be different.

[0041] The in Fig.The circuits and blocks shown in Figures 1-5 can be implemented in many different ways to optimize performance in a given application. For example, although four transistors T1, T2, T3, and T4 are shown, any number can be used. Similarly, four diodes D1, D2, D3, and D4 are shown, but any number can be used, corresponding to the chosen number of transistors.

[0042] The in Fig. The circuits shown in 1-5 can be implemented as discrete components or integrated together in different modules or integrated circuits.

[0043] In a Fig.In the embodiment shown in Figure 8, diodes D1, D2, D3, D4, and optionally diode D5 can all be integrated together in a module or integrated circuit 800. The module 800 includes pins 802, which are coupled to the anodes of diodes D1-D4, and pins 804, which are coupled to the cathodes of diodes D1-D4. Optionally, the cathodes 802 can be internally coupled to each other and brought out to a single pin.

[0044] In another, in Fig. In the embodiment shown in 9, the transistors T1, T2, T3 and T4, as well as the diodes D1, D2, D3, D4 and D5, can all be interconnected and integrated together into a module or an integrated circuit 900. In the embodiment shown in Fig.In the embodiment shown in Figure 9, all collectors are brought out to pins C1, C2, C3, and C4; all gates are brought out to pins G1, G2, G3, and G4; all cathodes are brought out to pins DO1, DO2, DO3, and DO4; and all sensing nodes are brought out to pins S1, S2, S3, and S4. Optionally, the cathodes can be internally connected and brought out to a single pin. Other internal connections can also be made to accommodate a specific application.

[0045] In another, in Fig.In the embodiment shown in Figure 10, diode D5 and resistors R1 and R2 can be integrated into the control circuit in a module or integrated circuit 1000. In module 1000, nodes OCP, OCPG, GND, and VEE are all brought out to their respective pins. Module 1000 can be integrated together with other modules described above or eliminated entirely, as shown in Figure 10. Fig. The 3 multi-sensing circuit 100E shown was discussed.

[0046] Many other groupings of blocks or components in Fig. Steps 1-5 can be integrated into one or more modules or integrated circuits, as required for a specific application. Examples of Fig.Components 8-10 can be modified to accommodate a specific application. Diodes D1, D2, D3, D4, D5 and bias resistors R1 and R2 can also be implemented externally at the individual component level to form an integrated control circuit and an integrated power transistor module, if desired. Peak detector circuit 104 can be implemented with other multi-input peak detector circuits, if desired, and is not limited to those shown in Fig. The diode circuit implementation shown in 1-5 is limited.

[0047] With reference to Fig.In Section 11, an embodiment of the protection of multiple circuit breakers T1-T4 is initialized in step 1102. In step 1104, the voltage at each of the detection nodes S1-S4 of the multiple circuit breakers T1-T4 is measured or detected, and in step 1106, the highest detection voltage, which is the peak detection voltage, is selected. Steps 1104 and 1106 are automatically combined by the action of diodes D1-D4, as previously explained with respect to Tables I and II, but other circuits can be used to provide these functions independently in embodiments. The detected peak voltage, which is the difference between the voltage at nodes OCP and OCPG, is compared to an overcurrent threshold voltage in step 1108.In decision block 1110, the detected peak voltage is evaluated, and it is determined whether the detected peak voltage is greater than or not greater than the overcurrent threshold voltage. If "no," the procedure periodically returns to initialization step 1102. If "yes," the procedure then generates an overcurrent signal in step 1112. This overcurrent signal can then be used by the control circuit, or the control circuit in conjunction with other circuitry at the system level, to trip at least one of the multiple circuit breakers T1, T2, T3, and T4. Alternatively, a warning signal can be generated to indicate the presence of an overcurrent condition.

[0048] Peak voltage detection involves energizing one of several diodes D1-D4, each associated with several transistors coupled to several sensing resistors Rs1-Rs2. The detected peak sensing voltage, after evaluation by a control circuit, is used to perform a further action, such as turning off one or more of the transistors if the OCP voltage exceeds a predetermined threshold voltage, or, in some implementations, issuing a warning signal before deciding to turn off one or more of the transistors.

[0049] In summary, the current sensing outputs of N parallel-connected power switches detect the current peak (using diodes D1-D4) to determine a maximum value for the N current sensing outputs, which can then be evaluated and used as an overcurrent detection signal. Optionally, temperature compensation of the circuit (diode D5) is possible to improve performance.

[0050] Although the present invention has been described with reference to illustrative embodiments, this description should not be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to a person skilled in the art upon reference to the description. The attached claims are therefore intended to include all such modifications or embodiments.

Claims

Circuit (100A, 100B, 100C, 100D, 100E) comprising: a transistor sub-circuit (106) with multiple detection nodes and a gate node; a peak detector (104) with multiple inputs coupled to the multiple detection nodes of the transistor sub-circuit (106) and an output; and a control sub-circuit (102) with a gate control node coupled to the gate node of the transistor sub-circuit (106) and an overcurrent protection node coupled to the output of the peak detector (104), wherein the peak detector (104) comprises multiple diodes (D1-D4), each diode of the multiple diodes (D1-D4) having an anode coupled to one of the multiple inputs of the peak detector (104) and a cathode coupled to the output of the peak detector (104). Circuit (100A, 100B, 100C, 100D, 100E) according to claim 1, wherein the transistor sub-circuit (106) comprises several transistors (T1-T4) connected in parallel, each transistor of the several transistors (T1-T4) connected in parallel having a collector coupled to a first current node of the transistor sub-circuit (106), an emitter coupled to a second current node of the transistor sub-circuit (106), and a gate coupled to the gate node of the transistor sub-circuit (106). Circuit (100A, 100B, 100C, 100D, 100E) according to claim 2, wherein each transistor of the multiple parallel-connected transistors (T1-T4) further comprises an additional emitter coupled to a respective sensing node of the multiple sensing nodes. Circuit (100A, 100B, 100C, 100D, 100E) according to one of claims 1 to 3, wherein each transistor of the several parallel connected transistors (T1-T4) further comprises a detection resistor (Rs1-Rs4) coupled to a respective detection node of the several detection nodes. Circuit (100A, 100B, 100C, 100D, 100E) according to any one of claims 1 to 4, wherein the peak detector (104) further comprises an additional diode (D5) coupled between a ground and a reference output of the peak detector (104), a first resistor (I1) coupled between the output of the peak detector (104) and a voltage source, and a second resistor (I2) coupled between the reference output of the peak detector (104) and the voltage source. Circuit (100A, 100B, 100C, 100D, 100E) according to claim 5, wherein the voltage source comprises a negative voltage source. Circuit (100A, 100B, 100C, 100D, 100E) according to claim 5 or 6, wherein the reference output of the peak detector (104) is coupled to an overcurrent protection ground node of the control circuit (102). Circuit (100A, 100B, 100C, 100D, 100E) comprising: several diodes (D1-D4), each diode having an anode coupled to a corresponding sensing node and a cathode coupled to an overcurrent protection node; several resistors (Rs1-Rs4), each resistor coupled between the corresponding sensing nodes and ground; a first additional resistor (I1) coupled between the overcurrent protection nodes and a negative voltage source; a first additional diode (D5) coupled between ground and an overcurrent protection ground node; and a second additional resistor (I2) coupled between the overcurrent protection ground node and the negative voltage source. Circuit (100A, 100B, 100C, 100D, 100E) according to claim 8, wherein the multiple diodes (D1-D4) are coupled to corresponding multiple transistors (T1-T4) and are integrated together in a module. Circuit (100A, 100B, 100C, 100D, 100E) according to claim 8, wherein the multiple diodes (D1-D4) are integrated together in one module. Circuit (100A, 100B, 100C, 100D, 100E) according to one of claims 8 to 10, further comprising a control circuit (102) coupled to the overcurrent protection node and the overcurrent protection ground node. Circuit (100A, 100B, 100C, 100D, 100E) according to one of claims 8 to 11, wherein the negative voltage source comprises a charging pump. A method for protecting several transistors (T1-T4), comprising: sensing an emitter voltage of each of the several transistors (T1-T4); detecting a peak emitter voltage; evaluating the detected peak emitter voltage to determine that the peak emitter voltage is above an overcurrent threshold voltage; and using the evaluated detected peak emitter voltage to change the operating condition of at least one of the several transistors (T1-T4), wherein the detection comprises energizing one of several diodes (D1-D4), each diode of the several diodes (D1-D4) being associated with a respective transistor of the several transistors (T1-T4). Method according to claim 13, wherein the detection comprises detecting a detection emitter voltage at each of the multiple transistors (T1-T4). Method according to claim 13 or 14, wherein the detection further comprises the respective coupling of several resistors (Rs1-Rs4) to the several diodes (D1-D4). Method according to one of claims 13 to 15, wherein the use of the detected peak emitter voltage comprises coupling the detected peak emitter voltage to a control circuit (102) in communication with the multiple transistors (T1-T4).

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