A communication interface circuit and a communication interface

Abstract

The embodiment of the application provides a communication interface circuit and a communication interface, which are applied to a signal sending end and include a power supply end, a terminal impedance unit, a first conduction unit, a second conduction unit and a control signal end. Because the second conduction unit can conduct a path between the signal sending end and a third end of the terminal impedance unit when the power supply end is not powered on or in the power-on process, the potential of the third end of the terminal impedance unit is equal to the potential of the signal sending end, and then the terminal impedance unit can block the current flowing from the signal sending end to the power supply end, thereby preventing the current from flowing backward.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication interface circuit and a communication interface. Background Technology

[0002] Currently popular high-speed serial interfaces such as PCIe, HDMI, DisplayPort, and SGMII all utilize point-to-point serial communication technology to transmit signals between chips and systems. Simply put, a high-speed transmission interface system consists of three parts: the transmitter (TX), the transmission medium (cable), and the receiver (RX). The connection between the TX and RX ends can be either DC coupling or AC coupling.

[0003] In DC-coupled connections, especially in high-speed applications such as transmitting 4K or even 8K high-definition video signals via HDMI, a terminating impedance is often required at the TX end to improve signal quality and reduce reflections, ensuring stable and accurate reception of high-speed serial signals at the RX end. Since the TX and RX ends are in different systems, their interface (IO) power supplies are also independent.

[0004] For low-speed transmission, the TX terminal has no terminating impedance, and the driving circuit is open-drain. Therefore, there is no path from the RX terminal I / O power supply to the TX terminal I / O power supply, and thus no current flows back from the RX terminal I / O power supply to the TX terminal I / O power supply. For high-speed transmission, the TX terminal has a terminating impedance, so there is a path consisting of the RX terminal I / O power supply, the RX terminal terminating impedance, the cable, the TX terminal terminating impedance, and the TX terminal I / O power supply. Under normal operation, this path works without problems. However, if the TX terminal is not used or has not yet entered normal operation, but the RX terminal has already been powered on and there is a cable connection between the TX and RX terminals, current will flow back from the RX terminal power supply to the TX terminal power supply. This will cause abnormal startup of the TX terminal or prevent it from starting normally, resulting in abnormal signal transmission and possibly burning out the TX terminal I / O circuit. Summary of the Invention

[0005] This application provides a communication interface circuit and a communication interface to prevent the power supply current at the receiving end of the communication interface from flowing back to the power supply at the transmitting end.

[0006] In a first aspect, embodiments of this application provide a communication interface circuit applied to a signal transmitting end, comprising: a power supply end, a terminal impedance unit, a first conduction unit, a second conduction unit, and a control signal end;

[0007] The first end of the terminating impedance unit is connected to the power supply terminal and the first end of the first conducting unit, the second end of the terminating impedance unit is connected to the signal transmitting terminal and the first end of the second conducting unit, the third end of the terminating impedance unit is connected to the second end of the second conducting unit and the control signal terminal, and the fourth end of the terminating impedance unit is connected to the second end of the first conducting unit and the third end of the second conducting unit; the fourth end of the second conducting unit is connected to the power supply terminal.

[0008] The second conducting unit is used to block the path between the signal transmitting end and the third terminal of the terminal impedance unit when the power supply is normally powered on, and to conduct the path between the signal transmitting end and the third terminal of the terminal impedance unit when the power supply is not powered on or during the power-on process, so that the potential of the third terminal of the terminal impedance unit is equal to the potential of the signal transmitting end.

[0009] The control signal terminal is used to provide a control signal to the third terminal of the terminal impedance unit when the power supply terminal is normally powered, so as to control the impedance of the terminal impedance unit.

[0010] The terminating impedance unit is used to provide the required terminating impedance between the signal transmitting end and the power supply end after receiving the control signal, and to block the current flowing from the signal transmitting end to the power supply end when the power supply end is not powered on or is powered on.

[0011] The first conducting unit is used to provide the fourth terminal of the terminal impedance unit and the third terminal of the second conducting unit with the same potential as the power supply terminal when the power supply terminal is normally powered, and to block the current flowing from the signal transmitting terminal to the power supply terminal when the power supply terminal is not powered or is powered on.

[0012] In some embodiments, the terminating impedance unit includes a first MOS transistor and a first resistor;

[0013] The first end of the first resistor serves as the first end of the terminal impedance unit, and the second end of the first resistor is connected to the first end of the first MOS transistor.

[0014] The control terminal of the first MOS transistor serves as the third terminal of the terminating impedance unit, the second terminal of the first MOS transistor serves as the second terminal of the terminating impedance unit, and the third terminal of the first MOS transistor serves as the fourth terminal of the terminating impedance unit.

[0015] In some embodiments, the first conducting unit includes a second MOS transistor;

[0016] The first end of the second MOS transistor serves as the first end of the first conduction unit, and the control end of the second MOS transistor serves as the second end of the first conduction unit, and is connected to the second end and the third end of the second MOS transistor, respectively.

[0017] In some embodiments, the second conduction unit includes a third MOSFET, a first diode, a second diode, a second resistor, a Schmitt trigger, and an inverter;

[0018] The first end of the second resistor serves as the fourth end of the second conducting unit and is connected to the anode of the first diode. The second end of the second resistor is connected to the input of the Schmitt trigger.

[0019] The power supply terminal of the Schmitt trigger is connected to the power supply terminal of the inverter, the cathode of the first diode, and the cathode of the second diode, respectively, and the output terminal of the Schmitt trigger is connected to the input terminal of the inverter.

[0020] The output terminal of the inverter is connected to the control terminal of the third MOS transistor;

[0021] The first end of the third MOS transistor serves as the second end of the second conduction unit, the second end of the third MOS transistor serves as the first end of the second conduction unit and is connected to the anode of the second diode, and the third end of the third MOS transistor serves as the third end of the second conduction unit.

[0022] In some embodiments, a control unit and a mode selection terminal are also included;

[0023] The first terminal of the control unit is connected to the mode selection terminal, the second terminal of the control unit is connected to the control signal terminal, the third terminal of the control unit is connected to the power supply terminal, and the fourth terminal of the control unit is connected to the third terminal of the terminal impedance unit.

[0024] The control unit is configured to, when the mode selection terminal outputs a first mode signal, block the path between the third and fourth terminals of the control unit and open the path between the second and fourth terminals of the control unit, so that the control signal is input to the third terminal of the terminal impedance unit to control the impedance of the terminal impedance unit; and when the mode selection terminal outputs a second mode signal, block the path between the second and fourth terminals of the control unit and open the path between the third and fourth terminals of the control unit to control the terminal impedance unit to turn off.

[0025] In some embodiments, the control unit includes a fourth MOSFET, a fifth MOSFET, and a third diode;

[0026] The control terminal of the fourth MOS transistor serves as the first terminal of the control unit and is connected to the control terminal of the fifth MOS transistor. The first terminal of the fourth MOS transistor serves as the fourth terminal of the control unit and is connected to the cathode of the third diode. The second terminal of the fourth MOS transistor serves as the second terminal of the control unit. The first terminal of the fifth MOS transistor serves as the third terminal of the control unit, and the second terminal of the fifth MOS transistor is connected to the anode of the third diode.

[0027] In some embodiments, an electrostatic discharge protection unit is also included;

[0028] The electrostatic protection unit is connected between the power supply terminal and the third terminal of the terminating impedance unit.

[0029] The electrostatic protection unit is used for electrostatic protection.

[0030] In some embodiments, the electrostatic protection unit includes a first capacitor;

[0031] The first end of the first capacitor is connected to the power supply terminal, and the second end of the first capacitor is connected to the third end of the terminating impedance unit.

[0032] In some embodiments, a control signal generation circuit is also included;

[0033] The control signal generation circuit includes a third resistor, a first current source, a second current source, an amplifier, and a communication interface replication circuit.

[0034] The first end of the third resistor is connected to the power supply terminal, and the second end of the third resistor is connected to the input terminal of the first current source and the negative input terminal of the amplifier, respectively; the output terminal of the first current source is grounded; the positive input terminal of the amplifier is connected to the first terminal of the communication interface replication circuit and the input terminal of the second current source, respectively; the output terminal of the amplifier is connected to the second terminal of the communication interface replication circuit and the control signal terminal, respectively; the output terminal of the second current source is grounded.

[0035] The communication interface replication circuit is used to determine a control signal based on the current of the second current source. In a second aspect, embodiments of this application also provide a communication interface, including a communication interface circuit, a transmission medium, and a signal receiving end connected in series, wherein the communication interface circuit is the communication interface circuit described in any of the first aspects.

[0036] This application provides a communication interface circuit and a communication interface. The communication interface circuit is applied to a signal transmitting end and includes: a power supply end, a terminating impedance unit, a first conducting unit, a second conducting unit, and a control signal end. The first end of the terminating impedance unit is connected to both the power supply end and the first end of the first conducting unit. The second end of the terminating impedance unit is connected to both the signal transmitting end and the first end of the second conducting unit. The third end of the terminating impedance unit is connected to both the second end of the second conducting unit and the control signal end. The fourth end of the terminating impedance unit is connected to both the second end of the first conducting unit and the third end of the second conducting unit. The fourth end of the second conducting unit is connected to the power supply end. The second conducting unit is used to block the path between the signal transmitting end and the third end of the terminating impedance unit when the power supply end is normally powered, and to block the path when the power supply end is not powered on or... During power-on, the path between the signal transmitting end and the third terminal of the terminating impedance unit is established, so that the potential of the third terminal of the terminating impedance unit is equal to the potential of the signal transmitting end. The control signal end is used to provide a control signal to the third terminal of the terminating impedance unit when the power supply is normally powered, thereby controlling the impedance of the terminating impedance unit. The terminating impedance unit, upon receiving the control signal, provides the required terminating impedance between the signal transmitting end and the power supply, and blocks the current flowing from the signal transmitting end to the power supply when the power supply is not powered or during power-on. The first conducting unit is used to provide a potential equal to that of the power supply to the fourth terminal of the terminating impedance unit and the third terminal of the second conducting unit when the power supply is normally powered, and blocks the current flowing from the signal transmitting end to the power supply when the power supply is not powered or during power-on. When the power supply is not powered on or during the power-on process, the second conducting unit can conduct the path between the signal transmitting end and the third terminal of the terminating impedance unit, so that the potential of the third terminal of the terminating impedance unit is equal to the potential of the signal transmitting end, thereby enabling the terminating impedance unit to block the current flowing from the signal transmitting end to the power supply end and prevent current backflow. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a communication interface circuit provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of another communication interface circuit provided in an embodiment of this application;

[0040] Figure 3This is a schematic diagram of another communication interface circuit provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of another communication interface circuit provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of a control signal generation circuit provided in an embodiment of this application;

[0043] Figure 6a A simplified structural diagram of a low-speed serial transmit-receive system provided in this application embodiment;

[0044] Figure 6b A simplified structural diagram of a high-speed serial transmit-receive system provided in this application embodiment;

[0045] Figure 7 This is a schematic diagram of a communication interface provided in an embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0047] Since high-speed serial interfaces require a terminating impedance at the TX end when used in high-speed applications, there is a risk that the RX end IO power supply may flow back to the TX end IO power supply when the TX end IO power supply is not powered on or during power-on. Therefore, this application provides a communication interface circuit that can effectively prevent the RX end IO power supply from flowing back to the TX end IO power supply.

[0048] like Figure 1 As shown, a communication interface circuit provided in this application embodiment is applied to the signal transmitting end OUT, including: power supply end VCCT, terminal impedance unit 101, first conduction unit 102, second conduction unit 103 and control signal end Vctrl;

[0049] The first terminal of the terminating impedance unit 101 is connected to the power supply terminal VCCT and the first terminal of the first conducting unit 102, respectively. The second terminal of the terminating impedance unit 101 is connected to the signal transmitting terminal OUT and the first terminal of the second conducting unit 103, respectively. The third terminal of the terminating impedance unit 101 is connected to the second terminal of the second conducting unit 103 and the control signal terminal Vctrl, respectively. The fourth terminal of the terminating impedance unit 101 is connected to the second terminal of the first conducting unit 102 and the third terminal of the second conducting unit 103, respectively. The fourth terminal of the second conducting unit 103 is connected to the power supply terminal VCCT.

[0050] The second conducting unit 103 is used to block the path between the signal transmitting end OUT and the third terminal of the terminal impedance unit 101 when the power supply VCCT is normally powered on, and to conduct the path between the signal transmitting end OUT and the third terminal of the terminal impedance unit 101 when the power supply VCCT is not powered on or during the power-on process, so that the potential of the third terminal of the terminal impedance unit 101 is equal to the potential of the signal transmitting end OUT.

[0051] It should be noted that when the power supply VCCT is normally powered, the path between the signal transmitting end OUT and the third terminal of the terminating impedance unit 101 is blocked, and the voltage of the control signal end Vctrl will be applied to the third terminal of the terminating impedance unit 101. That is, the voltage of the third terminal of the terminating impedance unit 101 is dominated by Vctrl. When the power supply VCCT is not powered on or during the power-on process, the control signal end Vctrl should be in a high-impedance state. Since the path between the signal transmitting end OUT and the third terminal of the terminating impedance unit 101 is open, the voltage of the signal transmitting end OUT will be applied to the third terminal of the terminating impedance unit 101. That is, the voltage of the third terminal of the terminating impedance unit 101 is dominated by the voltage at OUT.

[0052] The control signal terminal Vctrl is used to provide a control signal to the third terminal of the terminal impedance unit 101 when the power supply terminal VCCT is normally powered, so as to control the impedance of the terminal impedance unit 101.

[0053] The terminating impedance unit 101 is used to provide the required terminating impedance between the signal transmitting end OUT and the power supply end VCCT after receiving the control signal, and to block the current flowing from the signal transmitting end OUT to the power supply end VCCT when the power supply end VCCT is not powered on or during the power-on process.

[0054] The first conducting unit 102 is used to provide the fourth terminal of the terminal impedance unit 101 and the third terminal of the second conducting unit 103 with a potential equal to that of the power supply terminal VCCT when the power supply terminal VCCT is normally powered on, and to block the current flowing from the signal transmitting terminal OUT to the power supply terminal VCCT when the power supply terminal VCCT is not powered on or during the power-on process.

[0055] It is worth noting that, in actual operation, the equal potentials mentioned in the embodiments of this application are not completely equal, but approximately equal.

[0056] The communication interface circuit provided in this application embodiment allows the second conducting unit 103 to conduct the path between the signal transmitting end OUT and the third terminal of the terminal impedance unit 101 when the power supply terminal VCCT is not powered on or during the power-on process. This makes the potential of the third terminal of the terminal impedance unit 101 equal to the potential of the signal transmitting end OUT, thereby enabling the terminal impedance unit 101 to block the current flowing from the signal transmitting end OUT to the power supply terminal VCCT and prevent current backflow.

[0057] It is worth noting that in the embodiments of this application, the power supply terminal VCCT refers to the IO power supply of the signal transmitting terminal OUT. When the signal transmitting terminal OUT in the high-speed transmission interface system is connected to the signal receiving terminal through the transmission medium (cable), the IO power supply of the signal receiving terminal may flow back to the IO power supply of the signal transmitting terminal OUT. The communication interface circuit provided in the embodiments of this application is applied to the signal transmitting terminal OUT, which can prevent the IO power supply of the signal receiving terminal from flowing back to the IO power supply of the signal transmitting terminal through the transmission medium.

[0058] In specific implementation, such as Figure 2 As shown, the terminating impedance unit 101 may include a first MOSFET M1 and a first resistor R1; the first end of the first resistor R1 serves as the first end of the terminating impedance unit 101, and the second end of the first resistor R1 is connected to the first end of the first MOSFET M1; the control end of the first MOSFET M1 serves as the third end of the terminating impedance unit 101, the second end of the first MOSFET M1 serves as the second end of the terminating impedance unit 101, and the third end of the first MOSFET M1 serves as the fourth end of the terminating impedance unit 101.

[0059] In specific implementation, such as Figure 2 As shown, the first conduction unit 102 may include a second MOS transistor M2; the first end of the second MOS transistor M2 serves as the first end of the first conduction unit 102, and the control end of the second MOS transistor M2 serves as the second end of the first conduction unit 102, and is respectively connected to the second end of the second MOS transistor M2 and the third end of the second MOS transistor M2.

[0060] In specific implementation, such as Figure 2As shown, the second conduction unit 103 may include a third MOSFET M3, a first diode D1, a second diode D2, a second resistor R2, a Schmitt trigger SCHMT, and an inverter INVO. The first end of the second resistor R2 serves as the fourth end of the second conduction unit 103 and is connected to the anode of the first diode D1. The second end of the second resistor R2 is connected to the input end of the Schmitt trigger SCHMT. The power supply end of the Schmitt trigger SCHMT is connected to the power supply end of the inverter INVO, the cathode of the first diode D1, and the cathode of the second diode D2, respectively. The output end of the Schmitt trigger SCHMT is connected to the input end of the inverter INVO. The output end of the inverter INVO is connected to the control end of the third MOSFET M3. The first end of the third MOSFET M3 serves as the second end of the second conduction unit 103 and is connected to the anode of the second diode D2. The third end of the third MOSFET M3 serves as the third end of the second conduction unit 103.

[0061] In specific implementation, such as Figure 3 As shown, it may also include a control unit 104 and a mode selection terminal EN;

[0062] The first terminal of the control unit 104 is connected to the mode selection terminal EN, the second terminal of the control unit 104 is connected to the control signal terminal Vctrl, the third terminal of the control unit 104 is connected to the power supply terminal VCCT, and the fourth terminal of the control unit 104 is connected to the third terminal of the terminating impedance unit 101.

[0063] The control unit 104 is configured to, when the mode selection terminal EN outputs a first mode signal, block the path between the third and fourth terminals of the control unit 104 and open the path between the second and fourth terminals of the control unit 104 so that a control signal is input to the third terminal of the terminal impedance unit 101 to control the impedance of the terminal impedance unit 101; and when the mode selection terminal EN outputs a second mode signal, block the path between the second and fourth terminals of the control unit 104 and open the path between the third and fourth terminals of the control unit 104 to control the terminal impedance unit 101 to turn off.

[0064] Specifically, such as Figure 4As shown, the control unit 104 may include a fourth MOSFET M4, a fifth MOSFET M5, and a third diode D3; the control terminal of the fourth MOSFET M4 serves as the first terminal of the control unit 104 and is connected to the control terminal of the fifth MOSFET M5; the first terminal of the fourth MOSFET M4 serves as the fourth terminal of the control unit 104 and is connected to the cathode of the third diode D3; the second terminal of the fourth MOSFET M4 serves as the second terminal of the control unit 104; the first terminal of the fifth MOSFET M5 serves as the third terminal of the control unit 104; and the second terminal of the fifth MOSFET M5 is connected to the anode of the third diode D3.

[0065] In specific implementation, such as Figure 3 As shown, it may also include an electrostatic discharge (ESD) protection unit 105; the ESD protection unit 105 is connected between the power supply terminal VCCT and the third terminal of the terminating impedance unit 101. Specifically, as... Figure 4 As shown, the electrostatic discharge protection unit 105 may include a first capacitor C1; the first end of the first capacitor C1 is connected to the power supply terminal VCCT, and the second end of the first capacitor C1 is connected to the third end of the terminating impedance unit 101.

[0066] The electrostatic discharge protection unit 105 is used for electrostatic discharge protection. When electrostatic discharge occurs at the signal transmitting end OUT, a high voltage will be generated at the OUT end instantly, and the substrate B end of M1 will also rise rapidly. However, due to the presence of the capacitor C1 at the gate of M1, its gate voltage does not change during the instant, causing the source S and drain D of M1 to reverse, and the current is discharged to the power supply VCCT, thereby playing the role of electrostatic discharge protection.

[0067] It is worth noting that the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fifth MOS transistor M5 provided in this application embodiment are PMOS transistors, and the fourth MOS transistor M4 is an NMOS transistor. For any MOS transistor, the control terminal is the gate G, the first terminal is the source S, the second terminal is the drain D, and the third terminal is the substrate B. The connection structure of the substrates of the fourth MOS transistor M4 and the fifth MOS transistor M5 is not shown; conventional connections are sufficient. The substrate of M5 can be connected to the power supply terminal VCCT, and the substrate of M4 can be grounded.

[0068] The following is about Figure 4 The circuit structure shown illustrates the working principle of the communication interface circuit provided in the embodiments of this application:

[0069] The communication interface circuit provided in this application embodiment has the ability to prevent backflow of current, the ability to adjust impedance, the ability to select mode, and the ability to protect against electrostatic discharge (ESD).

[0070] 1. Anti-current backflow capability:

[0071] When the signal transmitting terminal OUT is connected to the RX terminal via cable, and the TX terminal power supply VCCT is not powered on or is in the process of being powered on, the potential of the OUT terminal is also the drain D potential of PMOS transistor M1. This potential is the RX terminal power supply voltage VCCR. Due to the presence of the parasitic PN junction between the drain D and substrate B of PMOS transistor M1, the potential of its substrate B is close to VCCR. Since the VCCT voltage is low, the gate of PMOS transistor M3 is 0V, and M3 is turned on, making the gate potential of M1 also close to VCCR. At this time, M1 is similar to a diode with its positive terminal connected to VCCT and its negative terminal connected to OUT. PMOS transistor M2 is also equivalent to a diode with its positive terminal connected to VCCT and its negative terminal connected to OUT. Due to the presence of D1 and D2, and the enable terminal EN being in a low-level state, NMOS transistor M4 is turned off, and the path from OUT to VCCT is blocked, so the current cannot flow back.

[0072] 2. It has adjustable impedance capability:

[0073] During normal operation, M3 is off, M2 pulls the substrate B of M1 up close to the power supply VCCT, the enable terminal EN is high, M5 is off, M4 is on, and the control voltage Vctrl (i.e., the control signal) is transmitted to the gate G of M1, turning M1 on. The value of Vctrl determines the magnitude of the on-resistance of M1, that is, the magnitude of the TX terminal termination impedance (the TX terminal termination impedance is R1 + R). M1 Meanwhile, the temperature coefficient of resistor R1 is opposite to that of M1, which plays a certain role in temperature compensation.

[0074] 3. Possesses mode selection capability:

[0075] This communication interface circuit is compatible with both low-speed and high-speed applications. When operating in high-speed mode and signal quality needs to be improved, EN is turned on (EN is set to 1), M4 is turned on, Vctrl is transmitted to the gate G of M1, M1 is turned on, that is, the termination impedance of the TX terminal is turned on. When operating in low-speed applications, the requirements for signal quality are not particularly strict. In order to save power, the termination impedance of the TX terminal can be turned off and EN is set to 0. At this time, M4 is turned off, M5 is turned on, M3 is still turned off, the gate G of M1 is pulled up close to the power supply voltage VCCT, M1 is in the off state, and its on-resistance is close to infinity.

[0076] 4. ESD protection capability:

[0077] When ESD occurs at the signal transmitting end OUT, a high voltage will be generated instantaneously at the OUT end, and the substrate B end of M1 will also rise rapidly. However, due to the presence of capacitor C1 at the gate of M1, its gate voltage does not change instantaneously, causing the source S and drain D of M1 to reverse, and the current is discharged to the power supply VCCT, thus playing the role of ESD protection.

[0078] This application embodiment also provides a control signal generation circuit for generating an adjustable control signal Vctrl, such as... Figure 5 As shown, this is a control signal generation circuit 200 provided in an embodiment of this application.

[0079] The control signal generation circuit 200 includes a third resistor R3 and a first current source I. D1 Second current source I D2 The amplifier (amp) and communication interface replication circuit (RTT') are connected; the first terminal of the third resistor R3 is connected to the power supply terminal VCCT, and the second terminal of the third resistor R3 is connected to the first current source I. D1 The input terminal of the amplifier is connected to the negative input terminal of the amplifier amp; the first current source I D1 The output terminal is grounded; the positive input terminal of amplifier amp is connected to the first terminal of the communication interface replication circuit RTT' and the second current source I, respectively. D2 The input terminal is connected, and the output terminal of the amplifier amp is connected to the second terminal of the communication interface replication circuit RTT' and the control signal terminal Vctrl, respectively; the second current source I D2 The output terminal is grounded; the communication interface replication circuit RTT' is used based on the second current source I. D2 The current is used to determine the control signal. Among them, the second current source I... D2 It is an adjustable current source.

[0080] The RTT internally refers to the implementation details provided in this application. Figure 4 The communication interface circuit shown is basically the same as RTT' in structure. The difference is that RTT' does not include the second conducting unit 103 in RTT. The rest of the structure is exactly the same, except that the impedance is a multiple relationship. That is, the terminal impedance value of RTT' is equal to the terminal impedance value of N*RTT. Where N can be equal to 10 or 100, which can be set according to the actual situation. The specific implementation can be that M1 and R1 in RTT are composed of N M1 and R1 in RTT' connected in parallel.

[0081] Since amplifier amp and RTT' form a negative feedback system, according to the concept of virtual short circuit of amplifier, VN≈VP, and the voltage of VN is determined by R3 and I. D1 The supply voltage (VP) is fixed, therefore the VP voltage is also fixed; its value is the difference between the supply voltage and the output signal swing. This can be adjusted by changing I...D2 The current can be used to indirectly adjust the voltage value of Vctrl, thereby adjusting the RTT' and the impedance of RTT.

[0082] like Figure 6a The diagram shown is a simplified structure of a low-speed serial transmit-receive system. In low-speed applications, there is no terminating impedance. That is, in low-speed applications, when the transmitter (TX) and receiver (RX) are connected via a cable, there is no terminating impedance, and therefore, there is no backflow from the receiver's power supply (VCCR) to the transmitter's power supply (VCCT). Figure 6b The diagram shown is a simplified structure of a high-speed serial transmit-receive system. In high-speed applications, a termination impedance RTT is connected. However, the communication interface circuit provided in this application embodiment can prevent the power supply VCCR at the receiving end from flowing back into the power supply VCCT at the transmitting end.

[0083] The implementation of the communication interface circuit provided in the embodiments of this application is briefly summarized below, which may include the following steps:

[0084] The first step is to design a communication interface circuit with current backflow prevention capability, in which the terminal impedance value is controlled by the control signal Vctrl.

[0085] The second step is to generate a static reference voltage VN, which is equal to I. D1 *R3;

[0086] The third step involves using the reference voltage VN generated in the previous step, amplifier amp, RTT', and adjustable current bias I. D2 This forms a negative feedback system and generates a control signal Vctrl;

[0087] The fourth step is to use the control signal Vctrl generated in the previous step to control the terminating impedance RTT of multiple signal output terminals.

[0088] Based on the same application concept, such as Figure 7 As shown, this application embodiment also provides a communication interface, including a communication interface circuit 701, a transmission medium 702 and a signal receiving end 703 connected in series, wherein the communication interface circuit is the communication interface circuit as described above.

[0089] In this embodiment, a communication interface circuit is provided at the signal transmitting end to improve the signal quality in the channel. When cable and RX are connected, it effectively prevents the IO power supply current of the RX end from flowing back into the IO power supply of the TX end, ensuring that the TX end can start normally without being interfered with by the RX end. The shut-off capability and adjustable resistance value of the TX end termination impedance can effectively take into account both low-speed and high-speed applications, and can optimize power consumption by compromise. The TX end termination impedance circuit also has the ESD protection function of the IO port, avoiding the need to add additional ESD circuits and effectively reducing the parasitic load of the TX output port.

[0090] Those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A communication interface circuit, applied at a signal transmitting end, characterized in that, include: Power supply terminal, terminating impedance unit, first conduction unit, second conduction unit, and control signal terminal; The first end of the terminating impedance unit is connected to the power supply terminal and the first end of the first conducting unit, the second end of the terminating impedance unit is connected to the signal transmitting terminal and the first end of the second conducting unit, the third end of the terminating impedance unit is connected to the second end of the second conducting unit and the control signal terminal, and the fourth end of the terminating impedance unit is connected to the second end of the first conducting unit and the third end of the second conducting unit; the fourth end of the second conducting unit is connected to the power supply terminal. The second conducting unit is used to block the path between the signal transmitting end and the third terminal of the terminal impedance unit when the power supply is normally powered on, and to conduct the path between the signal transmitting end and the third terminal of the terminal impedance unit when the power supply is not powered on or during the power-on process, so that the potential of the third terminal of the terminal impedance unit is equal to the potential of the signal transmitting end. The control signal terminal is used to provide a control signal to the third terminal of the terminal impedance unit when the power supply terminal is normally powered, so as to control the impedance of the terminal impedance unit. The terminating impedance unit is used to provide the required terminating impedance between the signal transmitting end and the power supply end after receiving the control signal, and to block the current flowing from the signal transmitting end to the power supply end when the power supply end is not powered on or is powered on. The first conducting unit is used to provide the fourth terminal of the terminal impedance unit and the third terminal of the second conducting unit with the same potential as the power supply terminal when the power supply terminal is normally powered, and to block the current flowing from the signal transmitting terminal to the power supply terminal when the power supply terminal is not powered or is powered on.

2. The circuit as described in claim 1, characterized in that, The termination impedance unit includes a first MOS transistor and a first resistor; The first end of the first resistor serves as the first end of the terminal impedance unit, and the second end of the first resistor is connected to the first end of the first MOS transistor. The control terminal of the first MOS transistor serves as the third terminal of the terminating impedance unit, the second terminal of the first MOS transistor serves as the second terminal of the terminating impedance unit, and the third terminal of the first MOS transistor serves as the fourth terminal of the terminating impedance unit.

3. The circuit as described in claim 1, characterized in that, The first conducting unit includes a second MOS transistor; The first end of the second MOS transistor serves as the first end of the first conduction unit, and the control end of the second MOS transistor serves as the second end of the first conduction unit, and is connected to the second end and the third end of the second MOS transistor, respectively.

4. The circuit as described in claim 1, characterized in that, The second conduction unit includes a third MOSFET, a first diode, a second diode, a second resistor, a Schmitt trigger, and an inverter; The first end of the second resistor serves as the fourth end of the second conducting unit and is connected to the anode of the first diode. The second end of the second resistor is connected to the input of the Schmitt trigger. The power supply terminal of the Schmitt trigger is connected to the power supply terminal of the inverter, the cathode of the first diode, and the cathode of the second diode, respectively, and the output terminal of the Schmitt trigger is connected to the input terminal of the inverter. The output terminal of the inverter is connected to the control terminal of the third MOS transistor; The first end of the third MOS transistor serves as the second end of the second conduction unit, the second end of the third MOS transistor serves as the first end of the second conduction unit and is connected to the anode of the second diode, and the third end of the third MOS transistor serves as the third end of the second conduction unit.

5. The circuit as described in claim 1, characterized in that, It also includes a control unit and a mode selection terminal; The first terminal of the control unit is connected to the mode selection terminal, the second terminal of the control unit is connected to the control signal terminal, the third terminal of the control unit is connected to the power supply terminal, and the fourth terminal of the control unit is connected to the third terminal of the terminal impedance unit. The control unit is configured to, when the mode selection terminal outputs a first mode signal, block the path between the third and fourth terminals of the control unit and open the path between the second and fourth terminals of the control unit, so that the control signal is input to the third terminal of the terminal impedance unit to control the impedance of the terminal impedance unit; and when the mode selection terminal outputs a second mode signal, block the path between the second and fourth terminals of the control unit and open the path between the third and fourth terminals of the control unit to control the terminal impedance unit to turn off.

6. The circuit as described in claim 5, characterized in that, The control unit includes a fourth MOSFET, a fifth MOSFET, and a third diode; The control terminal of the fourth MOS transistor serves as the first terminal of the control unit and is connected to the control terminal of the fifth MOS transistor. The first terminal of the fourth MOS transistor serves as the fourth terminal of the control unit and is connected to the cathode of the third diode. The second terminal of the fourth MOS transistor serves as the second terminal of the control unit. The first terminal of the fifth MOS transistor serves as the third terminal of the control unit, and the second terminal of the fifth MOS transistor is connected to the anode of the third diode.

7. The circuit as described in claim 1, characterized in that, It also includes an electrostatic discharge protection unit; The electrostatic protection unit is connected between the power supply terminal and the third terminal of the terminating impedance unit. The electrostatic protection unit is used for electrostatic protection.

8. The circuit as described in claim 7, characterized in that, The electrostatic protection unit includes a first capacitor; The first end of the first capacitor is connected to the power supply terminal, and the second end of the first capacitor is connected to the third end of the terminating impedance unit.

9. A communication interface, characterized in that, It includes a communication interface circuit, a transmission medium, and a signal receiving end connected in series, wherein the communication interface circuit is the communication interface circuit as described in any one of claims 1-8.

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