A redundant logic gate cascade circuit based on dynamic threshold and path synergy

Abstract

The utility model discloses a kind of redundant logic gate cascade circuit based on dynamic threshold and path cooperation, the circuit includes: adaptive control module includes clock signal input end, reset signal input end, noise sensing signal input end, detection enable signal input end, high noise threshold input end, low noise threshold input end, threshold selection signal output end and redundant path enable signal output end;Redundant logic gate array module includes the redundant path enable signal input end of being connected with redundant path enable signal output end one-to-one correspondence, redundant logic gate unit input end and redundant logic gate array output end;Multiple voter module includes the threshold selection signal input end being connected with threshold selection signal output end, the redundant logic gate output signal input end being connected with redundant logic gate array output end one-to-one correspondence and voting signal output end.The utility model can improve the anti-interference ability of circuit, to dynamically adapt different noise level, reduce resource waste.

Description

Technical Field

[0001] This utility model relates to the field of digital integrated circuit design technology, and in particular to a redundant logic gate cascade circuit based on dynamic threshold and path coordination. Background Technology

[0002] In the field of digital integrated circuits, signal crosstalk is a common problem: capacitive coupling between adjacent signal lines causes distortion of the logic gate output signal, such as rising edge jitter or falling edge jitter, which may lead to timing errors. Traditional triple modular redundancy (TMR) requires replicating the entire module and always enabling three redundancies, resulting in a large area overhead (increasing by more than 200%), insufficient fault tolerance in high-noise scenarios, and resource waste in low-noise scenarios. Other solutions employ a single voting threshold or static redundancy. However, a single voting threshold cannot adapt to different noise levels; static redundancy cannot dynamically adapt to changes in noise intensity, resulting in low resource utilization. Utility Model Content

[0003] The purpose of this invention is to address the shortcomings of existing technologies by providing a redundant logic gate cascade circuit based on dynamic threshold and path coordination.

[0004] The purpose of this utility model is achieved through the following technical solution: a redundant logic gate cascade circuit based on dynamic threshold and path coordination, comprising:

[0005] The adaptive control module includes a clock signal input terminal, a reset signal input terminal, a noise sensing signal input terminal, a detection enable signal input terminal, a set of high noise threshold input terminals, a set of low noise threshold input terminals, a threshold selection signal output terminal, and five redundant path enable signal output terminals.

[0006] The redundant logic gate array module includes five redundant path enable signal input terminals, five sets of redundant logic gate unit input terminals, and five redundant logic gate array output terminals; wherein, the five redundant path enable signal input terminals are respectively connected to the five redundant path enable signal output terminals of the adaptive control module.

[0007] Most voting module includes a threshold selection signal input terminal, five redundant logic gate output signal input terminals, and a voting signal output terminal; wherein, the threshold selection signal input terminal is connected to the threshold selection signal output terminal of the adaptive control module, and the five redundant logic gate output signal input terminals are respectively connected to the five redundant logic gate array output terminals of the redundant logic gate array module.

[0008] Furthermore, the redundant logic gate array module is composed of five functionally identical redundant logic gate array sub-units in parallel. Each redundant logic gate array sub-unit includes a redundant logic gate module and a redundant path enable control module. The redundant logic gate module is a gate circuit module composed of redundant logic basic units. The redundant path enable control module is composed of an AND gate. The input terminal of the redundant logic gate module is the input terminal of the redundant logic gate unit of the redundant logic gate array module. The output terminal of the redundant logic gate module is connected to one input terminal of the AND gate. The other input terminal of the AND gate is the redundant path enable signal input terminal of the redundant logic gate array module. The output terminal of the AND gate is the redundant logic gate array output terminal of the redundant logic gate array module.

[0009] Furthermore, the types of redundant logic basic units include combinational logic gate units and sequential logic gate units. Combinational logic gate units include AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, and XNOR gates. Sequential logic gate units include D-type flip-flops.

[0010] Furthermore, in the redundant logic gate array module, the physical layout of the redundant logic gate modules is distributed in a dispersed manner, and the parallel wiring length of adjacent redundant paths is limited.

[0011] Furthermore, the physical layout of the redundant logic gate module adopts a diagonal layout strategy.

[0012] Furthermore, the adaptive control module includes a two-stage D flip-flop synchronizer, a single-stage D flip-flop, an XOR gate, a state machine, and a 2-to-1 multiplexer. The data input terminal of the two-stage D flip-flop synchronizer serves as the noise sensing signal input terminal of the adaptive control module. The clock input terminals of the two-stage D flip-flop synchronizer, the single-stage D flip-flop, and the state machine are connected and serve as the clock signal input terminal of the adaptive control module. The reset control terminals of the two-stage D flip-flop synchronizer, the single-stage D flip-flop, and the state machine are connected and serve as the reset signal input terminal of the adaptive control module. The output terminal of the two-stage D flip-flop synchronizer is connected to the data input terminal of the single-stage D flip-flop and one input terminal of the XOR gate. The output terminal of the single-stage D flip-flop is... The state machine is connected to the other input of an XOR gate, and the output of the XOR gate is connected to the noise edge input of the state machine. The detection enable signal input, high noise threshold input, and low noise threshold input of the state machine are the detection enable signal input, high noise threshold input, and low noise threshold input of the adaptive control module. The noise state output of the state machine is the threshold selection signal output of the adaptive control module. The state machine also includes a window counter and a noise counter. The noise state output of the state machine is connected to the selection control signal input of a 2-to-1 multiplexer. The two data inputs of the 2-to-1 multiplexer receive the redundant path enable control signals corresponding to the dual noise states, and the output of the 2-to-1 multiplexer is the redundant path enable signal output of the adaptive control module.

[0013] Furthermore, the majority voter module includes an adder, a 2-to-1 multiplexer, and a comparator; wherein, the five input terminals of the adder are the output signal input terminals of the five redundant logic gates of the majority voter module, and the output terminal of the adder is connected to one set of input terminals of the comparator; the two data input terminals of the 2-to-1 multiplexer respectively receive the voting threshold corresponding to the dual-noise state, the selection control signal input terminal of the 2-to-1 multiplexer is the threshold selection signal input terminal of the majority voter module, the output terminal of the 2-to-1 multiplexer is connected to another set of input terminals of the comparator; the output terminal of the comparator is the voting signal output terminal of the majority voter module.

[0014] Furthermore, the circuit also includes an output register or a low-pass filter or a filtering unit, the input of which is connected to the voting signal output of the majority voter module.

[0015] Compared with the prior art, the beneficial effects of this utility model are:

[0016] (1) This utility model utilizes a dynamic coordination mechanism of path quantity and voting threshold to achieve anti-crosstalk through a hardware-level voting mechanism. It improves the anti-crosstalk capability of the circuit by dynamically adjusting the number of redundant paths and voting threshold. For transient crosstalk, it suppresses local coupling noise through physical layout dispersion and dynamic voting, further optimizing the anti-crosstalk capability. The overall circuit structure can be adaptively adjusted according to the noise level. It is suitable for suppressing transient crosstalk errors in high-speed signals, especially for the protection of high noise sensitive signal paths in digital integrated circuits, and for the protection of critical signal paths in high noise environments.

[0017] (2) This utility model does not require module-level copying of the entire complete design module, but copies the logic units with the same function at the logic gate level (such as AND gate, OR gate), and the increase in redundant logic area is less than that of the traditional TMR method.

[0018] (3) This utility model is entirely implemented by digital logic circuits, has good compatibility, can support standard cell library implementation, does not require customized process, does not require modification of process library, and is compatible with standard digital design flow.

[0019] (4) This utility model can dynamically configure the threshold and support 2 / 3 or 3 / 5 voting modes to adapt to different reliability requirements.

[0020] (5) This utility model defines a dual noise state (high_noise / low_noise) and dynamically switches between the dual noise states through the state machine in the adaptive module; this utility model supports the dynamic activation of redundant paths (such as 3 or 5 paths) according to the noise level, and can dynamically manage power consumption. When the noise is low, some redundant paths are turned off to reduce power consumption; the dynamic redundancy configuration balances reliability and power consumption, and is suitable for low power consumption scenarios such as the Internet of Things. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the redundant logic gate cascade circuit based on dynamic threshold and path coordination of this utility model;

[0022] Figure 2 This is the schematic diagram of the redundant logic gate cascade circuit based on dynamic threshold and path coordination of this utility model.

[0023] Figure 3 This is an example diagram of the internal circuit of the redundant logic gate array module of this utility model (taking an AND gate as an example);

[0024] Figure 4 This is a schematic diagram of the diagonal layout of the five redundant logic gate modules of this utility model;

[0025] Figure 5 This is an example diagram of the internal circuit of the adaptive control module of this utility model;

[0026] Figure 6 This is a schematic diagram of the state machine transition in the adaptive control module of this utility model;

[0027] Figure 7 This is an example diagram of the internal circuit of the majority voting unit module of this utility model. Detailed Implementation

[0028] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0029] The present invention will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementation methods can be combined with each other.

[0030] like Figure 1 and Figure 2As shown, the redundant logic gate cascade circuit based on dynamic threshold and path coordination of this utility model includes an adaptive control module, a redundant gate array module, and a majority voter module. The adaptive control module includes a clock signal input terminal for receiving a clock signal clk, a reset signal input terminal for receiving a reset signal rst_n, a noise sensing signal input terminal for receiving a noise sensing signal noise_in, a detection enable signal input terminal for receiving a noise detection enable signal det_en, a set of high noise threshold input terminals for receiving an eight-bit high noise threshold signal NTH[7:0], a set of low noise threshold input terminals for receiving an eight-bit low noise threshold signal NTL[7:0], a threshold selection signal output terminal for outputting a threshold selection signal voter_config, and five redundant path enable signal output terminals for outputting five redundant path enable control signals redundancy_en[4:0]. The redundant logic gate array module includes five redundant path enable signal input terminals EN1~EN5 for receiving the five redundant path enable control signals redundancy_en[4:0] output by the five redundant path enable signal output terminals, five sets of redundant logic gate unit input terminals for receiving the input signals A1 / B1~A5 / B5 of the five redundant logic gates, and five redundant logic gate array output terminals for outputting the output signals OUT1~OUT5 of the five redundant logic gates. The five redundant path enable signal input terminals are respectively connected to the five redundant path enable signal output terminals of the adaptive control module. Most voting module includes a threshold selection signal input terminal for receiving the threshold selection signal voter_config output from the threshold selection signal output terminal, five redundant logic gate output signal input terminals in1 to in5 for receiving the output signals OUT1 to OUT5 of the five redundant logic gate array output terminals, and a voting signal output terminal for outputting the final voting signal final_out. The threshold selection signal input terminal is connected to the threshold selection signal output terminal of the adaptive control module, and the five redundant logic gate output signal input terminals in1 to in5 are respectively connected to the five redundant logic gate array output terminals of the redundant logic gate array module.

[0031] It should be noted that the cascaded circuit described in this invention can achieve crosstalk suppression, disperse the influence of noise, reduce power consumption, and avoid resource waste caused by global redundancy. The essential requirement for crosstalk suppression is that independent signal copies must be generated through physically isolated redundant paths. The principle is that when a redundant path experiences an output error due to crosstalk (e.g., G1 outputs an abnormally low level), the majority voting module can still generate the correct result based on the normal outputs of other paths (G2, G3, G4, G5). Therefore, redundant logic gate array modules are indispensable. They provide independent fault sources, meaning that each redundant logic gate is independent of the others. An error in one redundant logic gate will not affect other redundant logic gates, which is the physical basis for majority voting. Generating independent signal copies through physically redundant paths is an effective means of reducing the impact of crosstalk. If there is physical isolation between redundant paths, capacitive or inductive coupling can be effectively reduced, making the signal noise of each redundant path independent. Parallel processing of redundant logic gates can mitigate the impact of noise. The independence of each path reduces the probability of noise simultaneously breaking down all redundant paths. For example, if noise causes one path to fail, the remaining two normal paths can still output the correct result through majority voting, thereby improving noise tolerance. The power supply, ground, and signal drive circuits of redundant paths need to be designed independently to ensure that fault sources are independent and to avoid sharing common nodes or paths. The core assumption of the majority voting mechanism is that faults in redundant paths must be independent of each other. If all paths share the same logic gate or are affected by the same interference source, crosstalk or faults will affect all replicas simultaneously, causing the majority vote to fail.

[0032] In this embodiment, logic gates with the same function are replicated into five parallel logic gates, and redundant paths are added to enable the control module, forming a redundant logic gate array module whose input signals are accessed through different physical paths. For example... Figure 3 As shown, the redundant logic gate array module consists of five functionally identical redundant logic gate array sub-units arranged in parallel. Each redundant logic gate array sub-unit includes a redundant logic gate module and a redundant path enable control module. The redundant logic gate module is a gate circuit module composed of redundant logic basic units. The redundant path enable control module is composed of an AND gate. The input terminal of the redundant logic gate module is the input terminal of the redundant logic gate unit of the redundant logic gate array module. The output terminal of the redundant logic gate module is connected to one input terminal of the AND gate. The other input terminal of the AND gate is the redundant path enable signal input terminal of the redundant logic gate array module. The output terminal of the AND gate is the redundant logic gate array output terminal of the redundant logic gate array module.

[0033] It should be noted that in digital IC design, when a cell with insufficient timing margin encounters noise interference, it may cause several problems: ① Timing errors and metastability: Noise may cause signal transmission delay fluctuations, causing signals that are already close to the timing boundary to deviate further from the clock cycle, resulting in setup / hold time violations and thus metastability, manifested as the output signal being in an uncertain state before stabilization; ② Data errors: Noise superimposed on the signal may cause logic level ambiguity (such as high levels being pulled low or low levels being raised), which in turn causes logic gates to flip incorrectly, ultimately leading to data errors; ③ Decreased reliability: Paths with insufficient timing margin are more sensitive to noise, and may frequently fail due to noise accumulation during long-term operation, reducing the overall reliability of the chip. In this case, the cascaded circuit described in this invention is needed to improve these problems. Specifically, first, the redundant logic base units that need to be redundant are identified. Before selecting the redundant logic base units, noise sensitivity analysis is required: ① Critical path identification: High noise-sensitive paths are located through static timing analysis (STA), and units with insufficient timing margin (Slack) are prioritized for redundancy; ② Coupling effect assessment: Parasitic parameter extraction tools (such as StarRC) are used to quantify the coupling capacitance between signal lines, and redundancy is implemented for critical paths with relatively large coupling capacitance (e.g., >0.5fF). Then, redundancy is implemented on the selected redundant logic base units, and five logic gates with the same function (such as NAND gates) are configured in parallel on the critical path, with each gate independently processing the same input signal; noise may cause some paths to fail, but most paths can still output correctly. The majority result is selected as the final output through a majority voting module. By introducing redundant paths and adopting voting logic, the noise immunity can be effectively improved and the impact of noise can be reduced. Parallel processing of redundant logic gates can mitigate the impact of noise, and the independence of each path reduces the probability of noise simultaneously breaking down all paths. For example, if noise causes one path to fail, the remaining two normal paths can still output the correct result through majority voting, thereby improving noise tolerance. Redundant logic gate array modules and majority voter modules are deployed only on critical paths with the most insufficient timing margin and highest noise sensitivity to avoid resource waste caused by global redundancy.

[0034] It should be understood that, due to the need to introduce redundant paths and employ voting logic to improve noise immunity, specifically using a majority voting strategy (more than half in favor), the number of redundant paths needs to be an odd number greater than 1. Furthermore, with three-way redundancy, fault tolerance in high-noise scenarios is insufficient. With five-way redundancy, crosstalk immunity can be achieved through redundant logic gate modules, reducing the impact of noise, while also implementing a 2 / 3 voting mode in low-noise conditions and a 3 / 5 voting mode in high-noise conditions, without making the circuit overly complex. Therefore, the preferred number of redundant paths is 5, meaning the number of parallel redundant logic gate array sub-units in the redundant logic gate array module is five, and the redundant logic gate array module is composed of five functionally identical redundant logic gate array sub-units operating in parallel.

[0035] Furthermore, the types of redundant logic basic units include combinational logic gates such as AND gates, OR gates, XOR gates, and NAND gates, as well as sequential logic gates such as D-flip-flop (DFF) units. The types of redundant logic basic units are very flexible. Combinational logic gates such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, and XNOR gates can be used, with the advantage of not needing to consider timing synchronization, making implementation very simple. Alternatively, sequential logic gates such as DFFs can be used. When redundant DFFs, timing constraints need to be designed specifically. All redundant DFFs share the same clock network, and the clock skew must be less than the setup / hold time margin. Input data must reach each DFF through different wiring paths.

[0036] For example, to visually demonstrate the redundant logic gate array module, and to support a physically friendly implementation of a loosely coupled layout, in such... Figure 3 In the example of the redundant logic gate array module shown, the basic unit of redundant logic is selected as the AND gate to form the redundant logic gate module. For example... Figure 3 As shown, the five identical AND gates G1, G2, G3, G4, and G5 form a redundant logic gate module. This module uses only AND gates, but other redundant logic base units can also be selected. The input signals (A1-A5, B1-B5) of G1, G2, G3, G4, and G5 reach the input terminals of each gate through different wiring paths. Input signals A1-A5 and B1-B5 represent their source signals A and B reaching the input terminals of each gate through different wiring paths. The five identical AND gates U1, U2, U3, U4, and U5 form the redundancy path enable control module for each redundant logic gate module, used to control whether the corresponding redundant path is enabled. Figure 3As shown, the input terminals of G1, G2, G3, G4, and G5 serve as the input terminals of five redundant logic gate units in the redundant logic gate array module, receiving input signals A1 / B1 to A5 / B5 from G1, G2, G3, G4, and G5. The output terminals of G1, G2, G3, G4, and G5 are connected to one of the input terminals of U1, U2, U3, U4, and U5, respectively. The other input terminal of U1, U2, U3, U4, and U5 serves as the five redundant path enable signal input terminals EN1 to EN5 of the redundant logic gate array module. The output terminals of U1, U2, U3, U4, and U5 serve as the five redundant logic gate array output terminals of the redundant logic gate array module, outputting the output signals OUT1 to OUT5 of the five redundant logic gates. The EN1 to EN5 terminals receive the redundant path enable signal (active high), controlling whether the five redundant paths are enabled, thus helping to reduce power consumption. When the redundancy path enable signal is high, the corresponding redundancy path is enabled, and the output signal of the redundancy logic gate module can be sent to the majority voter module; otherwise, the corresponding redundancy path will be disabled, and the output signal of the redundancy logic gate module cannot be sent to the majority voter module. This redundancy gate array module includes five redundancy paths, and considering both low-noise and high-noise scenarios, it can support switching between 3 or 5 redundancy paths to support the 2 / 3 and 3 / 5 voting modes of the majority voter module.

[0037] Furthermore, the physical layout of the multiple redundant logic gate modules in the redundant logic gate array module is optimized. Specifically, the redundant logic gate modules are physically distributed in a dispersed manner, such as using a diagonal layout strategy. Figure 4 As shown, this effectively reduces the coupling probability of adjacent signal lines and limits the parallel routing length of adjacent redundant paths to ensure that the input traces of each redundant logic gate module have no overlapping areas. Redundant paths need to achieve electromagnetic field independence through inter-layer vertical routing, ground plane isolation, and increased spacing.

[0038] For example, a diagonal layout strategy is used to distribute the physical locations of redundant logic gate modules. The core idea of ​​the diagonal layout is to reduce the coupling capacitance between adjacent signal lines by maximizing the physical distance between redundant units, thereby reducing the probability of crosstalk. A typical implementation involves placing each redundant logic gate module in a diagonal area of ​​the chip layout, forming a triangular layout. In cases such as... Figure 3The redundant gate array (GNA) module shown contains five redundant gate modules. These five redundant gate modules are distributed as widely as possible during layout to reduce the coupling probability between them. Assuming a core area of ​​100μm × 100μm and a safety distance of corner_offset = 15μm satisfying the boundary DRC rules of the specific TSMC28 process, the coordinates of the five redundant gate modules can be arranged as follows: bottom left corner (15, 15), bottom right corner (85, 15), top left corner (15, 85), top right corner (85, 85), and center gate (50, 50). The final diagonal layout effect is as follows. Figure 4 As shown.

[0039] It should be noted that some key design rules in digital circuit layout are as follows: (1) Minimum spacing constraint: Add a minimum spacing constraint between redundant units in the back-end layout tool TCL script: set_redundant_spacing_rule-min_distance20. Its function is to force the spacing between redundant units to be ≥20μm (depending on the specific process) to ensure that the signal lines have sufficient isolation space. Ensure that the 5-way redundant logic gate modules are physically isolated and reduce the risk of multiple errors due to local coupling at the same time. (2) Routing layer specification: Add a constraint in the back-end layout tool TCL script to restrict the use of high-layer metals for redundant unit signal lines (to reduce coupling): set_preferred_routing_direction-layer M4 horizontal, set_preferred_routing_direction-layer M5vertical. The principle is that the spacing between high-layer metals (such as M4 / M5) is larger, and the coupling capacitance is 30% to 50% lower than that of the bottom metals (M1 / M2). (3) Prohibit parallel long line rule: Add a constraint in the backend layout tool TCL script to prohibit parallel routing between redundant units that exceeds 50μm: set_max_parallel_run_length-netRedundantGateArray / *50. Its function is to avoid continuous coupling interference caused by long-distance parallel routing in the RedundantGateArray module.

[0040] Here, we explain the core functions of the redundant gate array (BGA) module. ① The BGA module is the physical basis for crosstalk immunity: Path decentralization: By placing redundant gates in different physical locations, the probability of capacitive coupling between adjacent signal lines is reduced; Error isolation: Crosstalk on a single path only affects the output of the corresponding redundant gate, while other paths can still provide correct signals. ② The BGA module is a necessary condition for majority voting: Independent error source assumption: The fault causes of each redundant path must be independent; if all paths share the same logic gate, errors caused by crosstalk cannot be corrected through voting. ③ Dynamic reliability enhancement: Noise adaptation: By dynamically enabling or disabling redundant paths, power consumption is saved in low-noise scenarios, and fault tolerance is improved in high-noise scenarios.

[0041] In this embodiment, the adaptive control module calculates the real-time output noise level (i.e., low noise NTL or high noise NTH) based on the transition edge density of the noise sensing signal noise_in, and dynamically enables or disables redundant paths according to the noise level (5 redundancies are enabled for high noise, and only 3 redundancies are enabled for low noise). Figure 5As shown, the adaptive control module includes a two-stage D flip-flop synchronizer, a single-stage D flip-flop, an XOR gate, a state machine, and a 2-to-1 multiplexer (MUX). The data input of the two-stage D flip-flop synchronizer serves as the noise sensing signal input of the adaptive control module, receiving the noise sensing signal `noise_in`. The edge density of the noise sensing signal `noise_in` reflects the noise level; more edges per unit time indicate higher noise. The clock inputs (rising edge triggered) of the two-stage D flip-flop synchronizer, the single-stage D flip-flop, and the state machine are connected and serve as the clock signal input of the adaptive control module, receiving the clock signal `clk`. The reset control terminal of the two-stage D flip-flop synchronizer (low level triggers...) The reset control terminal (active low) of the first-stage D flip-flop and the reset control terminal (active high) of the state machine are connected, and serve as the reset signal input terminal of the adaptive control module for the reset signal rst_n; the output terminal of the two-stage D flip-flop synchronizer is connected to the data input terminal of the first-stage D flip-flop and one input terminal of the XOR gate, the output terminal of the first-stage D flip-flop is connected to the other input terminal of the XOR gate, and the output terminal of the XOR gate is connected to the noise edge input terminal of the state machine; the detection enable signal input terminal, high noise threshold input terminal, and low noise threshold input terminal of the state machine are the detection enable signal input terminal and high noise threshold input terminal of the adaptive control module. The state machine's noise state input and low noise threshold input are used to receive the noise detection enable signal det_en, the high noise threshold signal NTH[7:0], and the low noise threshold signal NTL[7:0], respectively. The detection enable signal det_en is used to start or stop noise state detection, and the high noise threshold signal NTH[7:0] and the low noise threshold signal NTL[7:0] are used to set the threshold for triggering entry into the high noise state or the low noise state. The noise state output of the state machine serves as the threshold selection signal output of the adaptive control module, used to output the threshold selection signal voter_config. The state machine also includes a window counter for outputting the window value. The counter values ​​window_counter[16:0] and noise counter are used to output the noise counter values ​​edge_counter[7:0], etc.; the noise state output terminal of the state machine is connected to the selection control signal input terminal of the 2-to-1 multiplexer. The two data input terminals of the 2-to-1 multiplexer receive the redundant path enable control signals 5'b00111 and 5'b11111 corresponding to the dual noise states, respectively. The output terminal of the 2-to-1 multiplexer is used as the redundant path enable signal output terminal of the adaptive control module to output the five-way redundant path enable control signal redundancy_en[4:0].

[0042] Specifically, such as Figure 6As shown, when the circuit is reset, i.e., when the state machine's reset control terminal receives a valid reset signal rst_n, the state machine enters the IDLE state. At this time, the window counter value and the noise counter value are initialized, and noise detection is disabled. During reset, the circuit's current noise state is assigned a default state, which can be either high_noise or low_noise. This ensures that even without noise detection enabled, the circuit can still perform majority voting after the reset, preventing it from becoming inoperable. After the reset is released, if the state machine's detection enable signal input terminal receives a valid noise detection enable signal det_en, the state machine transitions from the IDLE state to the COUNTING state. By detecting the noise detection enable signal det_en at the enable signal input terminal, the adaptive module can only start or stop counting detection when needed, helping to save power. In the COUNTING state, the noise counter integrated inside the state machine increments based on the transition edge of the noise sensing signal noise_in within the window time. That is, the window counter works to periodically detect the length of the window time; at the same time, it detects the transition edge of the received noise sensing signal noise_in, and the noise counter increments on the transition edge of the noise sensing signal noise_in; when the window time is reached, that is, when the window counter value window_counter[16:0] reaches the preset condition, the noise counter stops counting, outputs the noise counter value edge_counter[7:0], and the state machine enters the EVALUATE state. In the EVALUATE state, a decision is made between high noise (high_noise) and low noise (low_noise) based on the noise counter value edge_counter[7:0] and the input high noise threshold signal NTH[7:0] and low noise threshold signal NTL[7:0]. If the noise counter value edge_counter[7:0] is greater than the high noise threshold signal NTH[7:0] (e.g., the high noise threshold is set to 100), then the high noise state is triggered, and the noise state output terminal of the state machine outputs noise_state = 1; otherwise, if the noise counter value edge_counter[7:0] is less than the low noise threshold signal NTL[7:0] (e.g., the low noise threshold is set to 50), then the low noise state is triggered, and the noise state output terminal of the state machine outputs noise_state = 0. Simultaneously, the state machine transitions to the IDLE state, and the noise level will be re-detected. The adaptive module manages the different detection stages (i.e., IDLE, COUNTING, EVALUATE) through the state machine.

[0043] Among them, a two-stage D flip-flop synchronizer is used to synchronize the noise sensing signal noise_in, which can eliminate potential metastability; a single-stage D flip-flop delays the noise_sync2 signal output by the two-stage D flip-flop synchronizer by one beat to obtain the noise_dly signal. The noise_sync2 signal and the noise_dly signal are XORed together to obtain the noise_edge signal, which is then input into the state machine. In the COUNTING state of the state machine, the noise sensing signal noise_in can be counted on the transition edge to obtain the noise counter value edge_counter[7:0].

[0044] It should be understood that by introducing a fixed time window mechanism in the state machine, such as counting the number of transitions in the noise sensing signal `noise_in` every 1ms, infinite accumulation can be avoided while providing a clear detection period. The counting restarts at the end of each window, and noise level evaluation is triggered at the end of the window, achieving precise time window control and ensuring the consistency of noise evaluation cycles. The impact of the detection time window length on the system also needs to be considered, as a window that is too short may lead to inaccurate noise evaluation, while a window that is too long will affect real-time performance. Therefore, an appropriate window time needs to be selected based on the application scenario; for example, in digital circuits, windows are commonly in the microsecond to millisecond range. The noise counters in the state machine have an overflow protection mechanism, and each noise counter has an upper limit to prevent overflow and data errors caused by rollback. For example, a corresponding maximum value is set, and once exceeded, the maximum value is maintained.

[0045] Furthermore, since the noise state output of the state machine serves as the threshold selection signal output of the adaptive control module, outputting the threshold selection signal `voter_config`, the noise state `noise_state` output by the noise state output is precisely the threshold selection signal `voter_config`. The adaptive control module provides the threshold selection signal `voter_config` output by the noise state output to the majority voter module. The state machine dynamically enables or disables redundant paths based on the noise level, balancing power consumption and reliability. In a high-noise state (`noise_state = 1`), five redundant paths are enabled; in a low-noise state (`noise_state = 0`), only three redundant paths are enabled. Therefore, the state machine of the adaptive control module can achieve a mapping relationship between noise level and redundant path configuration.

[0046] Furthermore, the 2-to-1 MUX will select one of 5'b00111 and 5'b11111 as the output based on the selection control signal received at its selection control signal input terminal. This output is the five-way redundant path enable control signal redundancy_en[4:0] output by the redundant path enable signal output terminal of the adaptive control module, and the five-way redundant path enable control signal redundancy_en[4:0] is input to the redundant logic gate array module. Specifically, when noise_state = 0, the selection control signal received by the selection control signal input terminal of the 2-to-1 MUX is 0, and the 2-to-1 MUX will select 5'b00111 as the output, which is the five-way redundant path enable control signal redundancy_en[4:0] output by the redundant path enable signal output terminal; conversely, when noise_state = 1, the selection control signal received by the selection control signal input terminal of the 2-to-1 MUX is 1, and the 2-to-1 MUX will select 5'b11111 as the output, which is the five-way redundant path enable control signal redundancy_en[4:0] output by the redundant path enable signal output terminal.

[0047] It should be understood that the two data input terminals of the 2-to-1 MUX receive 5'b00111 and 5'b11111 respectively, which means that whether the redundant path is enabled in 3 or 5 ways, there will be three redundant path enable signals of 1.

[0048] like Figure 5 As shown, an external noise sensor or noise sensing module is responsible for providing the noise sensing signal noise_in. The density of the noise_in transition edges represents different noise levels. The adaptive control module detects the noise level in real time and provides the corresponding configuration, that is, the adaptive control module dynamically enables or disables redundant paths according to the noise level (5 redundant paths are enabled when the noise is high, and only 3 redundant paths are enabled when the noise is low). Specifically, in the low noise state, voter_config = 0, redundancy_en[4:0] = 00111B, the voting threshold used by the majority voter is set to 2, and the number of redundant paths enabled is 3; in the high noise state, voter_config = 1, redundancy_en[4:0] = 11111B, the voting threshold used by the majority voter is set to 3, and the number of redundant paths enabled is 5.

[0049] In this embodiment, as Figure 7As shown, the majority voting module includes an adder, a 2-to-1 multiplexer (MUX), and a comparator. Based on the adder, comparator, and MUX, configurable voting logic can be implemented. Specifically, the five inputs of the adder serve as the five redundant logic gate output signal inputs of the majority voting module, receiving the five output signals from the redundant logic gate array module. The output of the adder is connected to one set of inputs of the comparator. The two data inputs of the MUX receive voting thresholds T=2 and T=3 corresponding to the dual-noise state, respectively. The selection control signal input of the MUX serves as the threshold selection signal input of the majority voting module, receiving the threshold selection signal `voter_config` output by the adaptive control module. The output of the MUX is connected to another set of inputs of the comparator. The output of the comparator serves as the voting signal output of the majority voting module, outputting the final voting signal `final_out`.

[0050] It should be noted that most voting unit modules can be understood as a voting system. A voting system is a system in which at least T out of the N constituent units will remain functional; it is also called a T / N system, where T represents the voting threshold, 1 ≤ T ≤ N, and N represents N-way redundancy. The reliability mathematical model of this voting system is as follows:

[0051]

[0052] In the formula, R system This indicates the reliability of the voting system, and also the reliability of most voting unit modules; R represents the single-path reliability. Therefore, the following scheme is configured for the majority voting module: In low-noise mode, the number of enabled paths N is 3, the voting threshold T = 2, and the fault tolerance F = NT = 1 path. This corresponds to a 2 / 3 voting mode, which can be understood as a 3-to-2 voting mode, meaning at least 2 out of 3 votes are in agreement. Therefore, it is subsequently compared with the voting threshold 2 in the comparator. In high-noise mode, the number of enabled paths N is 5, the voting threshold T = 3, and the fault tolerance F = NT = 2 paths. This corresponds to a 3 / 5 voting mode, which can be understood as a 5-to-3 voting mode, meaning at least 3 out of 5 votes are in agreement. Therefore, it is subsequently compared with the voting threshold 3 in the comparator. Taking a single-path reliability R = 0.9 as an example, the reliability under the two configurations is compared, and the results are shown in Table 1.

[0053] Table 1: Reliability Comparison Results of Majority Voting Modules under Dual-Noise Conditions

[0054]

[0055] As shown in Table 1, the reliability is higher under high noise conditions; the higher the noise, the stronger the fault tolerance, but the number of redundant paths needs to be increased to maintain reliability.

[0056] Specifically, such as Figure 7 As shown, in1 to in5 are the output signals from the redundant logic gate array module. They represent the output signals of each redundant logic gate after being enabled. That is, the output signals OUT1 to OUT5 of the five redundant logic gates output from the redundant logic gate array output terminal of the redundant logic gate array module are input to the majority voter module through the five input terminals of the adder. The logical expression of the adder is cnt[2:0] = in1 + in2 + in3 + in4 + in5. The adder can add five 1-bit wide signals and then output the sum value cnt[2:0]. The sum value is a three-bit binary number with a range of 0 to 5.

[0057] The two data input terminals of the 2-to-1 MUX receive voting thresholds T=2 and T=3 corresponding to the dual-noise state, respectively. Then, it selects the voting threshold T=2 corresponding to the low-noise state or the voting threshold T=3 corresponding to the high-noise state through the threshold selection signal voter_config received from the adaptive control module at its threshold selection signal input terminal. The 2-to-1 MUX has two selectable voting thresholds for comparison, 2 and 3, which are selected by the threshold selection signal voter_config received by the 2-to-1 MUX. The logical expression of the 2-to-1 MUX is th=voter_config? 3:2, that is: if voter_config is 1, then th is assigned the value 3; if voter_config is 0, then th is assigned the value 2. In addition, in order to facilitate the comparison of th with cnt[2:0], th is also defined as a three-bit binary number, that is, the output terminal of the 2-to-1 MUX outputs th[2:0], which makes the two data participating in the comparison have the same bit width and match. Specifically, when the threshold selection signal `voter_config` is 0, it indicates a low-noise state, and the voting threshold T = 2 is selected as the output of the 2-to-1 MUX, i.e., th[2:0] = 010B. This corresponds to a 2 / 3 voting mode, with 3 redundant paths enabled. When the threshold selection signal `voter_config` is 1, it indicates a high-noise state, and the voting threshold T = 3 is selected as the output of the 2-to-1 MUX, i.e., th[2:0] = 011B. This corresponds to a 3 / 5 voting mode, with 5 redundant paths enabled. Most voting module modules can select the voting mode (2 / 3 or 3 / 5) through the threshold selection signal `voter_config`, supporting dynamic switching of the voting threshold. This allows some redundant paths to be disabled when the noise is low, thereby reducing the dynamic power consumption caused by the flipping of some signal nodes in the adder and comparator.

[0058] Furthermore, the outputs cnt[2:0] of the adder and th[2:0] of the 2-to-1 MUX are input into a comparator for comparison. The voting rule of the comparator is as follows: when the output value cnt of the adder is greater than or equal to the selected voting threshold, the final voting signal final_out output by the comparator is 1; otherwise, the final voting signal final_out is 0. Specifically, when the threshold selection signal voter_config is 0, the voting threshold T selected by the 2-to-1 MUX is 2. If the output value cnt of the adder is ≥ 2, the final voting signal final_out is 1; otherwise, the final voting signal final_out is 0. When the threshold selection signal voter_config is 1, the voting threshold T selected by the 2-to-1 MUX is 3. If the output value cnt of the adder is ≥ 3, the final voting signal final_out is 1; otherwise, the final voting signal final_out is 0. The majority voter module performs majority decision on the redundant gate outputs through gate-level combinational logic circuits, ultimately generating one output signal as the final voting signal final_out.

[0059] It should be noted that the final voting signal `final_out` is a combinational logic output, which may have transient values ​​during the counting process, causing glitches. Such glitches may affect the stability of subsequent circuits. Glitches mainly arise because of different propagation delays between logic gates, causing brief fluctuations in the output before it stabilizes. Common methods to resolve combinational logic glitches include using synchronization registers, adding filtering circuits, or adjusting the logic design to reduce race conditions.

[0060] Therefore, it is necessary to suppress glitches in the final voting signal final_out. There are several glitch suppression schemes, namely: ① Output register: Add an output register after the voting signal output of the majority voter module. This allows the final voting signal generated by the original combinational logic to be output by a clock signal. Its advantage is that it can completely eliminate the impact of glitches on subsequent circuits, meet the synchronous design specifications, and improve timing predictability. ② Optimize the logic structure of the adder: The original logic of the adder is cnt[2:0] = in1 + in2 + in3 + in4 + in5. Such sequential addition may produce long delays. The original serial addition counting tree structure can be optimized to use a parallel counting tree structure: cnt_stage1[1:0] = in1 + in2, cnt_stage2[1:0] = in3 + in4, cnt[2:0] = cnt_stage1 + cnt_stage2 + in5. Its advantage is that it can reduce critical path delay, balance the delay of each bit, and reduce the risk of contention. ③ Glitch filtering circuit: A low-pass filter or dedicated filtering unit is added after the voting signal output of most voting modules. This glitch suppression scheme is suitable for asynchronous circuits that are not sensitive to delay.

[0061] In some embodiments, the adaptive control module is further adjusted by extending its configuration by adding a control signal input terminal to receive the control signal `mode_sel`. The threshold selection signal `voter_config` output by the adaptive control module depends only on the control signal `mode_sel`: when `mode_sel = 0`, `voter_config` is 0, and the voting threshold is set to 2; when `mode_sel = 1`, `voter_config` is 1, and the voting threshold is set to 3. The noise state `noise_state` only controls the number of redundant paths enabled: when `noise_state = 0` (low noise state), only 3 redundant paths are enabled; when `noise_state = 1` (high noise state), all 5 redundant paths are enabled. The combination of `mode_sel` and `noise_state` yields the four scenarios shown in Table 2.

[0062] Table 2: Number of redundant paths and voting thresholds under the four modes

[0063] Number of open paths Voting threshold Expected fault tolerance 3 2 1-channel error (low noise mode) 3 3 Error in 0-way (strict mode) 5 2 3-channel error (extreme interference / partial permanent failure) 5 3 2-channel error (high noise mode)

[0064] In other embodiments, the circuit is simplified by removing the adaptive control module and replacing it with a redundant path enable control signal `redundancy_en[4:0]` and a threshold selection signal `voter_config` directly controlled by an external controller. These can be flexibly configured according to the actual scenario. After removing the adaptive control module, the overall circuit area is only the size of two modules: the majority voter module and the redundant logic gate array module, representing a minimal core. However, the presence of the adaptive control module allows for real-time detection of noise levels and flexible control of redundant path activation and voting threshold switching based on these noise levels.

[0065] In summary, this invention utilizes a dynamic coordination mechanism between the number of paths and the voting threshold to improve the circuit's anti-crosstalk capability, dynamically adapt to different noise levels, enhance fault tolerance in high-noise conditions, reduce resource waste in low-noise conditions, and improve resource utilization.

[0066] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A cascaded circuit of redundant logic gates based on dynamic threshold and path coordination, characterized in that, include: The adaptive control module includes a clock signal input terminal, a reset signal input terminal, a noise sensing signal input terminal, a detection enable signal input terminal, a set of high noise threshold input terminals, a set of low noise threshold input terminals, a threshold selection signal output terminal, and five redundant path enable signal output terminals. The redundant logic gate array module includes five redundant path enable signal input terminals, five sets of redundant logic gate unit input terminals, and five redundant logic gate array output terminals; wherein, the five redundant path enable signal input terminals are respectively connected to the five redundant path enable signal output terminals of the adaptive control module. Most voting module includes a threshold selection signal input terminal, five redundant logic gate output signal input terminals, and a voting signal output terminal; wherein, the threshold selection signal input terminal is connected to the threshold selection signal output terminal of the adaptive control module, and the five redundant logic gate output signal input terminals are respectively connected to the five redundant logic gate array output terminals of the redundant logic gate array module.

2. The redundant logic gate cascade circuit based on dynamic threshold and path coordination according to claim 1, characterized in that, The redundant logic gate array module is composed of five functionally identical redundant logic gate array sub-units in parallel. Each redundant logic gate array sub-unit includes a redundant logic gate module and a redundant path enable control module. The redundant logic gate module is a gate circuit module composed of redundant logic basic units. The redundant path enable control module is composed of an AND gate. The input terminal of the redundant logic gate module is the input terminal of the redundant logic gate unit of the redundant logic gate array module. The output terminal of the redundant logic gate module is connected to one input terminal of the AND gate. The other input terminal of the AND gate is the redundant path enable signal input terminal of the redundant logic gate array module. The output terminal of the AND gate is the redundant logic gate array output terminal of the redundant logic gate array module.

3. The redundant logic gate cascade circuit based on dynamic threshold and path coordination according to claim 2, characterized in that, The redundant logic base units include combinational logic gate units and sequential logic gate units. Combinational logic gate units include AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, and XNOR gates. Sequential logic gate units include D-type flip-flops.

4. The redundant logic gate cascade circuit based on dynamic threshold and path coordination according to claim 2, characterized in that, In the redundant logic gate array module, the physical layout of the redundant logic gate modules is distributed in a dispersed manner, and the parallel wiring length of adjacent redundant paths is limited.

5. The redundant logic gate cascade circuit based on dynamic threshold and path coordination according to claim 4, characterized in that, The physical layout of the redundant logic gate module adopts a diagonal layout strategy.

6. The redundant logic gate cascade circuit based on dynamic threshold and path coordination according to claim 1, characterized in that, The adaptive control module includes a two-stage D flip-flop synchronizer, a single-stage D flip-flop, an XOR gate, a state machine, and a 2-to-1 multiplexer. The data input of the two-stage D flip-flop synchronizer serves as the noise sensing signal input of the adaptive control module. The clock inputs of the two-stage D flip-flop synchronizer, the single-stage D flip-flop, and the state machine are connected and serve as the clock signal input of the adaptive control module. The reset control terminals of the two-stage D flip-flop synchronizer, the single-stage D flip-flop, and the state machine are connected and serve as the reset signal input of the adaptive control module. The output of the two-stage D flip-flop synchronizer is connected to the data input of the single-stage D flip-flop and one input of the XOR gate. The output of the single-stage D flip-flop and the XOR gate are connected... The other input of the gate is connected, and the output of the XOR gate is connected to the noise edge input of the state machine. The detection enable signal input, high noise threshold input, and low noise threshold input of the state machine are the detection enable signal input, high noise threshold input, and low noise threshold input of the adaptive control module. The noise state output of the state machine is the threshold selection signal output of the adaptive control module. The state machine also includes a window counter and a noise counter. The noise state output of the state machine is connected to the selection control signal input of the 2-to-1 multiplexer. The two data inputs of the 2-to-1 multiplexer receive the redundant path enable control signals corresponding to the dual noise states, and the output of the 2-to-1 multiplexer is the redundant path enable signal output of the adaptive control module.

7. The redundant logic gate cascade circuit based on dynamic threshold and path coordination according to claim 1, characterized in that, The majority voter module includes an adder, a 2-to-1 multiplexer, and a comparator. The five inputs of the adder are the output signal inputs of the five redundant logic gates of the majority voter module, and the output of the adder is connected to one set of inputs of the comparator. The two data inputs of the 2-to-1 multiplexer receive voting thresholds corresponding to dual-noise states, and the selection control signal input of the 2-to-1 multiplexer is the threshold selection signal input of the majority voter module. The output of the 2-to-1 multiplexer is connected to another set of inputs of the comparator. The output of the comparator is the voting signal output of the majority voter module.

8. The redundant logic gate cascade circuit based on dynamic threshold and path coordination according to claim 1, characterized in that, The circuit also includes an output register, a low-pass filter, or a filtering unit, the input of which is connected to the voting signal output of the majority voter module.

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