An edge modulation and demodulation circuit for optically isolated transmission

Abstract

This invention belongs to the field of analog integrated circuit technology, specifically relating to an edge modulation and demodulation circuit for optically isolated transmission. It includes an SOI substrate, a waveguide layer, and a cladding layer. The SOI substrate comprises a substrate layer and a buried oxide layer. The waveguide layer comprises a lower silicon waveguide, a middle silicon dioxide spacer layer, and an upper silicon nitride waveguide. The upper silicon nitride waveguide modulates the width of the etched regions and the grating duty cycle on both sides of the central silicon nitride waveguide according to the near-field uniform emission principle, forming a fishbone-like grating antenna structure. The proposed double-layer grating structure utilizes the strong optical confinement of silicon waveguides and the weak perturbation characteristics of silicon nitride waveguides through full etching, reducing etching difficulty, effectively extending the effective length of the grating, thereby reducing the far-field emission angle of the beam, and exhibiting high wavelength tuning efficiency and high upward diffraction efficiency. The structure is simple and relatively easy to fabricate.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to an edge modulation and demodulation circuit for optically isolated transmission. Background Technology

[0002] In the field of integrated circuits, optocoupler isolation is a key technology for achieving complete electrical isolation of signal transmission paths. Optocoupler isolation typically uses LEDs and photodiodes to convert photoelectric signals. The transmitting end outputs a pulse signal to control the LED's emission frequency, and the receiving end receives the optical signal and reconstructs the pulse signal, achieving isolated signal transmission. However, because photodiodes exhibit signal falling edge tailing, directly transmitting the pulse signal leads to changes in the signal duty cycle, resulting in reduced signal transmission accuracy. Therefore, modulation and demodulation techniques are needed to improve signal transmission accuracy. Summary of the Invention

[0003] To address the aforementioned issues with the transmission accuracy of optically isolated signals, this invention proposes a modulation and demodulation circuit with a refresh function for high-precision optical isolation. The receiver detects the rising edge of the transmitter's output signal, effectively avoiding the impact of duty cycle distortion caused by the falling edge tailing of the photodiode on signal transmission accuracy. The receiver records the duration of the high-level signal received; once the duration exceeds a certain range, a refresh control signal is generated, re-enabling the receiver's output signal and reducing the impact of common-mode transient interference on signal transmission accuracy. Compared to traditional edge modulation and demodulation circuits, this invention simultaneously introduces a narrow pulse upon detecting the rising and falling edges of the signal and pulse-widens the signal corresponding to the rising edge. The receiver detects the high-level duration of the modulated signal. A sufficiently long high-level duration generates a refresh signal, reducing the impact of common-mode transient interference on signal transmission accuracy and achieving high-precision optically isolated transmission.

[0004] The technical solution of this invention is as follows:

[0005] An edge modulation and demodulation circuit with refresh function, wherein the modulation circuit is as follows: Figure 1 As shown, it includes a non-overlapping clock generation circuit and an edge modulation logic circuit; the demodulation circuit is as follows. Figure 2 As shown, it includes a first pulse broadening circuit, a second pulse broadening circuit, and a demodulation logic circuit.

[0006] The non-overlapping clock generation circuit is used to convert the clock signal into an asynchronous clock control signal, including a first inverter, an RS flip-flop, a second inverter, a third inverter, and a first NOR gate; the edge modulation logic circuit is used to detect the rising and falling edges of the input signal for edge modulation, including a first D flip-flop, a second D flip-flop, a third D flip-flop, a second NOR gate, an XOR gate, and a fourth inverter; the pulse widening circuit is used to detect the duration of the high level of the modulated signal to generate a refresh control signal, including an external voltage source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth inverter. The circuit includes four PMOS transistors, five PMOS transistors, six PMOS transistors, seven PMOS transistors, eight PMOS transistors, nine PMOS transistors, ten PMOS transistors, eleventh PMOS transistors, twelfth PMOS transistors, thirteenth PMOS transistors, one NMOS transistor, two NMOS transistors, three NMOS transistors, four NMOS transistors, five NMOS transistors, six NMOS transistors, a first resistor, a first capacitor, a third NOR gate, and a fourth inverter; the demodulation logic circuit is used to detect the rising edge of the modulated signal and restore the input signal, and includes a first T flip-flop and a second T flip-flop;

[0007] The input of the first inverter is connected to the clock signal; one input of the RS flip-flop is connected to the clock signal, and the other input is connected to the output of the first inverter; one output of the RS flip-flop is connected to the input of the second inverter, and the other output is connected to the input of the third inverter; the output of the second inverter is connected to the input of the first NOR gate and the clock input of the first D flip-flop; the output of the third inverter is connected to the other input of the first NOR gate and the clock input of the second D flip-flop; the output of the first NOR gate is connected to the clock input of the third D flip-flop.

[0008] The input pulse signal is connected to the signal input terminals of the first D flip-flop, the second D flip-flop, and the second NOR gate; the inverted output terminal of the first D flip-flop is connected to the other input terminal of the second NOR gate; the non-inverted output terminal of the second D flip-flop is connected to the input terminal of the XOR gate, and the output terminal of the second NOR gate is connected to the other input terminal of the XOR gate; the output terminal of the XOR gate is connected to the signal input terminal of the third D flip-flop; the non-inverted output terminal of the third D flip-flop is connected to the input terminal of the fourth inverter; the output of the fourth inverter outputs an edge-modulated signal that enters the optocoupler isolator.

[0009] The source of the first PMOS is connected to VDD potential, the gate of the first PMOS is connected to the gate of the second PMOS, and the drain of the first PMOS is connected to the source of the second PMOS; the gate and drain of the second PMOS are shorted and connected to the drain of the first NMOS; the source of the third PMOS is connected to VDD potential, the gate of the third PMOS is connected to the drain of the fourth PMOS and the gate of the fifth PMOS, and the drain of the third PMOS is connected to the source of the fourth PMOS; the gate of the fourth PMOS is connected to the gate of the second PMOS, and the drain of the fourth PMOS is connected to the drain of the second NMOS;

[0010] The source of the fifth PMOS is connected to the VDD potential, the gate of the fifth PMOS is connected to the gate of the third PMOS, and the drain of the fifth PMOS is connected to the source of the sixth PMOS; the gate of the sixth PMOS is connected to the gate of the fourth PMOS, and the drain of the sixth PMOS is connected to the drain of the third NMOS and the gate of the fourth NMOS.

[0011] The source of the seventh PMOS is connected to VDD potential, the gate of the seventh PMOS is connected to the drain of the eighth PMOS and the gate of the ninth PMOS, and the drain of the seventh PMOS is connected to the source of the eighth PMOS; the gate of the eighth PMOS is connected to the gate of the sixth PMOS, and the drain of the eighth PMOS is connected to the drain of the fourth NMOS; the source of the ninth PMOS is connected to VDD potential, and the drain of the ninth PMOS is connected to the source of the tenth PMOS; the gate of the tenth PMOS is connected to the gate of the eighth PMOS, and the drain of the tenth PMOS is connected to the drain of the fifth NMOS, one end of the first capacitor, and the gate of the sixth NMOS;

[0012] The source of the eleventh PMOS is connected to VDD potential, the gate of the eleventh PMOS is connected to the gate of the fifth PMOS, and the drain of the eleventh PMOS is connected to the source of the twelfth PMOS; the gate of the twelfth PMOS is connected to the gate of the tenth PMOS, and the drain of the twelfth PMOS is connected to the drain of the sixth NMOS; the source of the thirteenth PMOS is connected to VDD potential, the gate of the thirteenth PMOS is connected to an optocoupler to isolate the output of an inverted signal, and the drain of the thirteenth PMOS is connected to the drain of the sixth NMOS.

[0013] The gate of the first NMOS is connected to a voltage source, and the source of the first NMOS is connected to GND. The gate of the second NMOS is connected to a voltage source, and the source of the second NMOS is connected to GND. The gate of the third NMOS is connected to one end of the first resistor and the source of the fourth NMOS, and the source of the third NMOS is connected to GND. The gate of the fourth NMOS is connected to the drain of the third NMOS. The other end of the first resistor is connected to GND. The gate of the fifth NMOS is connected to an optocoupler to isolate the output of a positive phase signal, and the source of the fifth NMOS is connected to GND. One end of the first capacitor is connected to the drain of the fifth NMOS and the gate of the sixth NMOS, and the other end of the first capacitor is connected to GND. The source of the sixth NMOS is connected to GND.

[0014] One end of the third NOR gate is connected to the drain of the sixth NMOS transistor, and the other end is connected to an optocoupler to output a positive inverted signal. The output of the third NOR gate is connected to the fourth inverter. The output of the fourth inverter is the output of a pulse stretching circuit.

[0015] The output of the first pulse widening circuit is connected to the RST terminal of the first T flip-flop and the NRST terminal of the second T flip-flop; the output of the second pulse widening circuit is connected to the RST terminal of the second T flip-flop and the NRST terminal of the first T flip-flop; the positive output of the optocoupler isolator is connected to the CLK terminal of the first T flip-flop and the second T flip-flop; the output of the first T flip-flop is the demodulated positive phase signal; the output of the second T flip-flop is the demodulated inverted phase signal.

[0016] The beneficial effects of this invention are as follows: This invention proposes a refresh function edge modulation and demodulation circuit, which detects the rising edge of the signal at the receiving end to restore the input pulse signal, effectively avoiding the impact of the falling edge tailing problem of the photodiode on the transmission accuracy. At the same time, the refresh function reduces the impact of common-mode transient events on signal accuracy, and can realize high-precision transmission of optically isolated signals. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the edge modulation and demodulation optical coupling isolation system proposed in this invention.

[0018] Figure 2 This is a schematic diagram of the logic circuit for the edge modulation and demodulation circuit proposed in this invention.

[0019] Figure 3 This is a schematic diagram of the pulse broadening circuit proposed in this invention.

[0020] Figure 4 The simulated waveforms of key signals in the edge modulation and demodulation circuit proposed in this invention are shown. Detailed Implementation

[0021] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0022] Figure 1 The diagram shows the edge modulation and demodulation optical coupler isolation system of the present invention, which includes a modulation circuit, an optical coupler isolator, and a demodulation circuit. The modulation circuit includes a non-overlapping clock generation circuit and an edge modulation logic circuit. The demodulation circuit includes a demodulation logic circuit and a pulse widening circuit.

[0023] Figure 2 This is a schematic diagram of the edge modulation and demodulation circuit logic circuit of the present invention. It includes three parts, which are respectively connected to... Figure 1 Correspondingly, circuit 10 is a non-overlapping clock generation circuit, circuit 20 is an edge-modulated logic circuit, and circuit 30 is a demodulation logic circuit.

[0024] In the non-overlapping clock generation circuit 10, the input CLK signal is the clock control signal generated by frequency division of the oscillator output, corresponding to the narrowest pulse width in the Signal_in signal in this design. The CLK signal is connected to one input of the RS flip-flop, passes through the first inverter, and then is connected to the other input of the RS flip-flop. The truth table of the RS flip-flop is: when the input CLK is 0, the output CLK1 is 0 and CLK2 is 1; when the input CLK is 1, the output CLK1 is 1 and CLK is 0. Due to the delay of the signal after passing through INV1, when the CLK signal flips, there is a state where the output CLK1 and CLK2 are both 0, ensuring the non-overlapping state of the logic circuit control signals CLK1 and CLK2 and preventing logic errors. CLK1 and CLK2 are passed through the NOR gate NOR1 to generate CLK3, which is used to adjust the non-overlapping part of the control signal and improve signal accuracy.

[0025] In the edge-modulation logic circuit 20, CLK1 is the clock control signal for the first D flip-flop D1, CLK2 is the clock control signal for the second D flip-flop, and CLK3 is the clock control signal for the third D flip-flop. After the input pulse signal passes through the D1 flip-flop, the Q' output is ORed with the input pulse signal. Since the signal is delayed by one clock cycle after passing through the D flip-flop, the OR operation generates a narrow pulse of half a clock cycle at the signal change edge. After the input pulse signal passes through the D2 flip-flop, the Q output and the NOR2 output signal enter an XOR gate. The XOR gate output rises on the rising edge of the pulse signal, falls half a clock cycle before the falling edge, and inserts a narrow pulse of half a clock cycle at the original falling edge position. The XOR1 output is used to adjust the non-overlapping portion of the CLK1 and CLK2 signals after passing through the D3 flip-flop. This process achieves edge modulation and pulse widening of the high-level signal. The output signal is converted into an output V by the inverter INV2. A Enter the optocoupler isolator.

[0026] In the demodulation logic circuit 30, the optocoupler output V A The signal serves as the input signal for the demodulation logic circuit. V A The signal serves as the clock control input for T1 and T2 of the T flip-flops, while V... A The signal is used as the input to the pulse widening circuit 50, V A The signal passes through inverter INV3 as the input to pulse widening circuit 40. The output of pulse widening circuit 40 is connected to the RST control terminal of T flip-flop T1 and the NRST control terminal of T flip-flop T2. The output of pulse widening circuit 50 is connected to the NRST control terminal of T flip-flop T1 and the RST control terminal of T flip-flop T2. Pulse widening circuit 50 detects V. AThe high-level signal duration exceeds a set threshold; when this duration exceeds the threshold, the output signal toggles, disabling the T flip-flop and refreshing the output pulse. The pulse widening circuit 40 detects V. A The low-level signal duration exceeds a set threshold; when this duration exceeds the threshold, the output signal toggles, disabling the T flip-flop and refreshing the output pulse. T flip-flops T1 and T2 detect V... A The rising edge of the signal flips, completing the demodulation of the edge-modulated signal and outputting a differential pulse signal.

[0027] Figure 3 The diagram shows the pulse broadening circuit schematic of this invention. The left side forms a common-source, common-gate current mirror structure. The reference voltage Vbias, through the current mirror formed by M1 and M2, provides a stable static bias current to the circuit, ensuring the transistor operates in the saturation region. M15 gate voltage V... gs5 A reference current (V) is generated in resistor R. gs5 The current ( / R) is converted into capacitor charging current through a common-source cascode current mirror. The dynamic working mechanism of the circuit is as follows: When IN is low, M16 and M13 are cut off, and the reference current charges the capacitor through a fixed path. After a charging delay (determined by the RC time constant), M17 turns on, pulling node A low, and the OUT output is low, consistent with IN, achieving logic synchronization; when IN is high, transistors M16 and M13 turn on, the gate voltage of M17 is clamped to low, and the voltage of node A rises quickly to high through the pull-up path, driving the OUT port to output a high-level signal.

[0028] Figure 4 The key signal waveforms in the signal chain path of this invention are shown. Signal_IN represents the input pulse signal waveform, and signal A represents the modulated signal waveform after edge modulation. Signal A is delayed relative to Signal_IN by a certain time, and a narrow pulse is inserted at the falling edge of Signal_IN to effectively avoid duty cycle distortion caused by the falling edge tail of the photodiode, which affects the transmission accuracy. The Glitch spike in signal A indicates a non-ideal spike in the signal due to common-mode transient events. Signal B is the output signal of the pulse widening circuit 40. The pulse widening circuit 40 detects the duration of the low level of signal A. When the duration of the low level of signal A exceeds a set threshold, signal B flips to a low signal, the T flip-flop is disabled, and the output signal is refreshed. Signal C is the output signal of the demodulation logic circuit. The T flip-flop detects the rising edge of signal A and causes signal C to flip. The Error segment indicates the signal error segment caused by the influence of Glitch spikes. Compared with the last row of unrefreshed Error segments, it can be seen that the refresh function reduces the error time of the Glitch signal on the output signal and improves the signal transmission accuracy.

Claims

1. An edge modulation and demodulation circuit for optically isolated transmission, characterized in that, It includes a non-overlapping clock generation circuit, an edge modulation circuit, a first pulse widening circuit, a second pulse widening circuit, and a demodulation circuit; The non-overlapping clock generation circuit is used to convert the clock signal into an asynchronous clock control signal, and includes a first inverter, an RS flip-flop, a second inverter, a third inverter, and a first NOR gate; The edge modulation circuit is used to detect the rising and falling edges of the input signal and perform edge modulation, including a first D flip-flop, a second D flip-flop, a third D flip-flop, a second NOR gate, an XOR gate, and a fourth inverter; The pulse widening circuit is used to detect the duration of the high level of the modulated signal and generate a refresh control signal. It includes an external voltage source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first resistor, a first capacitor, a third NOR gate, and a fourth inverter. The demodulation circuit is used to detect the rising edge of the modulated signal and restore the input signal, and includes a first T flip-flop and a second T flip-flop. The input to the first inverter is connected to the clock signal; One input of the RS flip-flop is connected to a clock signal, and the other input is connected to the output of the first inverter; one output of the RS flip-flop is connected to the input of the second inverter, and the other output is connected to the input of the third inverter; the output of the second inverter is connected to the input of the first NOR gate and the clock input of the first D flip-flop; the output of the third inverter is connected to the other input of the first NOR gate and the clock input of the second D flip-flop; the output of the first NOR gate is connected to the clock input of the third D flip-flop. The input pulse signal is connected to the signal input terminals of the first D flip-flop, the second D flip-flop, and the second NOR gate; the inverted output terminal of the first D flip-flop is connected to the other input terminal of the second NOR gate; the non-inverted output terminal of the second D flip-flop is connected to the input terminal of the XOR gate, and the output terminal of the second NOR gate is connected to the other input terminal of the XOR gate; the output terminal of the XOR gate is connected to the signal input terminal of the third D flip-flop; the non-inverted output terminal of the third D flip-flop is connected to the input terminal of the fourth inverter; the output of the fourth inverter outputs an edge-modulated signal that enters the optocoupler isolator. The source of the first PMOS is connected to the VDD potential, the gate of the first PMOS is connected to the gate of the second PMOS, and the drain of the first PMOS is connected to the source of the second PMOS. The gate and drain of the second PMOS are shorted together and connected to the drain of the first NMOS. The source of the third PMOS is connected to the VDD potential, the gate of the third PMOS is connected to the drain of the fourth PMOS and the gate of the fifth PMOS, the drain of the third PMOS is connected to the source of the fourth PMOS; the gate of the fourth PMOS is connected to the gate of the second PMOS, and the drain of the fourth PMOS is connected to the drain of the second NMOS. The source of the fifth PMOS is connected to the VDD potential, the gate of the fifth PMOS is connected to the gate of the third PMOS, and the drain of the fifth PMOS is connected to the source of the sixth PMOS. The gate of the sixth PMOS is connected to the gate of the fourth PMOS, and the drain of the sixth PMOS is connected to the drain of the third NMOS and the gate of the fourth NMOS. The source of the seventh PMOS is connected to the VDD potential, the gate of the seventh PMOS is connected to the drain of the eighth PMOS and the gate of the ninth PMOS, and the drain of the seventh PMOS is connected to the source of the eighth PMOS. The gate of the eighth PMOS is connected to the gate of the sixth PMOS, and the drain of the eighth PMOS is connected to the drain of the fourth NMOS. The source of the ninth PMOS is connected to the VDD potential, and the drain of the ninth PMOS is connected to the source of the tenth PMOS. The gate of the tenth PMOS is connected to the gate of the eighth PMOS, and the drain of the tenth PMOS is connected to the drain of the fifth NMOS, one end of the first capacitor, and the gate of the sixth NMOS. The source of the eleventh PMOS is connected to VDD potential, the gate of the eleventh PMOS is connected to the gate of the fifth PMOS, and the drain of the eleventh PMOS is connected to the source of the twelfth PMOS; the gate of the twelfth PMOS is connected to the gate of the tenth PMOS, and the drain of the twelfth PMOS is connected to the drain of the sixth NMOS; the source of the thirteenth PMOS is connected to VDD potential, the gate of the thirteenth PMOS is connected to an optocoupler to isolate the output of an inverted signal, and the drain of the thirteenth PMOS is connected to the drain of the sixth NMOS. The gate of the first NMOS is connected to a voltage source, and the source of the first NMOS is connected to the GND potential. The gate of the second NMOS is connected to a voltage source, and the source of the second NMOS is connected to the GND potential. The gate of the third NMOS is connected to one end of the first resistor and the source of the fourth NMOS, and the source of the third NMOS is connected to the GND potential. The gate of the fourth NMOS is connected to the drain of the third NMOS; the other end of the first resistor is connected to the GND potential. The gate of the fifth NMOS is connected to an optocoupler to isolate the output of a positive-phase signal, and the source of the fifth NMOS is connected to the GND potential; one end of the first capacitor is connected to the drain of the fifth NMOS and the gate of the sixth NMOS, and the other end of the first capacitor is connected to the GND potential. The source of the sixth NMOS is connected to GND potential; One end of the third NOR gate is connected to the drain of the sixth NMOS, and the other end is connected to an optocoupler to output a positive inverted signal. The output of the third NOR gate is connected to the fourth inverter. The output of the fourth inverter is the output of the pulse widening circuit; The output of the first pulse widening circuit is connected to the RST terminal of the first T flip-flop and the NRST terminal of the second T flip-flop. The output of the second pulse widening circuit is connected to the RST terminal of the second T flip-flop and the NRST terminal of the first T flip-flop; the positive output of the optocoupler isolator is connected to the CLK terminal of the first T flip-flop and the second T flip-flop. The output of the first T flip-flop is a demodulated positive phase signal; The output of the second T flip-flop is a demodulated inverted signal.

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