A high aspect ratio hard mask removal method

By filling the trenches of the hard mask structure with BARC and adjusting the etching ratio, the hard mask structure is thinned, which solves the problem of acid damage to the gate oxide structure in wet etching and achieves effective removal of the hard mask.

CN117711920BActive Publication Date: 2026-06-09HUA HONG SEMICON WUXI LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HUA HONG SEMICON WUXI LTD
Filing Date
2023-11-27
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

In existing technologies, wet etching can lead to the thinning of the hard mask, causing acid to damage the gate oxide structure.

Method used

BARC is filled into the trenches of the hard mask structure, and the selectivity ratio of the hard mask structure and BARC is adjusted by etching to make it thinner to 1 μm or less. Then the BARC and hard mask structure are removed.

Benefits of technology

It reduces wet etching time, prevents acid from entering the trenches of the gate oxide structure, and prevents the gate oxide structure from being damaged.

✦ Generated by Eureka AI based on patent content.

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  • Figure CN117711920B_ABST
    Figure CN117711920B_ABST
Patent Text Reader

Abstract

The application provides a high-depth-width-ratio hard mask removing method, which comprises the following steps: providing a first semiconductor structure, the first semiconductor structure comprising a second semiconductor structure and two hard mask structures which are spaced apart from each other on the second semiconductor structure; forming a groove between the two hard mask structures; filling BARC in the groove between the two hard mask structures; etching the two hard mask structures and the BARC at a constant ratio until the height of the two hard mask structures is 1 μm or below; removing the remaining BARC; and removing the remaining two hard mask structures. The BARC is filled in the groove of the hard mask structure, the selectivity of the hard mask structure and the BARC is adjusted by etching, the hard mask structure is thinned to 1 μm or below, and the hard mask structure is removed after the BARC is removed. Since the hard mask structure is thinned, the time of wet etching is reduced, the acid solution does not have enough time to enter the groove of the gate oxide structure, and the gate oxide structure will not be damaged.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for removing high aspect ratio hard masks. Background Technology

[0002] LV_SJ forms P-pillars through multiple high-energy IMP processes. DS simulation results show that 3400K energy requires a 5.6µm HM (high-density metal) barrier. Furthermore, the thickness of the Pre-PPL IMP Film directly affects the subsequent IMP implantation depth, thus directly impacting the device's gate oxide (BV). To ensure the BV reaches the target value, the thickness before pre-IMP implantation needs to be around 500-600µm (SiN 200-300µm). However, during the subsequent wet removal of the HM via TEOS, a series of problems were encountered, including insufficient remaining SiN due to the long process time, or the acid having enough time to enter the trench from the dicing channel, damaging the gate oxide structure in the trench. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high aspect ratio hard mask removal method to solve the problem that the thinning of the hard mask during wet etching in the prior art leads to acid damage to the gate oxide structure.

[0004] To achieve the above and other related objectives, the present invention provides a method for removing high aspect ratio hard masks.

[0005] Step 1: Provide a first semiconductor structure, the first semiconductor structure including a second semiconductor structure and two hard mask structures spaced apart on the second semiconductor structure; a trench is formed between the two hard mask structures;

[0006] Step 2: Fill the trench between the two hard mask structures with BARC;

[0007] Step 3: Etch the two hard mask structures and the BARC in the same proportion until the two hard mask structures are retained to a height of 1 μm or less;

[0008] Step 4: Remove the remaining BARC;

[0009] Step 5: Remove the remaining two hard mask structures.

[0010] Preferably, the two hard mask structures in step one are TEOS structures.

[0011] Preferably, the two hard mask structures in step one are structures formed after etching the PPL hard mask layer.

[0012] Preferably, the two hard mask structures in step one are high-depth-wide structures.

[0013] Preferably, the second semiconductor structure in step one includes a gate oxide structure covered by the two hard mask structures respectively, and a SiN layer covering the gate oxide structure.

[0014] Preferably, the gate oxide structure in step one is a gate oxide layer located on the inner wall of the trench of the second semiconductor structure.

[0015] Preferably, in step three, the height of the two hard mask structures is kept to be greater than 0.

[0016] Preferably, the etching method for the two hard mask structures and the BARC in step three is dry etching and wet etching.

[0017] As described above, the high aspect ratio hard mask removal method of the present invention has the following beneficial effects: The present invention fills the trenches of the hard mask structure with BARC (Browser Arc Removal), and adjusts the selectivity ratio of the hard mask structure and BARC through etching to thin it to 1µm or less. The BARC is removed before removing the hard mask structure. Because the hard mask structure is thinner, the wet etching time is reduced, and the acid does not have enough time to enter the trenches of the gate oxide structure, thus preventing damage to the gate oxide structure. Attached Figure Description

[0018] Figures 1 to 6 The diagram shows the structural schematics of each step in the high aspect ratio hard mask removal method of the present invention.

[0019] Figure 7 The diagram shown is a flowchart of the high aspect ratio hard mask removal method of the present invention. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] This invention provides a method for removing high aspect ratio hard masks, such as... Figure 7 As shown, Figure 7The flowchart shown is a high aspect ratio hard mask removal method of the present invention, which includes at least the following:

[0023] Step 1: Provide a first semiconductor structure, the first semiconductor structure including a second semiconductor structure and two hard mask structures spaced apart on the second semiconductor structure; a trench is formed between the two hard mask structures;

[0024] Furthermore, in this embodiment, the two hard mask structures mentioned in step one are TEOS structures.

[0025] Furthermore, in this embodiment, the two hard mask structures mentioned in step one are structures formed after etching the PPL hard mask layer.

[0026] Furthermore, in this embodiment, the two hard mask structures in step one are high-depth-wide structures.

[0027] Furthermore, in step one of this embodiment, the second semiconductor structure includes a gate oxide structure covered by the two hard mask structures and a SiN layer covering the gate oxide structure.

[0028] In a further embodiment of the present invention, the gate oxide structure in step one is a gate oxide layer located on the inner wall of the trench of the second semiconductor structure.

[0029] like Figure 1 As shown, step one provides a first semiconductor structure, which includes a second semiconductor structure 01 and two hard mask structures 04 spaced apart on the second semiconductor structure 01; a trench 06 is formed between the two hard mask structures 04; further, in this embodiment, the two hard mask structures 04 are TEOS structures. The two hard mask structures 04 are structures formed after etching a PPL hard mask layer. The two hard mask structures 04 are high-depth-wide-side structures. The second semiconductor structure includes a gate oxide structure 02 covered by the two hard mask structures 04 respectively, and a SiN layer covering the gate oxide structure 02. The gate oxide structure 02 is a gate oxide layer located on the inner wall of the trench of the second semiconductor structure 01. Figure 1 The two hard mask structures 04 described above also have photoresist 05 remaining after etching. Figure 2 for Figure 1 The structure after removing the photoresist.

[0030] Step 2: Fill the trench between the two hard mask structures with BARC; as shown Figure 3 As shown, in step two, BARC(07) is filled into the trench 06 between the two hard mask structures 04.

[0031] Step 3: Etch the two hard mask structures and the BARC in the same proportion until the two hard mask structures are retained to a height of 1 μm or less;

[0032] Furthermore, in step three of this embodiment, the height of the two hard mask structures is kept to be greater than 0.

[0033] Furthermore, in step three of this embodiment, the etching methods for the two hard mask structures and the BARC are dry etching and wet etching.

[0034] like Figure 4 As shown, step three involves etching the two hard mask structures and the BARC in a proportional manner until the height of the two hard mask structures is 1 μm or less. In other words, the selection ratio of the two hard mask structures and the BARC is adjusted so that they are etched proportionally, retaining a height of the two hard mask structures 04 that is greater than 0 and less than or equal to 1 μm. The etching methods for proportionally etching the two hard mask structures 04 and the BARC are dry etching and wet etching.

[0035] Step 4: Remove the remaining BARC; as Figure 5 As shown, step four removes the remaining BARC, forming Figure 5 The structure shown.

[0036] Step 5: Remove the remaining two hard mask structures. (As shown) Figure 6 As shown, step five removes the remaining two hard mask structures to form... Figure 6 The structure shown is as follows. Because the TEOS is thinned in step four, the wet etching time is reduced, and the acid does not have enough time to enter the trenches of the gate oxide structure, so the gate oxide structure is not destroyed.

[0037] In summary, this invention involves filling the trenches of a hard mask structure with bar arc resonators (BARCs). By adjusting the selectivity ratio of the hard mask structure to the BARCs through etching, the hard mask structure is thinned to 1µm or less. The BARCs are then removed before removing the hard mask structure. Because the hard mask structure is thinner, the wet etching time is reduced, and the acid does not have sufficient time to penetrate the trenches of the gate oxide structure, thus preventing damage to the gate oxide structure. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0038] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for removing high aspect ratio hard masks, characterized in that, At least including: Step 1: Provide a first semiconductor structure, the first semiconductor structure including a second semiconductor structure and two hard mask structures spaced apart on the second semiconductor structure; a trench is formed between the two hard mask structures; Step 2: Fill the trench between the two hard mask structures with BARC; Step 3: Etch the two hard mask structures and the BARC in the same proportion until the two hard mask structures are retained to a height of 1 μm or less; Step 4: Remove the remaining BARC; Step 5: Remove the remaining two hard mask structures.

2. The high aspect ratio hard mask removal method according to claim 1, characterized in that: The two hard mask structures mentioned in step one are TEOS structures.

3. The high aspect ratio hard mask removal method according to claim 1, characterized in that: The two hard mask structures mentioned in step one are structures formed after etching the PPL hard mask layer.

4. The high aspect ratio hard mask removal method according to claim 1, characterized in that: The two hard mask structures mentioned in step one are high-depth-wide structures.

5. The high aspect ratio hard mask removal method according to claim 1, characterized in that: The second semiconductor structure in step one includes a gate oxide structure covered by the two hard mask structures respectively, and a SiN layer covering the gate oxide structure.

6. The high aspect ratio hard mask removal method according to claim 5, characterized in that: The gate oxide structure in step one is the gate oxide layer located on the inner wall of the trench of the second semiconductor structure.

7. The high aspect ratio hard mask removal method according to claim 1, characterized in that: In step three, the height of the two hard mask structures is kept to be greater than 0.

8. The high aspect ratio hard mask removal method according to claim 1, characterized in that: In step three, the etching methods for the two hard mask structures and the BARC are dry etching and wet etching.