A communication circuit, a semiconductor integrated circuit, a system on chip, and an electronic device

Abstract

The application provides a communication circuit, a semiconductor integrated circuit, a system on chip and an electronic device, which are applied to the technical field of computers, and the circuit comprises a first selection circuit and a second selection circuit. The first selection circuit is connected with a first end of a signal TSV and a redundant TSV respectively, the second selection circuit is connected with a second end of the signal TSV and the redundant TSV respectively, the first selection circuit and the second selection circuit transmit a configuration signal for switching a communication signal transmission path through the signal TSV, in the case that the signal TSV is normal, the first selection circuit and the second selection circuit transmit a communication signal through the signal TSV, in the case that the signal TSV is abnormal, the first selection circuit and the second selection circuit transmit a communication signal through the redundant TSV, the circuit can realize self-detection of the state of the signal TSV, switch the signal TSV and the redundant TSV automatically, can omit a feedback TSV, and effectively reduces TSV cost.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a connecting circuit, integrated circuit, system-on-a-chip, and electronic device. Background Technology

[0002] With the advent of the post-Moore's Law era, 3D chip technology has become one of the important directions for further improving chip performance. By integrating multiple dies inside the chip and interconnecting them through TSV (Through Silicon Via) communication, the chip becomes a whole, thereby achieving more powerful functions.

[0003] 3D chips contain a large number of TSVs (Transmission Signal Vessels). In practical applications, it is inevitable that some TSVs will fail. To solve this problem, existing technologies, in addition to setting up signal TSVs for transmitting communication signals, also set up redundant backup TSVs in the chip. When a signal TSV fails, it can be replaced by a redundant TSV, thereby reducing the impact of the failed TSV on the overall performance of the chip.

[0004] However, in order to detect the status of the signal TSV and switch the redundant TSV in time when the signal TSV is abnormal, a feedback TSV must be integrated into the chip to feed back the detection result of the signal TSV. The decision to switch the redundant TSV is based on the detection result fed back by the feedback TSV. Obviously, the existing technology increases the overhead of the TSV and increases the overall manufacturing cost of the 3D chip. Summary of the Invention

[0005] In view of this, this application aims to provide a connectivity circuit, semiconductor integrated circuit, system-on-a-chip, and electronic device to solve the problems of high TSV overhead and high overall chip manufacturing cost in the prior art.

[0006] In a first aspect, this application provides a connectivity circuit applied to a semiconductor integrated circuit, the semiconductor integrated circuit including a signal TSV and redundant TSVs, the connectivity circuit including: a first selection circuit and a second selection circuit, wherein...

[0007] The first selection circuit is connected to the first terminal of the signal TSV and the redundant TSV, respectively.

[0008] The second selection circuit is connected to the second terminals of the signal TSV and the redundant TSV, respectively;

[0009] The first selection circuit and the second selection circuit transmit a configuration signal for switching the communication signal transmission path via the signal TSV.

[0010] When the TSV signal is normal, the first selection circuit and the second selection circuit transmit communication signals through the TSV signal in response to the configuration signal.

[0011] In the event of an abnormal TSV signal, the first selection circuit and the second selection circuit transmit communication signals via redundant TSVs.

[0012] In one optional implementation, the first selection circuit includes an input control circuit and an input selection circuit, and the second selection circuit includes an output control circuit and an output selection circuit, wherein...

[0013] The input control circuit is connected to the output control circuit via the signal TSV;

[0014] The input selection circuit is connected to the first terminal of the signal TSV and the redundant TSV, respectively.

[0015] The output selection circuit is connected to the second terminal of the signal TSV and the redundant TSV, respectively.

[0016] When the signal TSV is normal, the input control circuit responds to the configuration signal to control the input selection circuit to connect with the signal TSV, and the output control circuit responds to the configuration signal to control the output selection circuit to connect with the signal TSV.

[0017] In the event of an abnormal TSV signal, the input control circuit controls the input selection circuit to connect with the redundant TSV, and the output control circuit controls the output selection circuit to connect with the redundant TSV.

[0018] In one optional implementation, the configuration signal includes a first reset signal, a first test signal, a second reset signal, and a second test signal configured sequentially.

[0019] When the TSV signal is normal, the process by which the first selection circuit and the second selection circuit respond to the configuration signal includes:

[0020] The input control circuit responds to the first reset signal by controlling the input selection circuit to connect with the redundant TSV.

[0021] In response to the first test signal, the output control circuit controls the output selection circuit to connect with the signal TSV, and provides the first test signal to the input control circuit through the signal TSV.

[0022] The input control circuit responds to the first test signal and controls the input selection circuit to connect with the signal TSV.

[0023] The output control circuit responds to the second reset signal by controlling the output selection circuit to connect with the redundant TSV.

[0024] The input selection circuit receives the second test signal and provides the second test signal to the output control circuit through the signal TSV;

[0025] The output control circuit responds to the second test signal and controls the output selection circuit to connect with the signal TSV.

[0026] In one alternative implementation, the process by which the first selection circuit and the second selection circuit respond to the configuration signal in the event of an abnormal TSV signal includes:

[0027] The input control circuit responds to the first reset signal by controlling the input selection circuit to connect with the redundant TSV.

[0028] The output control circuit responds to the first test signal and controls the output selection circuit to connect with the signal TSV.

[0029] The output control circuit responds to the second reset signal by controlling the output selection circuit to connect with the redundant TSV.

[0030] The input selection circuit receives the second test signal and provides the second test signal to the output selection circuit through redundant TSV.

[0031] In one optional implementation, the configuration signal includes a first reset signal, a first test signal, a second reset signal, and a second test signal configured sequentially.

[0032] The input control circuit includes: a first OR gate, wherein...

[0033] The first OR gate is provided with a first input terminal, a second input terminal, and an output terminal, wherein,

[0034] The first input terminal of the first OR gate is used to receive the first reset signal;

[0035] The output terminal of the first OR gate is connected to the first input terminal of the first OR gate and the control terminal of the input selection circuit, respectively.

[0036] The second input terminal of the first OR gate is connected to the first terminal of the signal TSV.

[0037] The input selection circuit includes: a first multiplexer, wherein,

[0038] The first multiplexer is provided with a first output terminal, a second output terminal, an input terminal, and a control terminal, wherein,

[0039] The first output terminal of the first multiplexer is connected to the signal TSV, and the second output terminal of the first multiplexer is connected to the first terminal of the redundant TSV.

[0040] The input of the first multiplexer is used to receive the second test signal;

[0041] The control terminal of the first multiplexer serves as the control terminal of the input selection circuit.

[0042] In one optional implementation, the configuration signal further includes a first strobe signal and a second strobe signal;

[0043] The input selection circuit further includes: a second multiplexer, wherein...

[0044] The second multiplexer is provided with a first input terminal, a second input terminal, an output terminal, and a control terminal, wherein,

[0045] The first input terminal of the second multiplexer is used to receive a communication signal, and the second input terminal of the second multiplexer is used to receive the second test signal;

[0046] The output of the second multiplexer is connected to the input of the first multiplexer;

[0047] The control terminal of the second multiplexer is used to receive either the first strobe signal or the second strobe signal;

[0048] The second multiplexer responds to the first strobe signal by connecting its second input and output terminals, or responds to the second strobe signal by connecting its first input and output terminals.

[0049] In one optional implementation, the input control circuit further includes: a first diode, wherein,

[0050] The anode of the first diode is used to receive the first reset signal, and the cathode of the first diode is connected to the first input terminal of the first OR gate.

[0051] The input selection circuit further includes a second diode, wherein...

[0052] The anode of the second diode is connected to the first output terminal of the first multiplexer, and the cathode of the second diode is connected to the first terminal of the signal TSV.

[0053] In one optional implementation, the configuration signal includes a first reset signal, a first test signal, a second reset signal, and a second test signal configured sequentially.

[0054] The output control circuit includes: a second OR gate, wherein,

[0055] The second OR gate is provided with a first input terminal, a second input terminal, and an output terminal, wherein,

[0056] The first input of the second OR gate is used to receive the second reset signal;

[0057] The second input terminal of the second OR gate is connected to the second terminal of the signal TSV and is used to receive the first test signal;

[0058] The output terminal of the second OR gate is connected to the first input terminal of the second OR gate and the control terminal of the output selection circuit, respectively.

[0059] The output selection circuit includes: a third multiplexer, wherein,

[0060] The third multiplexer is provided with a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein,

[0061] The first input terminal of the third multiplexer is connected to the second terminal of the signal TSV, and the second input terminal of the third multiplexer is connected to the second terminal of the redundant TSV.

[0062] The output of the third multiplexer is used to transmit communication signals;

[0063] The control terminal of the third multiplexer serves as the control terminal of the output selection circuit.

[0064] In one optional implementation, the output control circuit further includes: a third diode and a fourth diode, wherein,

[0065] The anode of the third diode is used to receive the first test signal, and the cathode of the third diode is connected to the second terminal of the signal TSV.

[0066] The anode of the fourth diode is used to receive the second reset signal, and the cathode of the fourth diode is connected to the first input terminal of the second OR gate.

[0067] In one alternative implementation, the connectivity circuit provided in the first aspect of this application further includes a controller for providing the configuration signal.

[0068] Secondly, this application provides a semiconductor integrated circuit, comprising: at least two dies and at least one interconnect circuit as described in any one of the first aspects of this application, wherein...

[0069] The bare wafers are stacked sequentially in the vertical direction;

[0070] The first die and the second die are connected by a signal TSV and a redundant TSV, wherein the first die is any one of the at least two dies, and the second die is the die adjacent to the first die;

[0071] The first selection circuit in the connected circuit is disposed on the first bare die;

[0072] The second selection circuit in the connected circuit is configured with the second die.

[0073] In one alternative implementation, the signal TSVs and redundant TSVs between the first die and the second die are divided into at least one TSV cluster;

[0074] The TSV cluster includes at least one signal TSV and one redundant TSV, and each signal TSV is configured with one of the connected circuits.

[0075] In one alternative implementation, within the same TSV cluster, each signal TSV and redundant TSV are equidistant in the horizontal direction.

[0076] In one alternative implementation, within the same TSV cluster, each signal TSV is evenly distributed around redundant TSVs.

[0077] In one alternative implementation, within the same TSV cluster, the timing path distance between any connected circuit and a redundant TSV is equal to the timing path distance between the connected circuit and the corresponding signal TSV.

[0078] In one optional embodiment, the semiconductor integrated circuit provided in the second aspect of this application further includes at least one alarm circuit, wherein,

[0079] Each of the TSV clusters is configured with one of the alarm circuits;

[0080] The alarm circuit is used to detect the status of each signal TSV in the corresponding TSV cluster.

[0081] In one alternative implementation, the TSV cluster includes two or more signal TSVs;

[0082] The alarm circuit outputs an alarm signal when at least two TSV signals are abnormal.

[0083] In one optional implementation, the first selection circuit includes an input control circuit and an input selection circuit, wherein the input control circuit outputs a first strobe signal to the input selection circuit when the connected signal TSV is abnormal.

[0084] The alarm circuits are respectively connected to the input control circuits of each connected circuit within the same TSV cluster;

[0085] The alarm circuit outputs the alarm signal when it detects at least two of the first strobe signals.

[0086] Thirdly, this application provides a system-on-a-chip, including a semiconductor integrated circuit as described in any of the second aspects of this application.

[0087] Fourthly, this application provides an electronic device, including: a system-on-a-chip as described in the third aspect of this application.

[0088] Based on the above, this application is applied to semiconductor integrated circuits including signal TSVs and redundant TSVs. The connection circuit provided by this application includes a first selection circuit and a second selection circuit. The first selection circuit and the second selection circuit transmit a configuration signal for switching the transmission path of the communication signal through the signal TSV. When the signal TSV is normal, the first selection circuit and the second selection circuit can successfully transmit the configuration signal, and then transmit the communication signal through the signal TSV in response to the configuration signal. Correspondingly, when the signal TSV is abnormal, the first selection circuit and the second selection circuit cannot respond to the configuration signal, that is, they transmit the communication signal through the redundant TSV. Through the connection circuit provided by this application, the autonomous detection of the signal TSV status can be realized, and the signal TSV and the redundant TSV can be switched automatically according to the detection result. Since it is not necessary to provide the detection result to the outside, the feedback TSV can be omitted. Compared with the prior art, the TSV overhead is effectively reduced, thereby reducing the overall manufacturing cost of the chip. Attached Figure Description

[0089] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0090] Figure 1 This is a schematic diagram of the structure of a semiconductor integrated circuit in the prior art.

[0091] Figure 2 This is a structural block diagram of a connected circuit provided in this application.

[0092] Figure 3 This is a structural block diagram of another connected circuit provided in this application.

[0093] Figure 4 This is a structural block diagram of another connected circuit provided in this application.

[0094] Figure 5 This is a structural block diagram of another connected circuit provided in this application.

[0095] Figure 6 This is a schematic diagram of the structure of a semiconductor integrated circuit provided in this application.

[0096] Figure 7 This is a schematic diagram of the layout of a TSV and a connecting circuit provided in this application.

[0097] Figure 8 This is another schematic diagram of the layout of TSV and connecting circuit provided in this application.

[0098] Figure 9 This is a topology diagram of an alarm circuit provided in this application. Detailed Implementation

[0099] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0100] In existing technologies, 3D chips integrate multiple dies, which are interconnected via TSV communication, making the chip a unified whole and thus enabling more powerful functions. Figure 1 As shown, taking a 3D chip including two dies, die 1 and die 2, as an example, die 1 is provided with a multiplexer 1, die 2 is provided with a multiplexer 2, and multiple TSV signals for communication transmission are provided between die 1 and die 2. Figure 1 (Signals TSV1-4 are shown in the diagram), including a redundant TSV as a backup and a feedback TSV for reporting the TSV detection results. In practical applications, the functional modules inside die 1 that implement preset functions are connected to multiplexer 1, which connects the corresponding TSV signals. Similarly, the functional modules inside die 2 are connected to multiplexer 2, which connects the corresponding TSV signals, thereby enabling communication signal transmission between die 1 and die 2.

[0101] 3D chips contain a large number of TSVs, and in practical applications, it is inevitable that some TSVs will fail. Figure 1As shown, when a signal TSV fails, a redundant TSV can replace the failed signal TSV, thereby reducing the impact of the failed TSV on the overall performance of the chip. For example, if signal TSV1 fails, a redundant TSV can replace signal TSV1, and the communication signal originally transmitted by signal TSV1 can be transmitted through the redundant TSV, thus ensuring the normal operation of the 3D chip.

[0102] However, in order to detect the status of the signal TSV and switch the redundant TSV in time when the signal TSV is abnormal, a feedback TSV must be integrated into the chip. The feedback TSV reports the detection result of the signal TSV, and determines whether to switch the redundant TSV based on the detection result reported by the feedback TSV. Obviously, the existing technology increases the overhead of TSV and increases the overall manufacturing cost of 3D chip.

[0103] To address the aforementioned problems, this application provides a connection circuit applied to a semiconductor integrated circuit configured with signal TSV and redundant TSV. See [link to relevant documentation]. Figure 2 As shown, the connection circuit provided in this application includes a first selection circuit 10 and a second selection circuit 20. Based on the first selection circuit 10 and the second selection circuit 20, the signal TSV state can be autonomously detected, and the signal TSV and redundant TSV can be switched automatically according to the detection result. Since it is not necessary to provide the detection result to the outside, the feedback TSV can be omitted. Compared with the prior art, the TSV overhead is effectively reduced, thereby reducing the overall manufacturing cost of the chip.

[0104] It is understandable that in practical applications, semiconductor integrated circuits typically include multiple signal TSVs and multiple redundant TSVs. To facilitate the explanation of the specific implementation of the connection circuit provided in this application and its connection relationship with the TSVs, in... Figure 2 The embodiment shown only illustrates one signal TSV and one redundant TSV. The arrangement of TSVs and connecting circuits in the case of multiple signal TSVs and multiple redundant TSVs in a semiconductor integrated circuit will be discussed in detail later.

[0105] See Figure 2 As shown, the first selection circuit 10 is connected to the first terminals of both the signal TSV and the redundant TSV, and the second selection circuit 20 is connected to the second terminals of both the signal TSV and the redundant TSV. That is, the signal TSV and the redundant TSV are connected between the first selection circuit 10 and the second selection circuit 20. Figure 2As shown, there are two communication signal transmission paths between the first selection circuit 10 and the second selection circuit 20. One is the communication signal transmission path corresponding to the signal TSV, and the other is the communication signal transmission path corresponding to the redundant TSV. The first selection circuit 10 can transmit communication signals to the second selection circuit 20 through the signal TSV, or it can transmit communication signals to the second selection circuit 20 through the redundant TSV.

[0106] In this application, the first selection circuit 10 and the second selection circuit 20 also transmit a configuration signal for switching the communication signal transmission path via a TSV signal. Based on this, when the TSV signal is normal, the configuration signal can be reliably transmitted, and both the first selection circuit 10 and the second selection circuit 20 can receive and respond to the configuration signal. Conversely, when the TSV signal is abnormal, the configuration signal is difficult to transmit between the first selection circuit 10 and the second selection circuit 20. It should be noted that in this application, the source of the configuration signal can be varied. For example, it can be provided by a controller other than the semiconductor integrated circuit; another example is that a dedicated controller can be set in the interconnecting circuit to provide the configuration signal; yet another example is that it can be provided by any functional module in any die of the semiconductor integrated circuit. In short, any implementation that can provide the configuration signal and thus drive the interconnecting circuit provided in this application to operate normally is optional and, provided it does not exceed the core concept of this application, also falls within the scope of protection of this application.

[0107] Based on the above, when the TSV signal is normal, the first selection circuit 10 and the second selection circuit 20 respond to the obtained configuration signal and select the TSV signal to transmit the communication signal. Correspondingly, when the TSV signal is abnormal, the first selection circuit 10 and the second selection circuit 20 cannot exchange configuration signals, and then the communication signal is transmitted through redundant TSV.

[0108] In summary, if the first selection circuit and the second selection circuit can interact to configure signals and transmit communication signals through the signal TSV, then the signal TSV can be determined to be normal. Conversely, if the first selection circuit and the second selection circuit transmit communication signals through a redundant TSV, then the signal TSV can be determined to be abnormal. In other words, the connection circuit provided in this application can achieve autonomous detection of the signal TSV state. Simultaneously, the signal TSV and redundant TSV can automatically switch, ensuring reliable transmission of communication signals. Even if the signal TSV is abnormal, the redundant TSV can replace it. Furthermore, since the detection of the signal TSV state is completed by the first and second selection circuits during the communication signal transmission path selection process, it is not necessary to provide the detection results for the signal TSV to the outside. Therefore, the feedback TSV set in the prior art can be omitted, thereby effectively reducing TSV overhead and lowering the overall manufacturing cost of the chip.

[0109] Furthermore, in Figure 2 Based on the illustrated embodiment, this application also provides another connection circuit. See [link to embodiment]. Figure 3 As shown, in the connected circuit provided in this embodiment, the first selection circuit 10 includes an input control circuit 110 and an input selection circuit 120, and the second selection circuit 20 includes an output control circuit 210 and an output selection circuit 220.

[0110] Combination Figure 3 As shown, the input control circuit 110 in the first selection circuit 10 is connected to the output control circuit 210 in the second selection circuit 20 via the signal TSV. The input selection circuit 120 is connected to the first terminals of the signal TSV and the redundant TSV, respectively. The input control circuit 110 is also connected to the input selection circuit 120 to control the connection state between the input selection circuit 120 and the signal TSV and the redundant TSV.

[0111] Furthermore, the output selection circuit 220 in the second selection circuit 20 is connected to the second terminals of the signal TSV and the redundant TSV respectively, and the output control circuit 210 is connected to the output selection circuit 220 to control the connection state between the output selection circuit 220 and the signal TSV and the redundant TSV.

[0112] based on Figure 2In the illustrated embodiment, under normal TSV signal conditions, the input control circuit 110 and the output control circuit 210 can transmit configuration signals via TSV. Based on this, the input control circuit 110 responds to the configuration signal by controlling the input selection circuit 120 to connect with the TSV signal, and correspondingly, the output control circuit 210 responds to the configuration signal by controlling the output selection circuit 220 to connect with the TSV signal. This configuration ensures that, under normal TSV signal conditions, the input selection circuit 120 and the output selection circuit 220 can transmit communication signals via TSV. In practical applications, the input selection circuit 120 can be connected to a functional module in its die, receiving communication signals sent by that functional module and transmitting the received communication signals to the output selection circuit 220 via TSV. Similarly, the output selection circuit 220 can be connected to a functional module in its die, receiving the communication signals transmitted by the input selection circuit 120 and transmitting the received communication signals to its connected functional module, thus achieving complete communication signal transmission. Of course, the communication signal can also be transmitted from the output selection circuit 220 to the input selection circuit 120 via the signal TSV. The transmission process is similar to the above process and will not be described in detail here.

[0113] Correspondingly, in the event of an abnormal TSV signal, the input control circuit 110 cannot interact with the output control circuit 210 to configure signals via the TSV. The input control circuit 110 then controls the input selection circuit 120 to connect with the redundant TSV, while the output control circuit 210 controls the output selection circuit 220 to connect with the redundant TSV. Based on this, the input selection circuit 120 establishes a communication signal transmission path with the output selection circuit 220 via the redundant TSV. The input selection circuit 120 can send communication signals to the output selection circuit 220 via the redundant TSV, and similarly, the output selection circuit 220 can also send communication signals to the input selection circuit 120 via the redundant TSV. The specific signal transmission process can be found in the preceding description and will not be repeated here.

[0114] In one optional implementation, the configuration signals described in this application include a first reset signal, a first test signal, a second reset signal, and a second test signal configured sequentially. It should be emphasized that the configuration signals described in this embodiment are provided to the connected circuit in a strictly sequential order. The following is in conjunction with... Figure 3 The example shown details the process of the connected circuit responding to the configuration signal provided in this embodiment.

[0115] When the TSV signal is normal, the process by which the first selection circuit 10 and the second selection circuit 20 respond to the configuration signal is as follows:

[0116] S11: Input control circuit 110 receives and responds to the first reset signal, controlling input selection circuit 120 to connect with redundant TSV.

[0117] S12: The output control circuit 210 receives and responds to the first test signal, controls the output selection circuit 220 to connect with the signal TSV, and more importantly, the output control circuit 210 also provides the first test signal to the input control circuit 110 through the signal TSV.

[0118] S13: The input control circuit 110 receives the first test signal provided by the output control circuit 210 and controls the input selection circuit 120 to connect with the signal TSV. In this way, the input selection circuit 120 is switched from redundant TSV to signal TSV.

[0119] S14: The output control circuit 210 receives and responds to the second reset signal, and controls the output selection circuit 220 to connect with the redundant TSV, thereby switching the output selection circuit 220 from the signal TSV to the redundant TSV.

[0120] S15: Input selection circuit 120 receives the second test signal. Since input selection circuit 120 has been connected to signal TSV in S13, input selection circuit 120 provides the second test signal to output control circuit 210 through signal TSV.

[0121] S16: In response to the obtained second test signal, the output control circuit 210 controls the output selection circuit 220 to connect with the signal TSV, that is, the output selection circuit 220 is switched from redundant TSV to signal TSV.

[0122] At this point, the input selection circuit 120 is connected to the output selection circuit 220 via the signal TSV, thus obtaining the communication signal transmission path under normal conditions for the signal TSV.

[0123] In the event of an abnormal TSV signal, the first selection circuit 10 and the second selection circuit 20 respond to the configuration signal as follows:

[0124] S21. The input control circuit 110 receives and responds to the first reset signal, and controls the input selection circuit 120 to connect with the redundant TSV.

[0125] S22, the output control circuit 210 receives and responds to the first test signal, controlling the output selection circuit 220 to connect with the signal TSV. Compared to the above, due to the abnormality of the signal TSV, the input control circuit 110 and the output control circuit 210 cannot exchange the first test signal through the signal TSV. The input control circuit 110 will not control the input selection circuit 120 to switch from the redundant TSV to the signal TSV, but will maintain the connection between the input selection circuit 120 and the redundant TSV.

[0126] S23. The output control circuit 210 receives and responds to the second reset signal, and controls the output selection circuit 220 to connect with the redundant TSV, thereby switching the output selection circuit 220 from the signal TSV to the redundant TSV.

[0127] S24. The input selection circuit 120 receives the second test signal. Due to the abnormality of the signal TSV, the second test signal can only be provided to the output selection circuit 220 through the redundant TSV. Since the output control circuit 210 does not receive the second test signal, it will not control the output selection circuit 220 to connect with the signal TSV. The second test signal is directly output by the output selection circuit 220.

[0128] At this point, the input selection circuit 120 is connected to the output selection circuit 220 via redundant TSV, thus obtaining the communication signal transmission path under abnormal TSV conditions.

[0129] Furthermore, based on the foregoing embodiments, this application also provides specific implementations of the first selection circuit and the second selection circuit.

[0130] See Figure 4 As shown, the input control circuit 110 in the first selection circuit 10 includes a first OR gate U1. Specifically, the first OR gate U1 is provided with a first input terminal C11, a second input terminal C12, and an output terminal C13. The first input terminal C11 of the first OR gate U1 serves as a connection terminal of the input control circuit 110, used to receive a first reset signal. The output terminal C13 of the first OR gate U1 is connected to the first input terminal C11 of the first OR gate U1 and the control terminal of the input selection circuit 120, respectively. The second input terminal C12 of the first OR gate U1 is connected to the first terminal of the signal TSV.

[0131] Combining the aforementioned connection relationships and Figure 4 As shown, the connection of the first OR gate U1 constitutes a latching circuit. When the second input terminal C12 receives a high level (1), the output terminal C13 of the first OR gate U1 outputs a high level and feeds back the high level to its own first input terminal C13, thereby achieving closed-loop self-locking. In this case, regardless of how the input to the second input terminal C12 of the first OR gate U1 changes, the first OR gate U1 will maintain a high-level output until the first input terminal C11 of the first OR gate U1 receives a low level (0), unlocking the closed-loop self-locking of the first OR gate U1. The closed-loop self-locking function implemented based on the first OR gate U1 plays an important role in this application, which will be elaborated in detail later.

[0132] Input selection circuit 120 includes a first multiplexer, combined with Figure 4As shown, the first multiplexer has a first output terminal S11, a second output terminal S12, an input terminal S13, and a control terminal S14. The first output terminal S11 is connected to the signal TSV, and the second output terminal S12 is connected to the first terminal of the redundant TSV. The input terminal S13 is used to receive a second test signal. Correspondingly, after completing the status detection of the signal TSV and determining whether to transmit the communication signal via the signal TSV or the redundant TSV, the input terminal S13 of the first multiplexer can also be used to receive the communication signal. The control terminal S14 of the first multiplexer serves as the control terminal of the input selection circuit 120, is connected to the output terminal C13 of the first OR gate U1, and receives the selection signal provided by the first OR gate U1. In one optional implementation, the strobe signal includes a first strobe signal and a second strobe signal. The first strobe signal can be 0, i.e., low level. The first multiplexer responds to the first strobe signal by connecting the input terminal S13 and the second output terminal S12. Correspondingly, the second strobe signal can be 1, i.e. high level. The first multiplexer responds to the second strobe signal by connecting the input terminal S13 and the first output terminal S11.

[0133] Furthermore, the output control circuit 210 in the second selection circuit 20 includes a second OR gate U2. Similar to the aforementioned first OR gate U1, the second OR gate U2 has a first input terminal C21, a second input terminal C22, and an output terminal C23. The first input terminal C21 of the second OR gate U2 serves as an external terminal of the output control circuit 210, used to receive a second reset signal. The second input terminal C22 of the second OR gate U2 is connected to the second terminal of the signal TSV, and simultaneously serves as another external terminal of the output control circuit 210, used to receive a first test signal. The output terminal C23 of the second OR gate U2 is connected to both the first input terminal C21 of the second OR gate U2 and the control terminal of the output selection circuit 220.

[0134] Referring to the foregoing, the connection method of the second OR gate U2 also constitutes a latching circuit. When the second input terminal C22 receives a high level (1), the output terminal C23 of the second OR gate U2 outputs a high level and feeds back the output high level to its first input terminal C21, thereby achieving closed-loop self-locking. In this case, no matter how the input of the second input terminal C22 of the second OR gate U2 changes, the second OR gate U2 will maintain a high-level output until the first input terminal C21 of the second OR gate U2 receives a low level (0), unlocking the closed-loop self-locking of the second OR gate U2. Unlike the first OR gate U1, the signal source for the second input terminal C22 of the second OR gate U2 is twofold: one is the externally configured first test signal, and the other is the signal transmitted by the TSV signal under normal conditions.

[0135] Output selection circuit 220 includes a third multiplexer, combined with Figure 4 As shown, the third multiplexer has a first input terminal S21, a second input terminal S22, an output terminal S23, and a control terminal S24. The first input terminal S21 is connected to the second terminal of the signal TSV, and the second input terminal S22 is connected to the second terminal of the redundant TSV. The output terminal S23 serves as an external terminal for transmitting communication signals in a connected circuit. The control terminal S24 serves as the control terminal of the output selection circuit 220 and is connected to the output terminal C23 of the second OR gate U2. Referring to the foregoing, when the third multiplexer receives a first selection signal, it connects the output terminal S23 to the second input terminal S22, i.e., connects the output terminal S23 to the redundant TSV. Correspondingly, when it receives a second selection signal, it connects the output terminal S23 to the first input terminal S21, i.e., connects the output terminal S23 to the signal TSV.

[0136] The following is based on Figure 4 The circuit topology provided in the illustrated embodiment is explained in detail, illustrating the process of the connected circuit corresponding to the aforementioned configuration signals.

[0137] When the TSV signal is normal, the process by which the first selection circuit 10 and the second selection circuit 20 respond to the configuration signal is as follows:

[0138] S31: Input control circuit 110 receives and responds to the first reset signal 00, the first OR gate U1 outputs the first strobe signal 0, the first multiplexer in input selection circuit 120 responds to the first strobe signal and connects the input terminal S13 to the second output terminal S12, that is, connects the input terminal S13 to the redundant TSV.

[0139] S32: Output control circuit 210 receives and responds to the first test signal 10. The second input terminal C22 of the second OR gate U2 first receives a high level 1. In this case, the output terminal C23 of the second OR gate U2 outputs a high level 1, i.e., the second strobe signal. At the same time, the second OR gate U2 enters a self-locking mode. Even if the second input terminal C22 of the second OR gate U2 subsequently receives a low level 0, the output terminal C23 of the second OR gate U2 will still continuously output the second strobe signal. Accordingly, while the output control circuit 210 continuously provides the second strobe signal, the output terminal S23 of the third multiplexer is connected to the signal TSV.

[0140] More importantly, the first test signal will also be transmitted to the input control circuit 110, i.e., the second input terminal C12 of the first OR gate, via the signal TSV.

[0141] It should be noted that configuring the first test signal to 10, that is, providing a low level after providing a high level, is mainly to prevent the subsequent state switching of the output control circuit 210 from being affected by the first test signal being continuously high.

[0142] S33: In the input control circuit 110, the second input terminal C12 of the first OR gate U1 receives the first test signal via the signal TSV. As mentioned earlier, before S12, the first OR gate U1 outputs a low level 0, i.e., provides a first strobe signal. Based on this, after receiving the high level 1 in the first test signal, the first OR gate U1 will output a high level, i.e., a second strobe signal. At the same time, the first OR gate U1 enters a self-locking state, and even if the low level 0 in the first test signal arrives, the first OR gate U1 will still maintain the output of the second strobe signal. The first multiplexer in the control input selection circuit 120 responds to the second strobe signal by connecting its input terminal S13 with its first output terminal S11, i.e., connecting its input terminal S13 with the signal TSV. In this way, the input selection circuit 120 is switched from redundant TSV to signal TSV.

[0143] S34: The first input terminal C21 of the second OR gate U2 in the output control circuit 210 receives the second reset signal 00. At this time, the self-locking state of the second OR gate U2 will be unlocked, and the output terminal C23 of the second OR gate U2 will output the first strobe signal, i.e., low level 0 (at this time, the second input terminal C22 of the second OR gate U2 also receives a low level). The third multiplexer circuit in the output selection circuit 220 responds to the first strobe signal and connects the output terminal S23 with the second input terminal S22, i.e., connects with the redundant TSV. In this way, the output selection circuit 220 is switched from the signal TSV to the redundant TSV.

[0144] S35: The first multiplexer in the input selection circuit 120 receives the second test signal 11 through the input terminal S13. Since the input selection circuit 120 has been connected to the signal TSV in S33, the input selection circuit 120 provides the second test signal to the output control circuit 210 through the signal TSV.

[0145] S36: The second input terminal C22 of the second OR gate U2 in the output control circuit 210 receives the second test signal 11. The output terminal C23 of the second OR gate U2 will output the second strobe signal, i.e., high level 1. At the same time, the second OR gate U2 enters a self-locking state to maintain the output of the second strobe signal. The third multiplexer in the output selection circuit 220 responds to the second strobe signal and connects the output terminal S23 with the first input terminal S21, i.e., connects with the signal TSV. That is, the output selection circuit 220 is switched from redundant TSV to signal TSV.

[0146] At this point, the input selection circuit 120 is connected to the output selection circuit 220 via the signal TSV, thus obtaining the communication signal transmission path of the signal TSV under normal conditions, which is consistent with the expected signal transmission path of the signal TSV under normal conditions.

[0147] In the event of an abnormal TSV signal, the first selection circuit 10 and the second selection circuit 20 respond to the configuration signal as follows:

[0148] S41. Input control circuit 110 receives and responds to first reset signal 00. First OR gate U1 outputs first strobe signal 0. First multiplexer in input selection circuit 120 responds to first strobe signal and connects input terminal S13 to second output terminal S12, that is, connects input terminal S13 to redundant TSV.

[0149] S42. The output control circuit 210 receives and responds to the first test signal 10. The second input terminal C22 of the second OR gate U2 first receives a high level 1. In this case, the output terminal C23 of the second OR gate U2 outputs a high level 1, which is the second strobe signal. At the same time, the second OR gate U2 enters a self-locking mode. Even if the second input terminal C22 of the second OR gate U2 subsequently receives a low level 0, the output terminal C23 of the second OR gate U2 will still continue to output the second strobe signal. Accordingly, while the output control circuit 210 continuously provides the second strobe signal, the output terminal S23 of the third multiplexer is connected to the signal TSV.

[0150] Compared to the above, due to the abnormality of the TSV signal, the input control circuit 110 and the output control circuit 210 cannot exchange the first test signal through the TSV signal. The input control circuit 110 will not control the input selection circuit 120 to switch from the redundant TSV to the signal TSV, but will maintain the connection between the input selection circuit 120 and the redundant TSV.

[0151] S43. In the output control circuit 210, the first input terminal C21 of the second OR gate U2 receives the second reset signal 00. At this time, the self-locking state of the second OR gate U2 will be unlocked, and the output terminal C23 of the second OR gate U2 will output the first strobe signal, i.e., low level 0 (at this time, the second input terminal C22 of the second OR gate U2 also receives a low level). The third multiplexer circuit in the output selection circuit 220 responds to the first strobe signal and connects the output terminal S23 with the second input terminal S22, i.e., connects with the redundant TSV. In this way, the output selection circuit 220 is switched from the signal TSV to the redundant TSV.

[0152] S44. The input selection circuit 120 receives the second test signal. Due to the abnormality of the signal TSV, the second test signal can only be provided to the output selection circuit 220 through the redundant TSV. Since the output control circuit 210 does not receive the second test signal, it will not control the output selection circuit 220 to connect with the signal TSV. The second test signal is directly output by the output selection circuit 220.

[0153] At this point, the input selection circuit 120 is connected to the output selection circuit 220 via the redundant TSV, thus obtaining the communication signal transmission path in the case of abnormal TSV signal, which is the same as the expected switching process in which the redundant TSV replaces the abnormal TSV signal.

[0154] In summary, the connectivity circuit provided in this embodiment enables autonomous detection of the TSV (Transmission Switched Stream) status. Simultaneously, the signal TSV and redundant TSVs can automatically switch, ensuring reliable transmission of communication signals. Even if the signal TSV malfunctions, the redundant TSV can replace it. Furthermore, since the detection of the signal TSV status is completed by the first and second selection circuits during the communication signal transmission path selection process, there is no need to provide the detection results for the signal TSV to the outside. Therefore, the feedback TSV required in the prior art can be omitted, effectively reducing TSV overhead and lowering the overall manufacturing cost of the chip.

[0155] Based on the above, it can be seen that Figure 4 The connected circuit provided in the illustrated embodiment shares the input terminal of the first selection circuit with the communication signal and the second test signal. In practical applications, after selecting the signal TSV and redundant TSV according to the configuration signals provided in sequence, the communication signal can be transmitted through the selected communication signal transmission path. Since the input terminal of the first multiplexer is a time-division multiplexed pin, used to receive both the communication signal and the second test signal, it is necessary to distinguish between the testing process and the signal transmission process; otherwise, signal transmission errors may easily occur. To solve this problem, this application provides another connected circuit, see [link to application]. Figure 5 As shown, in Figure 4 Based on the illustrated embodiment, the connecting circuit provided in this embodiment further includes the following components.

[0156] Combination Figure 5 As shown, in the connected circuit provided in this embodiment, the input selection circuit 120 in the first selection circuit 10 further includes a second multiplexer. Accordingly, in order to realize the selection control of the second multiplexer, the aforementioned configuration signal also includes a first selection signal and a second selection signal. Following the previous example, the first selection signal can be low level and the second selection signal can be high level.

[0157] The second multiplexer is provided with a first input terminal S15, a second input terminal S16, an output terminal S17, and a control terminal S18. The first input terminal S15 of the second multiplexer is used to receive communication signals, the second input terminal S16 of the second multiplexer is used to receive a second test signal, the output terminal S17 of the second multiplexer is connected to the input terminal S13 of the first multiplexer, and the control terminal S18 of the second multiplexer is used to receive the aforementioned first strobe signal or second strobe signal.

[0158] Based on the above, during the testing phase of the signal TSV, i.e., the phase of selecting the signal TSV or the redundant TSV, the control terminal S18 of the second multiplexer receives the first strobe signal and connects its second input terminal S16 to its output terminal S17 to ensure that the second test signal can be successfully transmitted to the first multiplexer. The signal TSV or the redundant TSV is selected according to the process described in the aforementioned embodiment. Based on this, it can be understood that in terms of the signal configuration order, the first strobe signal should be located between the second reset signal and the second test signal to ensure that the second input terminal S16 and the output terminal S17 of the second multiplexer are connected through the first strobe signal before the arrival of the second test signal.

[0159] Furthermore, after receiving the second test signal and completing the selection and switching of the TSV, the second multiplexer responds to the second strobe signal by connecting its first input terminal S15 and its output terminal S17, preparing to receive the communication signals transmitted during the communication process through the first input terminal S15. It is understood that the second strobe signal is configured after the second test signal.

[0160] Based on the above, it can be seen that the connection circuit provided in this embodiment adds a second multiplexer. By reasonably configuring the order of the first strobe signal, the second test signal, and the second strobe signal, the switching between the communication signal transmission path and the test signal transmission path can be realized, effectively distinguishing the transmission process of the communication signal and the test signal, and improving the reliability and safety of the connection circuit during use.

[0161] Furthermore, in the connection circuit provided in this embodiment, the input control circuit 110 further includes: a first diode D1, combined with... Figure 5 As shown, the anode of the first diode D1 is used to receive the first reset signal, and the cathode of the first diode D1 is connected to the first input terminal C11 of the first OR gate U1. The input selection circuit 120 also includes a second diode D2. The anode of the second diode D2 is connected to the first output terminal S11 of the first multiplexer, and the cathode is connected to the first terminal of the signal TSV. That is, the second diode D2 is connected in series between the first multiplexer and the signal TSV.

[0162] Correspondingly, the output control circuit 210 also includes a third diode D3 and a fourth diode D4, combined with Figure 5 As shown, the anode of the third diode D3 is used to receive the first test signal, and the cathode of the third diode D3 is connected to the second terminal of the signal TSV. The anode of the fourth diode D4 is used to receive the second reset signal, and the cathode of the fourth diode D4 is connected to the first input terminal C21 of the second OR gate U2.

[0163] By placing diodes at the aforementioned locations, signals at those locations can be effectively prevented from entering other transmission paths. At the same time, signal backflow can also be effectively prevented, thereby ensuring the reliability of the signal transmission direction.

[0164] Furthermore, this application also provides a semiconductor integrated circuit, including at least two dies and at least one interconnecting circuit as provided in any of the foregoing embodiments. The dies in the semiconductor integrated circuit are stacked sequentially in a vertical direction, with any one of the aforementioned at least two dies serving as the first die, and the die connected to the first die serving as the second die. In the semiconductor integrated circuit provided in this application, the first die and the second die are connected via a signal TSV and a redundant TSV.

[0165] Combination Figure 6 As shown, taking a semiconductor integrated circuit comprising two dies as an example, one die is designated as the first die, and the other as the second die. A first selection circuit in the connecting circuit is located in the first die, and correspondingly, a second selection circuit is located in the second die. Functional units in the first die that need to communicate with the second die are connected to the first selection circuit, and functional units in the second die that need to communicate with the first die are connected to the second selection circuit. A signal TSV and a redundant TSV are provided between the first and second dies. The first terminal of the signal TSV and the redundant TSV are connected to the first selection circuit, and the second terminal is connected to the second selection circuit. The detection of the signal TSV through the connecting circuit and the switching process between the signal TSV and the redundant TSV can be referred to the relevant content of the aforementioned embodiments, and will not be repeated here.

[0166] exist Figure 1In the existing technology shown, when any TSV signal malfunctions and redundant TSVs need to be activated, the transmission path of the communication signal needs to be shifted step by step. For example, if TSV1 malfunctions, the communication signal originally transmitted by TSV1 needs to be transmitted by TSV2, and the communication signal originally transmitted by TSV2 is then transmitted by TSV3, and so on, until the communication signal originally transmitted by TSV4 is transmitted by the redundant TSV, thus activating the redundant TSV and replacing the malfunctioning TSV. This step-by-step shifting of communication signals to activate redundant TSVs typically lengthens the communication signal transmission path, leading to increased signal transmission delays and making timing issues highly likely.

[0167] To address the aforementioned issues, based on the aforementioned embodiments, this application divides the signal TSVs and redundant TSVs between the first die and the second die (i.e., any two adjacent dies) into at least one TSV cluster. Each TSV cluster includes at least one signal TSV and one redundant TSV, and each signal TSV within the TSV cluster is configured with a connection circuit provided in the aforementioned embodiments.

[0168] Understandably, configuring a redundant TSV for each signal TSV, while effectively improving the reliability of the signal transmission path, would require a large number of redundant TSVs, consuming significant space in the integrated circuit and substantially increasing its overall cost. Therefore, in practical applications, multiple signal TSVs can be integrated into each TSV cluster, with each cluster sharing a redundant TSV. When one of the multiple TSVs fails, the redundant TSV can replace it. The number of signal TSVs in a cluster—how many signal TSVs should be configured for each redundant TSV—needs to be determined based on the failure rate of the signal TSVs in the actual application.

[0169] In one optional implementation, the failure rate of the signal TSV can be determined through actual fabrication data or laboratory data. This application does not limit the specific source of the TSV failure rate. The TSV failure rate is proportional to the ratio of redundant TSVs to signal TSVs. Based on the TSV failure rate, the configuration ratio of signal TSVs to redundant TSVs can be determined. For example, if there is approximately a 10% TSV failure rate, it is determined that one redundant TSV needs to be configured for every five signal TSVs. Therefore, when dividing TSV clusters, each TSV cluster includes five signal TSVs and one redundant TSV. As mentioned earlier, a connection circuit is configured for each signal TSV within a TSV cluster. The connection circuit corresponding to each signal TSV is connected to the corresponding signal TSV and the redundant TSV within the TSV cluster, respectively. For specific connection methods, please refer to the relevant content of the foregoing embodiments, which will not be repeated here.

[0170] Furthermore, to ensure that replacing a signal TSV with a redundant TSV does not cause a significant change in the path length of the communication signal transmission path, this application requires that the distance between each signal TSV and the redundant TSV in the horizontal direction be equal when deploying TSVs in each TSV cluster. Based on this, as a preferred embodiment, each signal TSV in the same TSV cluster should be evenly distributed around the redundant TSV.

[0171] Taking a TSV cluster with six signal TSVs configured into a redundant TSV as an example, the signal TSVs, redundant TSVs, and connecting circuits can be referenced. Figure 7 The layout is shown below. Specifically, each signal TSV is positioned at a vertex of a hexagon, centered on a redundant TSV. Connecting circuits are placed between the redundant TSV and the corresponding signal TSV. Furthermore, to minimize the impact of signal transmission path changes on signal timing during TSV switching, the connecting circuit is positioned between the signal TSV and the redundant TSV; that is, the timing path distance between any connecting circuit and the redundant TSV is equal to the timing path distance between the connecting circuit and the corresponding signal TSV. With this configuration, when any signal TSV malfunctions, switching to the redundant TSV can be achieved through the connecting circuit connected to that signal TSV. The redundant TSV replaces the malfunctioning signal TSV, avoiding the problem of step-by-step communication path switching in existing technologies. It also ensures that the transmission path lengths of the communication signal to the signal TSV and the redundant TSV are the same, thus ensuring equal path delays regardless of whether the signal TSV or the redundant TSV is selected, preventing timing changes after switching to the redundant TSV.

[0172] In a preferred embodiment, when multiple TSV clusters exist between the first die and the second die, the arrangement of each TSV cluster can be referred to Figure 8 As shown, with Figure 7 Similar to the examples shown, circles represent signal TSVs, squares represent redundant TSVs, and rectangles represent connected circuits. Figure 8 Deploying TSV clusters can improve the space utilization of semiconductor integrated circuits while ensuring that there are no major timing delays when switching TSVs, thus minimizing the space occupied by TSVs.

[0173] It is understandable that in the aforementioned embodiments, multiple signal TSVs share a redundant TSV. When one signal TSV malfunctions, it can be replaced by the redundant TSV. However, when two or more signal TSVs malfunction, there is a problem that one or more malfunctioning TSVs cannot be replaced, and the reliability of the signal transmission process will inevitably be affected.

[0174] To promptly identify the aforementioned problems, the semiconductor integrated circuit provided in this application also includes at least one alarm circuit. In practical applications, the alarm circuit can be configured based on the number of TSV clusters, such that each TSV cluster corresponds to one alarm circuit. The alarm circuit detects the status of each signal TSV within the corresponding TSV cluster and outputs an alarm signal when at least two signal TSVs are abnormal. It is understood that this alarm signal can be directly provided to any die in the integrated circuit, or to a controller within the integrated circuit that provides the aforementioned configuration signals. Alternatively, it can be fed back to another host computer outside the integrated circuit using relevant technical means to notify the receiver of the alarm signal that two or more signal TSVs within the corresponding TSV cluster of the integrated circuit are abnormal and require handling.

[0175] See Figure 9 As shown, taking a TSV cluster containing five TSV signals as an example, this application provides an optional implementation of an alarm circuit. The alarm circuit provided in this embodiment is mainly constructed using AND gates and OR gates, where I1 to I5 are the input terminals of the alarm circuit, and O1 is the output terminal of the alarm circuit. For the specific connection method between each AND gate and OR gate, please refer to [link to relevant documentation]. Figure 9 As shown, further details will not be elaborated here.

[0176] In conjunction with the connected circuit provided in the foregoing embodiments, the first selection circuit in the connected circuit includes an input control circuit and an input selection circuit. When the connected signal TSV is abnormal, the input control circuit outputs a first strobe signal to the input selection circuit. Based on this, the alarm circuit is connected to the input control circuit of each connected circuit in the same TSV cluster. That is, each input terminal of the alarm circuit is connected to the output segment of the input control circuit of a connected circuit, thereby collecting the first strobe signal of the corresponding input control circuit. When the alarm circuit detects at least two first strobe signals, it outputs an alarm signal.

[0177] In summary, by setting alarm circuits within each TSV cluster, the operating status of the corresponding TSV signal can be detected. When two or more TSV signals are abnormal, an alarm signal is provided to indicate that the TSV cluster has an unrepairable problem. This allows for more timely feedback on the integrated circuit's operating status, which is of great importance for troubleshooting and maintaining the operating status of integrated circuits.

[0178] Furthermore, this application also provides a system-on-a-chip, including a semiconductor integrated circuit as provided in any of the foregoing embodiments of this application.

[0179] This application also provides an electronic device, including: a system-on-a-chip as provided in any of the foregoing embodiments of this application.

[0180] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0181] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0182] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0183] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0184] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0185] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A connected circuit, characterized in that, Applied to semiconductor integrated circuits, the semiconductor integrated circuit includes signal TSVs and redundant TSVs, and the connecting circuit includes: a first selection circuit and a second selection circuit, wherein, The first selection circuit is connected to the first terminal of the signal TSV and the redundant TSV, respectively. The second selection circuit is connected to the second terminals of the signal TSV and the redundant TSV, respectively; The first selection circuit and the second selection circuit transmit a configuration signal for switching the communication signal transmission path via the signal TSV. When the TSV signal is normal, the first selection circuit and the second selection circuit transmit communication signals through the TSV signal in response to the configuration signal. In the event of an abnormal TSV signal, the first selection circuit and the second selection circuit transmit communication signals via redundant TSVs.

2. The connected circuit according to claim 1, characterized in that, The first selection circuit includes an input control circuit and an input selection circuit, and the second selection circuit includes an output control circuit and an output selection circuit, wherein, The input control circuit is connected to the output control circuit via the signal TSV; The input selection circuit is connected to the first terminal of the signal TSV and the redundant TSV, respectively. The output selection circuit is connected to the second terminal of the signal TSV and the redundant TSV, respectively. When the signal TSV is normal, the input control circuit responds to the configuration signal to control the input selection circuit to connect with the signal TSV, and the output control circuit responds to the configuration signal to control the output selection circuit to connect with the signal TSV. In the event of an abnormal TSV signal, the input control circuit controls the input selection circuit to connect with the redundant TSV, and the output control circuit controls the output selection circuit to connect with the redundant TSV.

3. The connecting circuit according to claim 2, characterized in that, The configuration signals include a first reset signal, a first test signal, a second reset signal, and a second test signal configured sequentially. When the TSV signal is normal, the process by which the first selection circuit and the second selection circuit respond to the configuration signal includes: The input control circuit responds to the first reset signal by controlling the input selection circuit to connect with the redundant TSV. In response to the first test signal, the output control circuit controls the output selection circuit to connect with the signal TSV, and provides the first test signal to the input control circuit through the signal TSV. The input control circuit responds to the first test signal and controls the input selection circuit to connect with the signal TSV. The output control circuit responds to the second reset signal by controlling the output selection circuit to connect with the redundant TSV. The input selection circuit receives the second test signal and provides the second test signal to the output control circuit via the signal TSV. The output control circuit responds to the second test signal and controls the output selection circuit to connect with the signal TSV.

4. The connecting circuit according to claim 3, characterized in that, In the event of an abnormal TSV signal, the process by which the first selection circuit and the second selection circuit respond to the configuration signal includes: The input control circuit responds to the first reset signal by controlling the input selection circuit to connect with the redundant TSV. The output control circuit responds to the first test signal and controls the output selection circuit to connect with the signal TSV. The output control circuit responds to the second reset signal by controlling the output selection circuit to connect with the redundant TSV. The input selection circuit receives the second test signal and provides the second test signal to the output selection circuit through redundant TSV.

5. The connecting circuit according to claim 2, characterized in that, The configuration signals include a first reset signal, a first test signal, a second reset signal, and a second test signal configured sequentially. The input control circuit includes: a first OR gate, wherein... The first OR gate is provided with a first input terminal, a second input terminal, and an output terminal, wherein, The first input terminal of the first OR gate is used to receive the first reset signal; The output terminal of the first OR gate is connected to the first input terminal of the first OR gate and the control terminal of the input selection circuit, respectively. The second input terminal of the first OR gate is connected to the first terminal of the signal TSV. The input selection circuit includes: a first multiplexer, wherein, The first multiplexer is provided with a first output terminal, a second output terminal, an input terminal, and a control terminal, wherein, The first output terminal of the first multiplexer is connected to the signal TSV, and the second output terminal of the first multiplexer is connected to the first terminal of the redundant TSV. The input of the first multiplexer is used to receive the second test signal; The control terminal of the first multiplexer serves as the control terminal of the input selection circuit.

6. The connected circuit according to claim 5, characterized in that, The configuration signal further includes a first strobe signal and a second strobe signal; The input selection circuit further includes: a second multiplexer, wherein... The second multiplexer is provided with a first input terminal, a second input terminal, an output terminal, and a control terminal, wherein, The first input terminal of the second multiplexer is used to receive a communication signal, and the second input terminal of the second multiplexer is used to receive the second test signal; The output of the second multiplexer is connected to the input of the first multiplexer; The control terminal of the second multiplexer is used to receive either the first strobe signal or the second strobe signal; The second multiplexer responds to the first strobe signal by connecting its second input and output terminals, or responds to the second strobe signal by connecting its first input and output terminals.

7. The connected circuit according to claim 6, characterized in that, The input control circuit further includes: a first diode, wherein... The anode of the first diode is used to receive the first reset signal, and the cathode of the first diode is connected to the first input terminal of the first OR gate. The input selection circuit further includes a second diode, wherein... The anode of the second diode is connected to the first output terminal of the first multiplexer, and the cathode of the second diode is connected to the first terminal of the signal TSV.

8. The connecting circuit according to claim 2, characterized in that, The configuration signals include a first reset signal, a first test signal, a second reset signal, and a second test signal configured sequentially. The output control circuit includes: a second OR gate, wherein, The second OR gate is provided with a first input terminal, a second input terminal, and an output terminal, wherein, The first input of the second OR gate is used to receive the second reset signal; The second input terminal of the second OR gate is connected to the second terminal of the signal TSV and is used to receive the first test signal; The output terminal of the second OR gate is connected to the first input terminal of the second OR gate and the control terminal of the output selection circuit, respectively. The output selection circuit includes: a third multiplexer, wherein, The third multiplexer is provided with a first input terminal, a second input terminal, a control terminal, and an output terminal, wherein, The first input terminal of the third multiplexer is connected to the second terminal of the signal TSV, and the second input terminal of the third multiplexer is connected to the second terminal of the redundant TSV. The output of the third multiplexer is used to transmit communication signals; The control terminal of the third multiplexer serves as the control terminal of the output selection circuit.

9. The connecting circuit according to claim 8, characterized in that, The output control circuit further includes: a third diode and a fourth diode, wherein, The anode of the third diode is used to receive the first test signal, and the cathode of the third diode is connected to the second terminal of the signal TSV. The anode of the fourth diode is used to receive the second reset signal, and the cathode of the fourth diode is connected to the first input terminal of the second OR gate.

10. The connecting circuit according to any one of claims 1 to 9, characterized in that, Also includes: A controller used to provide the configuration signals.

11. A semiconductor integrated circuit, characterized in that, include: At least two bare dies and at least one interconnecting circuit as described in any one of claims 1 to 10, wherein, The bare wafers are stacked sequentially in the vertical direction; The first die and the second die are connected by a signal TSV and a redundant TSV, wherein the first die is any one of the at least two dies, and the second die is the die adjacent to the first die; The first selection circuit in the connected circuit is disposed on the first bare die; The second selection circuit in the connected circuit is configured with the second die.

12. The semiconductor integrated circuit according to claim 11, characterized in that, The signal TSVs and redundant TSVs between the first die and the second die are divided into at least one TSV cluster; The TSV cluster includes at least one signal TSV and one redundant TSV, and each signal TSV is configured with one of the connected circuits.

13. The semiconductor integrated circuit according to claim 12, characterized in that, Within the same TSV cluster, each signal TSV and redundant TSV are equidistant in the horizontal direction.

14. The semiconductor integrated circuit according to claim 13, characterized in that, Within the same TSV cluster, each signal TSV is distributed around the redundant TSVs.

15. The semiconductor integrated circuit according to claim 12, characterized in that, Within the same TSV cluster, the timing path distance between any connected circuit and a redundant TSV is equal to the timing path distance between the connected circuit and the corresponding signal TSV.

16. The semiconductor integrated circuit according to claim 12, characterized in that, It also includes at least one alarm circuit, wherein, Each of the TSV clusters is configured with one of the alarm circuits; The alarm circuit is used to detect the status of each signal TSV in the corresponding TSV cluster.

17. The semiconductor integrated circuit according to claim 16, characterized in that, The TSV cluster includes two or more signal TSVs; The alarm circuit outputs an alarm signal when at least two TSV signals are abnormal.

18. The semiconductor integrated circuit according to claim 17, characterized in that, The first selection circuit includes an input control circuit and an input selection circuit. When the connected signal TSV is abnormal, the input control circuit outputs a first strobe signal to the input selection circuit. The alarm circuits are respectively connected to the input control circuits of each connected circuit within the same TSV cluster; The alarm circuit outputs the alarm signal when it detects at least two of the first strobe signals.

19. A system-on-a-chip, characterized in that, include: The semiconductor integrated circuit as described in any one of claims 11 to 18.

20. An electronic device, characterized in that, include: The system-on-a-chip as described in claim 19.

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