A clock source frequency offset correction method for an isolated sampling device

Abstract

This invention discloses a clock source frequency offset correction method for an isolated sampling device, relating to the field of power line communication systems. The clock source frequency offset correction method for the isolated sampling device includes the following steps: Step 1: The MCU chip drives a second timer with an external clock source, and the reference sampling frequency is denoted as F. c Step 2: After the second timer interrupt is triggered, the MCU chip generates a record of the number of sampling points of the ADC chip in the previous second; Step 3: The MCU chip generates the record of the number of sampling points of the ADC chip in the previous second after the second timer interrupt is triggered N times in a loop; Step 4: The MCU chip calculates the actual sampling frequency F of the ADC based on the N sampling point records. re Step 5: The MCU chip uses the actual sampling frequency F re Calculate the parameters I of the Gardner interpolation algorithm x Step 6: The MCU chip uses the interpolation parameter I... x The Gardner interpolation algorithm is used to interpolate F re The sampled data is interpolated at a sampling frequency of F. c Data; Step 7: Repeat steps 1 to 6 to correct the sampling frequency of the ADC cross-sampling chip in real time.

Description

Technical Field

[0001] This invention relates to the field of power line communication system technology, and in particular to a clock source frequency offset correction method for an isolated sampling device. Background Technology

[0002] In low-voltage distribution area micro-current communication, current sampling is designed using a metering ADC cross-sampling chip. Different schemes of ADC cross-sampling chips have different sampling frequencies and large differences in sampling frequency deviation, which have a significant impact on the performance of low-voltage distribution area micro-current communication and greatly affect the application effect of low-voltage distribution area micro-current communication.

[0003] Low-voltage distribution area micro-current communication receiving equipment typically adopts a combination design of MCU chip and ADC AC sampling chip. The frequency deviation of the external clock source used by the MCU chip is generally within ±20ppm, which can meet the performance requirements of low-voltage distribution area micro-current communication. This provides a basis for correcting the sampling frequency and frequency deviation of the ADC AC sampling chip through the MCU chip clock source. Summary of the Invention

[0004] This invention addresses the problem of inconsistent sampling frequency and significant frequency deviation between the ADC cross-sampling chip and the reference frequency in low-voltage distribution network micro-current communication systems. It provides a clock source frequency deviation correction method for isolated sampling devices. This method uses an MCU chip to generate a second timer, recording the number of ADC cross-sampling chip sampling points per second. The actual sampling frequency is calculated by repeatedly averaging the data. The MCU chip then calculates Gardner interpolation algorithm parameters based on the actual sampling frequency and uses the Gardner interpolation algorithm to interpolate the actual sampled data to the reference frequency sampling data, thus resolving the frequency deviation problem of the sampling device.

[0005] A method for correcting the clock source frequency offset of an isolated sampling device, characterized by comprising the following steps:

[0006] Step 1: The MCU chip drives the second timer with an external clock source, and the reference sampling frequency is denoted as F. c .

[0007] Step 2: After the second timer interrupt is triggered, the MCU chip generates a record of the number of sampling points of the ADC sampling chip in the previous second.

[0008] Step 3: The MCU chip generates N records of the number of sampling points of the ADC chip in the previous second after the second timer interrupt is triggered.

[0009] Step 4: The MCU chip calculates the actual sampling frequency F of the ADC based on the N sampling point records. re .

[0010] Step 5: The MCU chip uses the actual sampling frequency F reCalculate the parameters I of the Gardner interpolation algorithm x .

[0011] Step 6: The MCU chip uses I... x Using the Gardner interpolation algorithm, F re The sampled data is interpolated at a sampling frequency of F. c The data.

[0012] Step 7: Repeat steps 1 to 6 to correct the actual sampling frequency of the ADC cross-sampling chip in real time.

[0013] Furthermore, in step 2, the MCU chip uses a second timer to count the number of sampling points per second of the ADC sampling chip.

[0014] Furthermore, in step 3, N ranges from 1 to 60, meaning that the number of sampling points of the ADC cross-sampling chip is recorded 1 to 60 times using a second timer.

[0015] Furthermore, in step 4, the MCU chip calculates the actual sampling frequency F of the ADC cross-sampling chip using multiple statistical sampling point counts. re The calculation formula is: In the formula, N represents the number of statistical counts, and d j This represents the number of sampling points per second.

[0016] Furthermore, in step 5, the Gardner interpolation parameter I... x The calculation formula is: G = gcd(10 * F) re ,10*F c ), I x =(10*F c -10*F re ) / G, where F re F is the actual sampling frequency. c The reference sampling frequency is 10, the amplification factor is 10, and G is 10 times F. re and 10 times F c The greatest common divisor.

[0017] Furthermore, in step 6, the interpolation formula used by the Gardner interpolation algorithm is: In the formula D outi For the interpolated sampling points, D 1i D 2i D 3i and D 4i These are four consecutive pre-interpolation sampling points, where i is the interpolation data index, and k, k1, and k2 are intermediate variables that have no practical meaning. The initial values ​​of i, k1, and k2 are 0.

[0018] Furthermore, in step 6, during the MCU chip interpolation process, F re When changes occur, the interpolation parameters need to be updated again when k is 0 to ensure that each new actual sampling frequency interpolation uses the original data as the starting point, avoiding interpolation data deviation and obtaining the sampling data of the reference sampling frequency.

[0019] Furthermore, in step 7, the MCU chip generates N sampling records by deleting the first second sampling record and writing the latest second sampling record in a loop, and determines the actual sampling frequency time of the updated ADC sampling chip based on the set sampling frequency time interval.

[0020] The beneficial technical effects of this invention are as follows: The MCU chip records the number of sampling points per second of the ADC sampling chip through a second timer, obtains the actual sampling rate of the ADC by averaging multiple times, and then uses an interpolation algorithm to interpolate the sampling data to the sampling data of the reference sampling frequency. This solves the problem that the actual sampling frequency of the ADC sampling chip is inconsistent with the reference sampling frequency and that the sampling frequency deviation is large, and has good engineering applicability. Attached Figure Description

[0021] Figure 1 This is the overall flowchart of the sampling frequency correction scheme of the present invention.

[0022] Figure 2 This is a schematic diagram of the sampling system scheme in an embodiment of the present invention.

[0023] Figure 3 This is a diagram of the original sampling data of the ADC cross-sampling chip in an embodiment of the present invention.

[0024] Figure 4 This is a data graph after interpolation according to the calibrated sampling frequency in an embodiment of the present invention.

[0025] Figure 5 This is a data graph after interpolation according to the corrected sampling frequency in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and do not limit the scope of the invention.

[0027] Combined with appendix Figure 1 and attached Figure 2 A method for correcting the clock source frequency offset of an isolated sampling device, the steps of which are as follows:

[0028] Step 1: The MCU chip controls the ADC sampling chip to sample analog signals. A schematic diagram of the sampling system is attached. Figure 2As shown, the MCU chip uses an external crystal oscillator as its clock source, with a sampling frequency deviation within ±20ppm. The ADC cross-sampling chip uses an internal crystal oscillator for sampling, with a calibrated sampling frequency of 4687.5Hz and a sampling frequency deviation within ±5000ppm.

[0029] Step 2: The MCU chip drives the second timer with an external clock source, and the reference sampling frequency F c Take 5000Hz, and when the interrupt is triggered, generate a record of the number of sampling points of the ADC sampling chip in the previous second.

[0030] Step 3: The MCU chip generates a record of the number of sampling points of the ADC chip in the previous second after 32 interrupt triggers. The test signal is a 50Hz power frequency voltage generated by a standard source.

[0031] Step 4: The MCU chip calculates the actual sampling frequency F based on the 32 sampling points recorded. re The calculation formula is: In the formula, the number of statistical iterations N is taken as 32, and d j F is the number of sampling points per second. re It is 4687.3Hz.

[0032] Step 5: The MCU calculates the actual sampling frequency F. re and reference sampling frequency F c Calculate the parameters I of the Gardner interpolation algorithm x The calculation formula is: G = gcd(10 * F) re ,10*F c ), I x =(10*F c -10*F re ) / G, where 10 is the magnification factor and G is 10 times F. re and 10 times F c The greatest common divisor is 10 times F. re and 10 times F c The greatest common divisor G is 1, corresponding to the parameter I in the Gardner interpolation algorithm. x The value is 3127. Calculate 10 times the calibration frequency of 4687.5Hz and 10 times F. c The greatest common divisor G is 3125, corresponding to the parameter I in the Gardner interpolation algorithm. x The value is 1.

[0033] Step 6: Obtain the raw sampling data from the ADC acquisition chip, as shown in the attached image. Figure 3 As shown.

[0034] Step 7: The MCU uses the Gardner interpolation algorithm to interpolate the original sampling data from the ADC acquisition chip to a value based on F. cThe Gardner interpolation algorithm uses the following interpolation formula for the sampled data:

[0035] In the formula D outi For the interpolated sampling points, D 1i D 2i D 3i and D 4i These are four consecutive pre-interpolation sampling points, where i is the interpolation data index, and k, k1, and k2 are intermediate variables that have no practical meaning. The initial values ​​of i, k1, and k2 are 0.

[0036] Appendix Figure 4 The data obtained by interpolation at the calibrated sampling frequency of 4687.5Hz shows that the amplitude changes by 14.295V and 6.758V from sampling point 1 to sampling point 2 and sampling point 5001, respectively. The interpolated data frequency and F are calculated. c In comparison, it shifted by -95ppm.

[0037] Appendix Figure 5 The data obtained by interpolation based on the actual sampling frequency of 4687.3Hz shows that the amplitude changes by 14.294V and 1.87V from sampling point 1 to sampling point 2 and sampling point 5001, respectively. The interpolated data frequency and F are then calculated. c In comparison, it shifted by -27ppm.

[0038] Comparison Appendix Figure 4 and attached Figure 5 The frequency offset results show that the MCU chip can correct the sampling frequency by calculating the actual sampling frequency of the ADC sampling chip, thereby obtaining a smaller sampling frequency offset.

[0039] Furthermore, in step 4, the MCU generates 32 sampling records by deleting the first second sampling record and writing the latest second sampling record in a loop, calculating the actual sampling frequency every 10 seconds, and then updating the Gardner interpolation algorithm parameter I. x .

[0040] Furthermore, in step 7, when the MCU performs interpolation, if the calculated actual sampling frequency F of the ADC... re After a change, the interpolation parameters need to be updated again when k is 0 to ensure that each new sampling frequency interpolation is performed using the original data as the starting point, thus avoiding deviations in the interpolated data.

[0041] The above embodiments are descriptions of specific implementations of the present invention, and not limitations thereof. Those skilled in the art can make various modifications and changes without departing from the spirit and scope of the present invention to obtain corresponding equivalent technical solutions. Therefore, all equivalent technical solutions should be included in the patent protection scope of the present invention.

Claims

1. A method for correcting the clock source frequency offset of an isolated sampling device, characterized in that... Includes the following steps: Step 1: The MCU chip drives the second timer with an external clock source, and the reference sampling frequency is denoted as F. c ; Step 2: After the second timer interrupt is triggered, the MCU chip generates a record of the number of sampling points of the ADC sampling chip in the previous second; Step 3: The MCU chip generates N records of the number of sampling points of the ADC chip in the previous second after the second timer interrupt is triggered, where N ranges from 1 to 60. Step 4: The MCU chip calculates the actual sampling frequency F of the ADC based on the N sampling point records. re The calculation formula is: In the formula, N represents the number of statistical counts, and d j The number of sampling points per second; Step 5: The MCU chip uses the actual sampling frequency F re Calculate the parameters I of the Gardner interpolation algorithm x The calculation formula is: G = gcd(10 * F) re ,10*F c ) and I x =(10*F c -10*F re ) / G, where F re F is the actual sampling frequency. c The reference sampling frequency is 10, the amplification factor is 10, and G is 10 times F. re and 10 times F c The greatest common divisor; Step 6: The MCU chip uses interpolation parameter I... x The Gardner interpolation algorithm is used to interpolate F re The sampled data is interpolated at a sampling frequency of F. c The data, the interpolation formula is: In the formula D outi For the interpolated sampling points, D 1i D 2i D 3i and D 4i These are four consecutive pre-interpolation sampling points, where i is the interpolation data index, and k, k1, and k2 are intermediate variables that have no practical meaning. The initial values ​​of i, k1, and k2 are 0. Step 7: Repeat steps 1 to 6. The MCU chip generates N sampling records by deleting the first second sampling record and writing the latest second sampling record. It corrects the sampling frequency of the ADC cross-sampling chip in real time and determines the actual sampling frequency time of the ADC cross-sampling chip based on the set sampling frequency time interval.

2. The clock source frequency offset correction method for an isolated sampling device according to claim 1, characterized in that: In step 6, during the MCU chip interpolation process, F re When changes occur, the interpolation parameters need to be updated again when k is 0 to ensure that the actual sampling frequency interpolation is based on the original data each time, thus avoiding interpolation data deviation and confirming the obtained reference sampling frequency data.

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