Pixel circuit and display device
By writing a reset voltage affected by a jump to the first electrode of the light-emitting element in the OLED display, and using polycrystalline silicon oxide thin-film transistors to compensate for brightness differences, the problem of uneven brightness under the LTPO 2.0 frequency conversion function is solved, and a more uniform display effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2023-08-25
- Publication Date
- 2026-07-24
AI Technical Summary
In OLED displays, the LTPO 2.0 high-precision frequency conversion function causes pixels to reset when the data signal changes, resulting in brightness differences and uneven brightness of the display screen, thus creating a split-screen phenomenon.
By writing a reset voltage affected by the jump to the first electrode of the light-emitting element, the brightness difference of the first electrode of the light-emitting element caused by voltage refresh is compensated by the first reset circuit and the reset configuration circuit, and voltage transmission is achieved by using a polycrystalline silicon oxide thin film transistor.
It eliminates brightness differences in the display screen, improves display uniformity, reduces screen splitting, and optimizes the display effect.
Smart Images
Figure CN117037673B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a pixel circuit and a display device. Background Technology
[0002] In existing OLED (Organic Electroluminescence Display) products, to provide customers with more efficient responsiveness, the high-precision frequency conversion function of LTPO2.0 (Low Temperature Polycrystalline Oxide) is typically used. Under this function, pixels need to undergo multiple anode resets within a single frame. If pixels reset during data signal transitions, it will lead to differences in pixel brightness, causing uneven brightness on the display and resulting in screen splitting. Summary of the Invention
[0003] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a pixel circuit and display device, which can compensate for the brightness difference of the first electrode of the light-emitting element caused by voltage refresh by writing a reset voltage affected by the jump to the first electrode of the light-emitting element.
[0004] In a first aspect, this application provides a pixel circuit, comprising:
[0005] The main driving circuit is electrically connected to the data signal terminal and the first electrode of the light-emitting element, respectively, and is configured to generate a driving current according to the data signal of the data signal terminal to control the light-emitting element to emit light.
[0006] The first reset circuit is electrically connected to the reset configuration circuit and the first electrode of the light-emitting element, respectively. The connection point of the first reset circuit and the reset configuration circuit and the data signal line connected to the data signal terminal form a first coupling capacitor. The first reset circuit is configured to write the signal of the connection point to the first electrode of the light-emitting element in response to the signal of the first reset terminal, so as to reset the first electrode of the light-emitting element.
[0007] The reset configuration circuit is electrically connected to the first reset voltage terminal and is configured to transmit the first reset voltage of the first reset voltage terminal to the connection point. The voltage of the connection point changes with the jump of the data signal under the action of the first coupling capacitor.
[0008] According to the pixel circuit of this application, the main driving circuit is used to control the light-emitting element to emit light, and the first reset circuit and the reset configuration circuit are used to reset the light-emitting element. When the light-emitting element is reset, if the data signal transmission of the data signal line changes, the voltage of the first electrode of the light-emitting element and the connection point of the first reset circuit and the reset configuration circuit are affected. Therefore, by writing the reset voltage affected by the change to the first electrode of the light-emitting element, the brightness difference of the first electrode of the light-emitting element caused by voltage refresh can be compensated.
[0009] According to one embodiment of this application, the reset configuration circuit includes a first transistor electrically connected between a first reset circuit and a first reset voltage terminal to transmit the first reset voltage to the connection point.
[0010] According to one embodiment of this application, the gate and drain of the first transistor are electrically connected to each other and electrically connected to the first reset voltage terminal, and the source of the first transistor is electrically connected to the first reset circuit.
[0011] According to one embodiment of this application, the first transistor is an N-type transistor.
[0012] According to one embodiment of this application, the first electrode of the light-emitting element is the anode of the light-emitting element.
[0013] According to one embodiment of this application, the main drive circuit includes:
[0014] The driving sub-circuit includes a first terminal, a second terminal, and a control terminal;
[0015] The data writing circuit is electrically connected to the first terminal and the data signal terminal of the driver sub-circuit, respectively, and is configured to write the data signal from the data signal terminal to the first terminal of the driver sub-circuit in response to the signal from the scan control terminal.
[0016] The compensation circuit is electrically connected to the second terminal of the driving sub-circuit and the control terminal of the driving sub-circuit, respectively, and is configured to perform threshold compensation on the driving sub-circuit in response to the signal of the compensation signal terminal.
[0017] The first light-emitting control circuit is electrically connected to the first terminal and the driving voltage terminal of the driving sub-circuit, respectively, and is configured to respond to the signal of the light-emitting control terminal to realize the connection between the driving sub-circuit and the driving voltage terminal to be turned on or off.
[0018] The second light-emitting control circuit is electrically connected to the second terminal of the driving sub-circuit and the first electrode of the light-emitting element, respectively, and is configured to respond to the signal of the light-emitting control terminal to realize the connection between the driving sub-circuit and the light-emitting element to be turned on or off.
[0019] The second reset circuit is electrically connected to the second terminal and the second reset voltage terminal of the driving sub-circuit, respectively, and is configured to transmit the second reset voltage of the second reset voltage terminal to the second terminal of the driving sub-circuit in response to the signal of the second reset terminal.
[0020] According to one embodiment of this application, the first reset voltage is greater than the second reset voltage.
[0021] According to one embodiment of this application, the main drive circuit further includes:
[0022] The third reset circuit is connected to the first terminal and the third reset voltage terminal of the driver sub-circuit, respectively, and is configured to transmit the third reset voltage of the third reset voltage terminal to the first terminal of the driver sub-circuit in response to the signal of the first reset terminal.
[0023] According to one embodiment of this application, the second reset circuit includes a second transistor, and the compensation circuit includes a third transistor. Both the second and third transistors are polysilicon oxide thin-film transistors, and the active layer types of the second and third transistors are different from the active layer types of the transistors included in at least one of the driver sub-circuit, the data writing circuit, the first light-emitting control circuit, and the second light-emitting control circuit.
[0024] According to one embodiment of this application, the reset configuration circuit includes a first transistor, the data writing circuit includes a fourth transistor, the driving sub-circuit includes a fifth transistor, the first light-emitting control circuit includes a sixth transistor, the second light-emitting control circuit includes a seventh transistor, the first reset circuit includes an eighth transistor, and the main driving circuit further includes a ninth transistor and a first capacitor.
[0025] The gate of the fourth transistor is electrically connected to the scan control terminal, the first terminal of the fourth transistor is electrically connected to the data signal terminal, and the second terminal of the fourth transistor is electrically connected to the second terminal of the fifth transistor.
[0026] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the driving voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor.
[0027] The first terminal of the first capacitor is electrically connected to the driving voltage terminal, and the second terminal of the first capacitor is electrically connected to the gate of the fifth transistor.
[0028] The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element.
[0029] The gate of the eighth transistor is electrically connected to the first reset terminal, the first terminal of the eighth transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the eighth transistor is electrically connected to the second terminal of the seventh transistor.
[0030] The first terminal and the gate of the first transistor are electrically connected, and are also electrically connected to the first reset voltage terminal;
[0031] The gate of the ninth transistor is electrically connected to the first reset terminal, the first terminal of the ninth transistor is electrically connected to the second terminal of the fifth transistor, and the second terminal of the ninth transistor is electrically connected to the third reset voltage terminal.
[0032] The gate of the second transistor is electrically connected to the second reset terminal, the first terminal of the second transistor is electrically connected to the second reset voltage terminal, and the second terminal of the second transistor is electrically connected to the first terminal of the fifth transistor.
[0033] The gate of the third transistor is electrically connected to the compensation signal terminal, the first terminal of the third transistor is electrically connected to the first terminal of the fifth transistor, and the second terminal of the third transistor is electrically connected to the gate of the fifth transistor.
[0034] According to one embodiment of this application, the fourth to ninth transistors are all polycrystalline silicon thin-film transistors.
[0035] Secondly, this application provides a display device including a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel circuit and a light-emitting element as described above.
[0036] According to the display device of this application, by writing a reset voltage affected by the jump to the first electrode of each light-emitting element, the brightness difference of the first electrode of the light-emitting element caused by voltage refresh can be compensated, so that the display device is less likely to have screen splitting phenomenon when displaying.
[0037] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0038] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0039] Figure 1 This is a schematic diagram of a pixel circuit.
[0040] Figure 2 This is a schematic diagram of a data signal transition;
[0041] Figure 3 This is a schematic diagram of the reset point voltage change of a light-emitting element;
[0042] Figure 4 This is a schematic diagram illustrating changes in display screen brightness.
[0043] Figure 5This is a schematic diagram of the pixel circuit provided in an embodiment of this application;
[0044] Figure 6 This is a schematic diagram of the reset point voltage change of the light-emitting element provided in the embodiments of this application.
[0045] Figure label:
[0046] Pixel circuit 100, main driving circuit 110, driving sub-circuit 111, data writing circuit 112, compensation circuit 113, first light-emitting control circuit 114, second light-emitting control circuit 115, second reset circuit 116, third reset circuit 117, first reset circuit 120, reset configuration circuit 130, light-emitting element 200, first to ninth transistors T1 to T9. Detailed Implementation
[0047] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0048] In the following description, a "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "coupled to" or "connected to" another element, or when an element / circuit is said to be "coupled at" or "connected at" two nodes, it can be directly coupled to or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.
[0049] In the description, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such numerical descriptors can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0050] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0051] In related technologies, to achieve high-precision frequency conversion, displays need to reset the light-emitting element multiple times within a single frame to enable rapid switching of refresh rates. However, due to the coupling capacitance Cd between the reset point of the light-emitting element and the data signal line, voltage changes on the data signal line can be coupled into the reset point of the light-emitting element during data signal transitions, resulting in a replication distribution phenomenon that follows the reset.
[0052] As an example, refer to Figure 1 , Figure 1 A pixel circuit from a related art is illustrated. In this example, the reset point of the light-emitting element 200 is electrically connected to node N4 of the anode. When the reset circuit at node N4 is turned on, a reset voltage is written to node N4.
[0053] Reference Figure 2 When the data signal changes, its voltage Data will jump up or down. Because there is a coupling capacitance Cd between node N4 and the data signal line, when the data signal changes, the voltage of node N4 will rise with the rise of the data signal or fall with the fall.
[0054] like Figure 3 As shown, during the normal light-emitting phase, if the data signal changes, the potential at point N4 will be leveled off, and the brightness will not be affected. However, during the reset phase, if the data signal changes, the voltage jump of node N4 will be refreshed by the voltage at the reset voltage terminal Vint1.
[0055] Figure 4 As shown, during Data writing, the voltage at the reset point of the light-emitting element 200 in that column of pixels increases with the Data jump, resulting in increased brightness. If some pixels are reset, the voltage at the reset point of the reset light-emitting element 200 is pulled down. Therefore, in the entire display screen, some pixels do not reset, and the voltage of their corresponding N4 node rises; some pixels reset, and the voltage of their corresponding N4 node is the voltage of the reset voltage terminal Vint1. Due to the different voltages, the brightness of the light-emitting elements differs, resulting in a split-screen phenomenon. After the Data jumps down, the voltage loop at the reset point of the light-emitting element 200 in that column of pixels results in lower overall brightness for the reset pixels.
[0056] This application proposes a pixel circuit, in which a main driving circuit is used to control the light-emitting element to emit light, and a first reset circuit and a reset configuration circuit are used to reset the light-emitting element. When the light-emitting element is reset, if the data signal transmission of the data signal line changes, the voltage of the first electrode of the light-emitting element and the connection point of the first reset circuit and the reset configuration circuit are affected. Therefore, by writing the reset voltage affected by the change to the first electrode of the light-emitting element, the brightness difference of the first electrode of the light-emitting element caused by voltage refresh can be compensated.
[0057] Reference Figure 5 One embodiment of this application proposes a pixel circuit 100, which includes a main driving circuit 110, a first reset circuit 120, and a reset configuration circuit 130. The main drive circuit 110 is electrically connected to the data signal terminal Vdata and the first electrode of the light-emitting element 200, and is configured to generate a drive current according to the data signal of the data signal terminal Vdata to control the light-emitting element 200 to emit light; the first reset circuit 120 is electrically connected to the reset configuration circuit 130 and the first electrode of the light-emitting element 200, and the connection point N5 of the first reset circuit 120 and the reset configuration circuit 130 forms a first coupling capacitor Cr with the data signal line connected to the data signal terminal Vdata. The first reset circuit 120 is configured to write the signal of the connection point N5 to the first electrode of the light-emitting element 200 in response to the signal of the first reset terminal H-out, so as to reset the first electrode of the light-emitting element 200; the reset configuration circuit 130 is electrically connected to the first reset voltage terminal Vint1, and is configured to transmit the first reset voltage of the first reset voltage terminal Vint1 to the connection point N5. The voltage of the connection point N5 changes with the jump of the data signal under the action of the first coupling capacitor Cr.
[0058] In this embodiment, the reset point of the light-emitting element 200 is the first electrode of the light-emitting element 200, namely node N4. Node N4 and the data signal line form a second coupling capacitor Cd.
[0059] The light-emitting element 200 includes a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode. The second electrode of the light-emitting element 200 is electrically connected to a voltage terminal VSS. When the driving current generated by the pixel circuit 100 flows through the light-emitting element 200, the light-emitting layer of the light-emitting element 200 emits light with a brightness corresponding to the magnitude of the driving current.
[0060] In some embodiments, the light-emitting element 200 may be a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED), etc.
[0061] The light-emitting layer of the light-emitting element 200 may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. The light-emitting element 200 has a light-emitting threshold voltage, and emits light when the voltage between the first electrode and the second electrode of the light-emitting element 200 is greater than or equal to the light-emitting threshold voltage.
[0062] In some embodiments, the first electrode of the light-emitting element 200 is an anode, and the second electrode of the light-emitting element 200 is a cathode. The first reset circuit 120 and the reset configuration circuit 130 are used to perform an anode reset on the light-emitting element 200.
[0063] In this embodiment, the first reset terminal H-out is used to receive the first reset signal. The first reset circuit 120 enters the on state when it receives the first reset signal and enters the off state when it does not receive the first reset signal. The reset configuration circuit 130 can enter the on state in response to a control signal or remain in the on state continuously.
[0064] Reference Figure 6 During the normal light emission phase, when the data signal changes, the voltage effect of the second coupling capacitor Cd on node N4 is both pull-up and pull-down. The voltage change of node N5 does not affect the voltage of node N4 when the first reset circuit 120 is in the off state, so the average brightness remains unchanged.
[0065] During the reset phase, both the first reset circuit 120 and the reset configuration circuit 130 are in the on state. When the data signal jumps up, the second coupling capacitor Cd pulls up the voltage of node N4, and at the same time, the first coupling capacitor Cr pulls up the voltage of node N5. The voltage of node N5 is N5` = V1 + ΔV, where V1 is the first reset voltage of the first reset voltage terminal Vint1, and ΔV is the voltage pulled up by the first coupling capacitor Cr to node N5. At this time, the voltage written from node N4 to node N5 is N4` = V1 + ΔV.
[0066] In related technologies, when the data signal jumps up or down during the reset phase, node N4 is refreshed by the first reset voltage V1, making the voltage N4' of node N4 equal to V1. Therefore, this embodiment retains the effect of data signal transitions on the light-emitting element 200, eliminating brightness differences in the display screen.
[0067] In some embodiments, the reset configuration circuit 130 includes a first transistor T1, which is electrically connected between the first reset circuit 120 and the first reset voltage terminal Vint1 to transmit the first reset voltage V1 to the connection point N5.
[0068] In this embodiment, a single transistor is used to transmit voltage. This method is simple in structure, low in cost, occupies little space, has little impact on the overall structure of the pixel circuit 100, and does not affect the size of the display bezel.
[0069] In some embodiments, the gate and drain of the first transistor T1 are electrically connected to each other and electrically connected to the first reset voltage terminal Vint1, and the source of the first transistor T1 is electrically connected to the first reset circuit 120.
[0070] In this embodiment, when a first reset voltage V1 is applied to the first reset voltage terminal Vint1, the first transistor T1 enters the conducting state, and the voltage at node N5 rises to N5` = V1 - Vth, where Vth is the on-state voltage drop of the first transistor T1. If the data signal jumps upward, the voltage at node N5 is N5` = V1 - Vth + ΔV; if the data signal jumps downward, the voltage at node N5 is N5` = V1 - Vth + ΔV.
[0071] Therefore, the first transistor T1 does not require additional signal lines for control, resulting in a simple structure and a small footprint.
[0072] In other embodiments, the gate of the first transistor T1 can be connected to a signal line to receive a control signal. The control signal can control the first transistor T1 to turn on when the light-emitting element 200 needs to be reset, and before the data signal transition, so that when the data signal transitions, the voltage of node N5 rises or falls by ΔV based on the first reset voltage V1.
[0073] In some embodiments, the first transistor T1 is an N-type transistor.
[0074] It is understandable that the conduction condition of the first transistor T1 in the N-type circuit is that the voltage difference between the gate voltage and the source voltage is greater than the threshold voltage. Therefore, when the first reset voltage Vint1 is first applied, the first transistor T1 turns on, and the voltage at node N5 rises to V1 = Vth. When the data signal jumps up, the voltage at node N5 rises to N5` = V1 - Vth + ΔV. At this time, the first transistor T1 turns off to prevent the voltage at node N5 from being pulled down.
[0075] As an example, continuing with reference to 5, the main driving circuit 110 includes a driving sub-circuit 111, a data writing circuit 112, a compensation circuit 113, a first light-emitting control circuit 114, a second light-emitting control circuit 115, and a second reset circuit 116. The driving sub-circuit 111 includes a first terminal, a second terminal, and a control terminal. The data writing circuit 112 is electrically connected to the first terminal and the data signal terminal Vdata of the driving sub-circuit 111, respectively, and is configured to write the data signal of the data signal terminal Vdata into the first terminal of the driving sub-circuit 111 in response to the signal of the scan control terminal G-out. The compensation circuit 113 is electrically connected to the second terminal and the control terminal of the driving sub-circuit 111, respectively, and is configured to perform threshold compensation on the driving sub-circuit 111 in response to the signal of the compensation signal terminal E-out. The light-emitting control circuit 114 is electrically connected to the first terminal and the driving voltage terminal VDD of the driving sub-circuit 111, and is configured to turn on or off the connection between the driving sub-circuit 111 and the driving voltage terminal VDD in response to the signal of the light-emitting control terminal EM; the second light-emitting control circuit 115 is electrically connected to the second terminal of the driving sub-circuit 111 and the first electrode of the light-emitting element 200, and is configured to turn on or off the connection between the driving sub-circuit 111 and the light-emitting element 200 in response to the signal of the light-emitting control terminal EM; the second reset circuit 116 is electrically connected to the second terminal and the second reset voltage terminal Vint2 of the driving sub-circuit 111, and is configured to transmit the second reset voltage V2 of the second reset voltage terminal Vint2 to the second terminal of the driving sub-circuit 111 in response to the signal of the second reset terminal P-out.
[0076] In this embodiment, the control terminal of the drive sub-circuit 111 is electrically connected to the first node N1, the first terminal of the drive sub-circuit 111 is electrically connected to the second node N3, and the second terminal of the drive sub-circuit 111 is electrically connected to the third node N3.
[0077] The operation of the pixel circuit 100 is as follows: During the reset phase, the first reset circuit 120, the reset configuration circuit 130, the compensation circuit 113, and the second reset circuit 116 are turned on, while the remaining circuits are turned off, resetting the second node N2, the third node N3, and the fourth node N4; During the charging phase, the data writing circuit 112 and the compensation circuit 113 are turned on, while the remaining circuits are turned off, and the data signal is written to the first node N1; During the light emission phase, the first light emission control circuit 114 and the second light emission control circuit 115 are turned on, while the remaining circuits are turned off, and the current from the driving voltage terminal VDD flows into the light emission element 200, and the current magnitude is controlled by the driving sub-circuit 111, causing the light emission element 200 to emit light.
[0078] The control terminal of the driving sub-circuit 111 is electrically connected to the third node N3 through the compensation circuit 113, so that there is only one leakage path at the control terminal of the driving sub-circuit 111. Due to the reduction of leakage paths, the voltage leakage at the control terminal of the driving sub-circuit 122 is less during the light-emitting stage, the brightness difference between the front and back of a frame is reduced, the flicker problem is optimized, and the uniformity of the displayed image and the display quality of the display panel including the pixel circuit 100 are improved.
[0079] It should be noted that the main drive circuit 110 in this embodiment is only an example, and the pixel circuit 100 of this application can also adopt other main drive circuits 110. For example, multiple leakage paths can be set at the control terminal of the drive sub-circuit 111.
[0080] In some embodiments, the first reset voltage V1 is greater than the second reset voltage V2.
[0081] Therefore, by increasing the voltage of the first reset voltage V1, the charge carriers inside the light-emitting element 200 are reset, reducing the defects of charge carriers, increasing the stability of the device, and further improving the problem of screen flicker.
[0082] In some embodiments, the main drive circuit 110 further includes a third reset circuit 117, which is connected to the first terminal and the third reset voltage terminal Vint3 of the drive sub-circuit 111, and is configured to transmit the third reset voltage V3 of the third reset voltage terminal Vint3 to the first terminal of the drive sub-circuit 111 in response to the signal of the first reset terminal H-out.
[0083] In this embodiment, the third reset circuit 117 is used to reset the first terminal of the driving sub-circuit 111. During the reset phase, the third reset circuit 117 is also turned on to reset the second node, thereby improving the reliability of the pixel circuit 100.
[0084] In some embodiments, the second reset circuit 116 includes a second transistor T2, and the compensation circuit 113 includes a third transistor T3. Both the second transistor T2 and the third transistor T3 are polysilicon oxide thin film transistors, and the active layer types of the second transistor T2 and the third transistor T3 are different from the active layer types of the transistors included in at least one of the driving sub-circuit 111, the data writing circuit 112, the first light-emitting control circuit 114, and the second light-emitting control circuit 115.
[0085] In this embodiment, the second transistor T2 and the third transistor T3 can be low-temperature polycrystalline oxide (LTPO) thin-film transistors. Low-temperature polycrystalline silicon (LTPS) technology is a manufacturing process for next-generation thin-film transistor liquid crystal displays (TFT LCDs). During the LTPS packaging process, an excimer laser is used as a heat source. After passing through a transmission system, the laser beam generates a uniformly distributed energy beam and is projected onto an amorphous silicon glass substrate. When the amorphous silicon glass substrate absorbs the energy of the excimer laser, it transforms into a polycrystalline silicon structure. Because the entire process is completed below 500-600 degrees Celsius, compared to the temperatures exceeding 1000 degrees Celsius required in traditional polycrystalline silicon processes, it is called the low-temperature polycrystalline silicon process.
[0086] In the field of display technology, Low Temperature Polysilicon (LTPS) and oxide (e.g., Indium Gallium Zinc Oxide, IGZO) processes are two commonly used technologies for fabricating thin film transistor (TFT) array substrates. The LTPS process combines the advantages of LTPS and oxide processes, maximizing the use of the ultra-high mobility of LTPS and the low leakage current of oxides (e.g., IGZO) to achieve superior display performance.
[0087] "Active layer type" indicates the type of material used to fabricate the active layer. The active layer material can include indium gallium zinc oxide, low-temperature polycrystalline silicon, amorphous silicon (e.g., hydrogenated amorphous silicon), low-temperature polycrystalline silicon oxide, etc. For example, the active layer type of a thin-film transistor using indium gallium zinc oxide as the active layer is different from that of a thin-film transistor using low-temperature polycrystalline silicon oxide as the active layer.
[0088] In some embodiments, the pixel circuit 100 provided in this embodiment can adopt an LTPO2.0 design to achieve high-precision frequency conversion. When the pixel circuit 100 is displaying, the refresh rate can be adaptively switched according to requirements. At the same time, by setting a reset configuration circuit 130, the brightness difference caused by reset during frequency conversion switching is eliminated, thus improving the display effect.
[0089] In some embodiments, the reset configuration circuit 130 includes a first transistor T1, the data writing circuit 112 includes a fourth transistor T4, the driving sub-circuit 111 includes a fifth transistor T5, the first light-emitting control circuit 116 includes a sixth transistor T6, the second light-emitting control circuit 115 includes a seventh transistor T7, the first reset circuit 120 includes an eighth transistor T8, and the main driving circuit 110 further includes a ninth transistor T9 and a first capacitor C1.
[0090] The gate of the fourth transistor T4 is electrically connected to the scan control terminal G-out, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Vdata, and the second terminal of the fourth transistor T4 is electrically connected to the second terminal of the fifth transistor T5; the gate of the sixth transistor T6 is electrically connected to the light emission control terminal EM, the first terminal of the sixth transistor T6 is electrically connected to the driving voltage terminal VDD, and the second terminal of the sixth transistor T6 is electrically connected to the second terminal of the fifth transistor T5; the first terminal of the first capacitor C1 is electrically connected to the driving voltage terminal VDD, and the second terminal of the first capacitor C1 is electrically connected to the gate of the fifth transistor T5; the gate of the seventh transistor T7 is electrically connected to the light emission control terminal EM, the first terminal of the seventh transistor T7 is electrically connected to the first terminal of the fifth transistor T5, and the second terminal of the seventh transistor T7 is electrically connected to the first electrode of the light-emitting element 200; the gate of the eighth transistor T8 is electrically connected to the first reset terminal H-out, and the first terminal of the eighth transistor T8 is electrically connected to the first reset terminal H-out. The second terminal of transistor T1 is electrically connected to the first reset voltage terminal Vint1. The second terminal of transistor T8 is electrically connected to the second terminal of transistor T7. The first terminal and gate of transistor T1 are electrically connected and connected to the first reset voltage terminal Vint1. The gate of transistor T9 is electrically connected to the first reset terminal H-out. The first terminal of transistor T9 is electrically connected to the second terminal of transistor T5. The second terminal of transistor T9 is electrically connected to the third reset voltage terminal Vint3. The gate of transistor T2 is electrically connected to the second reset terminal P-out. The first terminal of transistor T2 is electrically connected to the second reset voltage terminal Vint2. The second terminal of transistor T2 is electrically connected to the first terminal of transistor T5. The gate of transistor T3 is electrically connected to the compensation signal terminal E-out. The first terminal of transistor T3 is electrically connected to the first terminal of transistor T5. The second terminal of transistor T3 is electrically connected to the gate of transistor T5.
[0091] In some embodiments, the first terminal of a transistor refers to the drain of the transistor, and the second terminal of the transistor refers to the source of the transistor. Specifically, the first transistor T1 and the third transistor T3 are N-type transistors, and the second transistor T2, the fourth transistor T4, through the ninth transistor T9 are P-type transistors.
[0092] In some embodiments, the fourth transistor T4 to the ninth transistor T9 are all polycrystalline silicon thin-film transistors.
[0093] In this embodiment, transistors T4 through T9 can be low-temperature polycrystalline silicon (LTPS) thin-film transistors. LTPS thin-film transistors generate less leakage current compared to LTPS thin-film transistors. Since transistors T4 through T9 are not on the leakage path, using LTPS thin-film transistors simplifies the manufacturing process.
[0094] One embodiment of this application also provides a display device. The display device includes a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel circuit 100 and a light-emitting element 200 as described above. The specific structure of the pixel circuit 100 can be referred to the foregoing embodiments, and will not be repeated here.
[0095] In some embodiments, the display device may be any product or component with display functionality, such as a mobile phone, tablet computer, television, laptop computer, digital photo frame, or navigator.
[0096] According to the display device of this application, by writing a reset voltage affected by the jump to the first electrode of each light-emitting element, the brightness difference of the first electrode of the light-emitting element caused by voltage refresh can be compensated, so that the display device is less likely to have screen splitting phenomenon when displaying.
[0097] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A pixel circuit, characterized in that, include: The main driving circuit is electrically connected to the data signal terminal and the first electrode of the light-emitting element, respectively, and is configured to generate a driving current according to the data signal of the data signal terminal to control the light-emitting element to emit light. The first reset circuit is electrically connected to the reset configuration circuit and the first electrode of the light-emitting element, respectively. The connection point of the first reset circuit and the reset configuration circuit forms a first coupling capacitor with the data signal line connected to the data signal terminal. The first reset circuit is configured to write the signal of the connection point to the first electrode of the light-emitting element in response to the signal of the first reset terminal, so as to reset the first electrode of the light-emitting element. A reset configuration circuit is electrically connected to a first reset voltage terminal and is configured to transmit a first reset voltage from the first reset voltage terminal to the connection point during the reset phase. The voltage at the connection point changes with the jump of the data signal under the action of the first coupling capacitor. The first electrode of the light-emitting element forms a second coupling capacitor with the data signal line, and the first electrode of the light-emitting element changes with the jump of the data signal under the action of the second coupling capacitor.
2. The pixel circuit according to claim 1, characterized in that, The reset configuration circuit includes a first transistor, which is electrically connected between the first reset circuit and the first reset voltage terminal to transmit the first reset voltage to the connection point.
3. The pixel circuit according to claim 2, characterized in that, The gate and drain of the first transistor are electrically connected to each other and electrically connected to the first reset voltage terminal, and the source of the first transistor is electrically connected to the first reset circuit.
4. The pixel circuit according to claim 3, characterized in that, The first transistor is an N-type transistor.
5. The pixel circuit according to any one of claims 1-4, characterized in that, The first electrode of the light-emitting element is the anode of the light-emitting element.
6. The pixel circuit according to any one of claims 1-4, characterized in that, The main drive circuit includes: The driving sub-circuit includes a first terminal, a second terminal, and a control terminal; The data writing circuit is electrically connected to the first terminal of the driving sub-circuit and the data signal terminal respectively, and is configured to write the data signal of the data signal terminal into the first terminal of the driving sub-circuit in response to the signal of the scan control terminal. The compensation circuit is electrically connected to the second terminal of the driving sub-circuit and the control terminal of the driving sub-circuit, respectively, and is configured to perform threshold compensation on the driving sub-circuit in response to the signal of the compensation signal terminal. The first light-emitting control circuit is electrically connected to the first terminal and the driving voltage terminal of the driving sub-circuit, respectively, and is configured to respond to the signal of the light-emitting control terminal to realize the connection between the driving sub-circuit and the driving voltage terminal to be turned on or off. The second light-emitting control circuit is electrically connected to the second terminal of the driving sub-circuit and the first electrode of the light-emitting element, respectively, and is configured to respond to the signal of the light-emitting control terminal to realize the connection between the driving sub-circuit and the light-emitting element being turned on or off. The second reset circuit is electrically connected to the second terminal and the second reset voltage terminal of the driving sub-circuit, respectively, and is configured to transmit the second reset voltage of the second reset voltage terminal to the second terminal of the driving sub-circuit in response to a signal from the second reset terminal.
7. The pixel circuit according to claim 6, characterized in that, The first reset voltage is greater than the second reset voltage.
8. The pixel circuit according to claim 6, characterized in that, The main drive circuit also includes: The third reset circuit is connected to the first terminal and the third reset voltage terminal of the driving sub-circuit, respectively, and is configured to transmit the third reset voltage of the third reset voltage terminal to the first terminal of the driving sub-circuit in response to a signal from the first reset terminal.
9. The pixel circuit according to claim 6, characterized in that, The second reset circuit includes a second transistor, and the compensation circuit includes a third transistor. Both the second transistor and the third transistor are polysilicon oxide thin-film transistors, and the active layer type of the second transistor and the third transistor is different from the active layer type of the transistors included in at least one of the driving sub-circuit, the data writing circuit, the first light-emitting control circuit, and the second light-emitting control circuit.
10. The pixel circuit according to claim 9, characterized in that, The reset configuration circuit includes a first transistor, the data writing circuit includes a fourth transistor, the driving sub-circuit includes a fifth transistor, the first light-emitting control circuit includes a sixth transistor, the second light-emitting control circuit includes a seventh transistor, the first reset circuit includes an eighth transistor, and the main driving circuit further includes a ninth transistor and a first capacitor. The gate of the fourth transistor is electrically connected to the scan control terminal, the first terminal of the fourth transistor is electrically connected to the data signal terminal, and the second terminal of the fourth transistor is electrically connected to the second terminal of the fifth transistor. The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the driving voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor. The first terminal of the first capacitor is electrically connected to the driving voltage terminal, and the second terminal of the first capacitor is electrically connected to the gate of the fifth transistor. The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element. The gate of the eighth transistor is electrically connected to the first reset terminal, the first terminal of the eighth transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the eighth transistor is electrically connected to the second terminal of the seventh transistor. The first terminal and the gate of the first transistor are electrically connected, and are also electrically connected to the first reset voltage terminal; The gate of the ninth transistor is electrically connected to the first reset terminal, the first terminal of the ninth transistor is electrically connected to the second terminal of the fifth transistor, and the second terminal of the ninth transistor is electrically connected to the third reset voltage terminal. The gate of the second transistor is electrically connected to the second reset terminal, the first terminal of the second transistor is electrically connected to the second reset voltage terminal, and the second terminal of the second transistor is electrically connected to the first terminal of the fifth transistor. The gate of the third transistor is electrically connected to the compensation signal terminal, the first terminal of the third transistor is electrically connected to the first terminal of the fifth transistor, and the second terminal of the third transistor is electrically connected to the gate of the fifth transistor.
11. The pixel circuit according to claim 10, characterized in that, The fourth to the ninth transistors are all polycrystalline silicon thin-film transistors.
12. A display device, characterized in that, It includes a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel circuit and a light-emitting element according to any one of claims 1-11.