Integrated circuit unit, gate driving circuit and display panel

Abstract

This application provides an integrated circuit unit, a gate driving circuit, and a display panel. In the integrated circuit unit, an input control sub-circuit is connected to a strobe signal terminal, a third clock signal terminal, and a first node; the input sub-circuit is connected to a second clock signal terminal, a first node, a first-level signal terminal, and a second node; the output control sub-circuit is connected to a fourth clock signal terminal, a second node, a first-level signal terminal, and multiple third nodes; the output circuit includes multiple output sub-circuits connected to multiple third nodes, multiple fifth clock signal terminals, multiple output terminals, and a fifth-level signal terminal; a first pull-down control sub-circuit is connected to a third node, a second-level signal terminal, a third-level signal terminal, and a fourth node; a second pull-down control sub-circuit is connected to a second node, a fourth clock signal terminal, a fourth node, and a fourth-level signal terminal; and a pull-down sub-circuit is connected to a fourth node, a third node, a fourth-level signal terminal, and a third clock signal terminal.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an integrated circuit unit, a gate driving circuit, and a display panel. Background Technology

[0002] Active-matrix organic light-emitting diodes (AMOLEDs) are expected to replace LCDs as the mainstream choice for next-generation displays due to their high contrast, wide viewing angle, and fast response speed. As an OLED product, it requires EL devices (electroluminescent devices) to emit light, and the required light-emitting current needs to be provided by driving transistors. Since driving transistors vary, it is necessary to increase the consistency of device characteristics to ensure the uniformity of light emission. This requires correction through external compensation and power-off compensation.

[0003] Conventional external compensation methods have problems such as the inability to output random frame shift signals or excessively complex circuitry. Summary of the Invention

[0004] The purpose of this application is to provide a display device, a gate driving circuit, an integrated circuit unit, and a driving method thereof, which can realize random gating compensation.

[0005] According to one aspect of this application, an integrated circuit unit is provided, comprising:

[0006] The input control sub-circuit is electrically connected to the gating signal terminal, the third clock signal terminal, and the first node, and controls the first node according to the gating signal terminal and the third clock signal terminal.

[0007] The input sub-circuit is electrically connected to the second clock signal terminal, the first node, the first level signal terminal, and the second node, and controls the second node according to the second clock signal terminal and the first node.

[0008] The output control sub-circuit is electrically connected to the fourth clock signal terminal, the second node, the first level signal terminal, and multiple third nodes, and controls the multiple third nodes according to the fourth clock signal terminal and the second node.

[0009] The output circuit includes multiple output sub-circuits, which are electrically connected to multiple third nodes, multiple fifth clock signal terminals, multiple output terminals, and a fifth level signal terminal, and output drive signals under the control of the third nodes and the fifth clock signal terminals.

[0010] The first pull-down control sub-circuit is electrically connected to the third node, the second level signal terminal, the third level signal terminal, and the fourth node, and controls the fourth node according to the third node.

[0011] The second pull-down control sub-circuit is electrically connected to the second node, the fourth clock signal terminal, the fourth node, and the fourth level signal terminal, and controls the fourth node according to the second node and the fourth clock signal terminal.

[0012] The pull-down circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the third clock signal terminal, and controls the third node according to the fourth node and the third clock signal terminal.

[0013] In some embodiments, the pull-down sub-circuit includes a first pull-down sub-circuit and a second pull-down sub-circuit;

[0014] The first sub-pull-down sub-circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the fifth node, and controls the third node according to the fourth node;

[0015] The second sub-pull-down circuit is electrically connected to the third node, the fifth node, and the third clock signal terminal, and controls the third node according to the third clock signal terminal.

[0016] In some embodiments, the first sub-pull-down circuit includes a plurality of transistors, the control electrode of the transistors being electrically connected to a fourth node, the first terminal of the transistors being electrically connected to a third node, and the second terminal of the transistors being electrically connected to a fourth level signal terminal.

[0017] In some embodiments, the second sub-pull-down circuit includes a plurality of transistors, the control electrode of the transistors being electrically connected to a third clock signal terminal, the first terminal of the transistors being electrically connected to a third node, and the second terminal of the transistors being electrically connected to a fifth node.

[0018] In some embodiments, the input sub-circuit includes a first capacitor and a tenth transistor and an eleventh transistor. The first terminal and the second terminal of the first capacitor are respectively connected to a first level signal terminal and a second node. The control electrode, the first electrode, and the second electrode of the eleventh transistor are respectively electrically connected to a second clock signal terminal, a first level signal terminal, and a second node. The control electrode, the first electrode, and the second electrode of the tenth transistor are respectively electrically connected to a first node, a second clock signal terminal, and a second node.

[0019] In some embodiments, the output control sub-circuit includes a plurality of control transistors, wherein the control electrode, the first electrode, and the second electrode of the control transistors are electrically connected to the fourth clock signal terminal, the second node, and the third node, respectively.

[0020] In some embodiments, the output sub-circuit includes a capacitor, an output transistor, and a pull-down transistor. The first terminal of the capacitor and the control terminal of the output transistor are electrically connected to the third node as the control terminal of the output sub-circuit. The first terminal of the output transistor is electrically connected to the fifth clock signal terminal. The second terminal of the capacitor and the second terminal of the output transistor together serve as the output terminal.

[0021] The first control terminal and the first terminal of the pull-down transistor are electrically connected to the fourth node and the second terminal of the output transistor, respectively. The second terminal of the pull-down transistor is the third terminal of the output sub-circuit and is electrically connected to the fifth level signal terminal.

[0022] In some embodiments, the first pull-down control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The control electrode and the first electrode of the fourteenth transistor are electrically connected to a second-level signal terminal, respectively. The second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor. The control electrode of the fifteenth transistor is electrically connected to the second-level signal terminal. The second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor. The second electrode of the sixteenth transistor is electrically connected to a third-level signal terminal. The control electrode of the sixteenth transistor serves as the first control terminal of the pull-down control sub-circuit and is electrically connected to a third node. The first electrode of the seventeenth transistor is connected to the second-level signal terminal, and the second electrode of the seventeenth transistor is electrically connected to a fourth node.

[0023] In some embodiments, the first pull-down control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The control electrode and the first electrode of the fourteenth transistor are electrically connected to a second-level signal terminal, respectively. The second electrode of the fourteenth transistor is electrically connected to the first electrode and the control electrode of the fifteenth transistor. The second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor. The second electrode of the sixteenth transistor is electrically connected to a third-level signal terminal. The control electrode of the sixteenth transistor serves as the first control terminal of the pull-down control sub-circuit and is electrically connected to a third node. The first electrode of the seventeenth transistor is connected to the second-level signal terminal, and the second electrode of the seventeenth transistor is electrically connected to a fourth node.

[0024] In some embodiments, the first pull-down control sub-circuit further includes an eighteenth transistor, the control electrode, the first electrode, and the second electrode of the eighteenth transistor being electrically connected to the third node, the fourth node, and the fourth level signal terminal, respectively.

[0025] In some embodiments, the number of the first pull-down control sub-circuit, the second pull-down control sub-circuit, and the pull-down sub-circuit is multiple.

[0026] In some embodiments, the second pull-down control sub-circuit includes a 37th transistor and a 38th transistor. The control electrode and the first electrode of the 37th transistor are respectively connected to the second node and the fourth node. The second electrode of the 37th transistor is electrically connected to the second electrode of the 38th transistor. The control electrode and the second electrode of the 38th transistor are respectively electrically connected to the fourth clock signal terminal and the fourth level signal terminal.

[0027] In some embodiments, the integrated circuit unit further includes a reset sub-circuit, which is electrically connected to a reset signal terminal, a first level signal terminal, a second node, a fourth node, and a fourth level signal terminal, respectively.

[0028] In some embodiments, the reset sub-circuit includes a nineteenth transistor, a twentieth transistor, and a twenty-second transistor. The control electrodes of the nineteenth, twentieth, and twenty-second transistors are electrically connected to the reset signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first level signal terminal, the second electrode of the nineteenth transistor is electrically connected to the fourth node, the first electrode of the twenty-second transistor is electrically connected to the second node, the second electrode of the twenty-second transistor is electrically connected to the first electrode of the twentieth transistor, and the second electrode of the twentieth transistor is electrically connected to the fourth level signal terminal.

[0029] In some embodiments, the integrated circuit unit further includes a leakage protection electronic circuit, wherein the first control electrode, the first terminal, and the second terminal of the leakage protection electronic circuit are electrically connected to the third node, the first level signal terminal, and the pull-down sub-circuit, respectively.

[0030] In some embodiments, the integrated circuit unit further includes a third pull-down sub-circuit, which is electrically connected to the second clock signal terminal, the third clock signal terminal, and the first node, respectively, and controls the first node according to the second clock signal terminal and the third clock signal terminal.

[0031] In some embodiments, the input control subcircuit includes a plurality of gating transistors connected in parallel, the number of gating transistors being less than or equal to the number of gating signal terminals, and the control electrode of each gating transistor being connected to one of the gating signal terminals.

[0032] In some embodiments, the first terminal of the plurality of parallel-connected gating transistors is electrically connected to the third clock signal terminal, the second terminal of the gating transistors is electrically connected to the first node, and the control terminal of the gating transistors is electrically connected to the gating signal to control the first node.

[0033] In some embodiments, among the gating signal terminals connected to the plurality of gating transistors, the pulse width of the gating signal of the nth gating signal terminal is twice the pulse width of the gating signal of the (n-1)th gating signal terminal, where n is an integer greater than 1.

[0034] In some embodiments, the high-level width and low-level width of the strobe signal are equal in one cycle of each of the strobe signal terminals.

[0035] A second aspect of this application provides a gate driving circuit including a plurality of integrated circuit unit groups, wherein the integrated circuit unit groups include the integrated circuit units described in the above embodiments, the number of gating signal terminals is twice the number of gating transistors, and the gating signal terminals include a plurality of positive gating signal terminals and a plurality of inverse gating signal terminals whose signals are opposite to those of the positive gating signal terminals.

[0036] In some embodiments, the integrated circuit unit group includes four integrated circuit units, the integrated circuit units in the same group are connected to the selected communication terminal in the same order, and the integrated circuit units in the same group are connected to each clock signal terminal in a different order.

[0037] In some embodiments, the connections between the integrated circuit units of different groups and the strobe signal terminal are different.

[0038] A third aspect of this application provides a display panel including the gate driving circuit described in the above embodiments.

[0039] This application achieves random compensation for external compensation through the cooperation of an input control sub-circuit, an input sub-circuit, an output control sub-circuit, an output circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, and a pull-down sub-circuit. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the driving signals for the first three rows of pixels in the related technology.

[0041] Figure 2 This is a schematic diagram of the circuit principle of an integrated circuit unit in related technologies.

[0042] Figure 3 This is a schematic diagram of the integrated circuit unit according to an embodiment of this application.

[0043] Figure 4 This is a timing diagram of an embodiment of the integrated circuit unit of this application.

[0044] Figure 5 This is a circuit diagram of an embodiment of the integrated circuit unit of this application.

[0045] Figure 6 This is a circuit diagram of another embodiment of the integrated circuit unit of this application.

[0046] Figure 7 This is a circuit diagram of another embodiment of the integrated circuit unit of this application.

[0047] Figure 8 This is a circuit diagram of another embodiment of the integrated circuit unit of this application.

[0048] Figure 9 This is a circuit diagram of another embodiment of the integrated circuit unit of this application.

[0049] Figure 10 This is a circuit diagram of another embodiment of the integrated circuit unit of this application.

[0050] Figure 11 This is a connection diagram of an embodiment of the gate drive circuit of this application.

[0051] Figure 12 This is a timing diagram of the selection signal terminal of the integrated circuit unit in this application. Detailed Implementation

[0052] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0053] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar words used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a" and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. The terms "comprising" or "including," and similar words mean that the element or object preceding "comprising" or "including" covers the element or object listed following "comprising" or "including" and its equivalents, and do not exclude other elements or objects. The terms "connected" or "linked," and similar words are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms "a," "the," and "the" used in this application specification and appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0054] The transistors used in this application can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this application, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0055] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0056] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0057] In pixel circuits, a combination of transistors and capacitors is typically used to drive organic light-emitting elements (OLEDs), such as the 3T1C circuit. However, this type of circuit has poor uniformity, requiring compensation circuitry to ensure consistent OLED emission. A common compensation method is external compensation via GOA (Gate on Array) circuitry to increase device uniformity.

[0058] like Figure 1 As shown, the external compensation signal is typically composed of a combination of "line shift" and "frame shift" signals. The signal during the blanking time of a frame is the frame shift signal, which is further divided into sequential frame shift and random frame shift. In the sequential frame shift compensation method, the gate drive circuit can output drive signals to pixels line by line to compensate the pixel drive circuit. In the random frame shift compensation method, the gate drive circuit can output compensation drive signals to any row of pixels in any frame to compensate the pixel drive transistor. However, the sequential frame shift compensation method is prone to producing compensation horizontal lines, resulting in poor display.

[0059] like Figure 2 As shown, a GOA unit for random frame shifting is provided. However, the GOA units in the figure are all independent and are connected to different signals entirely through the gating circuit in the dashed box in the figure, so as to achieve the purpose of gating the row. However, the number of transistors in the dashed box is too large, making the layout very difficult. Furthermore, the method of shielding the S point is not conducive to suppressing noise.

[0060] like Figure 3As shown, this application discloses an integrated circuit unit, including: an input control sub-circuit 100, an input sub-circuit 200, an output control sub-circuit 300, an output circuit 400, a first pull-down control sub-circuit 500, a second pull-down control sub-circuit 600, and a pull-down sub-circuit 700. The input control sub-circuit 100 is electrically connected to the gating signal terminal DA, the third clock signal terminal CLKD3, and the first node N, respectively, and controls the first node N according to the gating signal terminal DA and the third clock signal terminal CLKD3; the input sub-circuit 200 is electrically connected to the second clock signal terminal CLKD2, the first node N, the first level signal terminal GVDD1, and the second node P, respectively, and controls the second node P according to the second clock signal terminal CLKD2 and the first node N; the output control sub-circuit 300 is electrically connected to the fourth clock signal terminal CLKD4, the second node P, the first level signal terminal GVDD1, and multiple third nodes Q(n), respectively, and controls the multiple third nodes Q(n) according to the fourth clock signal terminal CLKD4 and the second node P; the output circuit 400 includes multiple output sub-circuits, and the multiple output sub-circuits are respectively connected to multiple third nodes Q(n), multiple fifth clock signal terminals CLKE(n), and multiple output terminals. SCOUT(n) and the fifth level signal terminal VGL1 are electrically connected, and the drive signal is output under the control of the third node Q(n) and the fifth clock signal terminal CLKE(n); the first pull-down control sub-circuit 500 is electrically connected to the third node Q(n), the second level signal terminal GVDD2, the third level signal terminal VGL2, and the fourth node QB, and controls the fourth node QB according to the third node Q(n); the second pull-down control sub-circuit 600 is electrically connected to the second node P, the fourth clock signal terminal CLKD4, the fourth node QB, and the fourth level signal terminal LVGL, and controls the fourth node QB according to the second node P and the fourth clock signal terminal CLKD4; the pull-down sub-circuit 700 is electrically connected to the fourth node QB, the third node Q(n), the fourth level signal terminal LVGL, and the third clock signal terminal CLKD3, and controls the third node Q(n) according to the fourth node QB and the third clock signal terminal CLKD3.

[0061] refer to Figure 4As shown, in the first stage S1, the rising edge of the second clock signal terminal CLKD2 arrives, and the first node N is in the off state, while the second node P is set to a high potential; in the second stage S2, the second node P remains high; in the third stage S3, the rising edge of the fourth clock signal terminal CLKD4 arrives, and the third node Q(n) is set to a high potential; in the fourth stage S4, the fourth clock signal terminal CLKD4 is turned off, and multiple fifth clock signal terminals CLKE(n) arrive sequentially with rising edges, resulting in the integrated circuit unit output; after the integrated circuit unit outputs, the rising edge of the third clock signal terminal CLKD3 arrives, and the third node Q(n) is pulled low. Here, CLKE(n) refers to CLKE1, CLKE2 to CLKE16, etc.

[0062] The integrated circuit unit proposed in this application uses a DA gate signal to select the row, avoiding the use of too many transistors, thus occupying less space and facilitating the achievement of a narrow bezel. Furthermore, this application sets up multiple output sub-circuits, allowing multiple compensation signals to be output within a single GOA unit.

[0063] In one embodiment, the input control sub-circuit 100 includes a plurality of gating transistors connected in parallel, the number of gating transistors being less than or equal to the number of gating signal terminals, and the control electrode of each gating transistor being connected to one gating signal terminal. It is understood that as long as one gating transistor is connected, the control sub-circuit 100 can control the first node N under the control of the third clock signal terminal CLKD3.

[0064] For further information, please refer to the following: Figure 5 The first terminal of each of the parallel-connected selection transistors is electrically connected to the third clock signal terminal, the second terminal of the selection transistor is electrically connected to the first node N, and the control terminal of the selection transistor is electrically connected to the selection signal DA to control the first node N. Based on the above structural configuration, the selection signal DA can control the potential of the first node N. Furthermore, the number of parallel-connected selection transistors can be changed according to requirements, and can be 1, 3, 6, 8, or 11, etc. The number of selection signal terminals is greater than or equal to the number of selection transistors, and the control terminal of each selection transistor is connected to one selection signal terminal. This embodiment takes 8 selection transistors and 8 selection signal terminals as an example. The 8 selection transistors are the second transistor T1 to the ninth transistor T8, and the 8 selection signal terminals are the first selection signal terminal D0 to the eighth selection signal terminal D7. The 8 selection transistors and 8 selection signal terminals are connected correspondingly. One cycle of the eighth selection signal terminal D7 can cover 2... 8 The first strobe signal terminal D0 has one cycle. A high-level segment of the eighth strobe signal terminal D7 can cover 2 cycles. 7 The first strobe signal terminal D0 cycle.

[0065] For further details, please refer to... Figure 11 and Figure 12 As shown, among the gating signal terminals connected to the plurality of gating transistors, the pulse width of the gating signal of the nth gating signal terminal is twice the pulse width of the gating signal of the (n-1)th gating signal terminal, where n is an integer greater than 1. With this configuration, the connection of the gating signal terminals can be set simply by connecting them sequentially. Furthermore, the high-level width and low-level width of the gating signal in one cycle of each gating signal terminal can be made equal. The equal high-level width and low-level width also ensure that the output after connection follows the specified parameters. Figure 11 The sequence is followed so that the entire GOA unit can function normally.

[0066] Optionally, the number of gating signal terminals can be greater than eight. Gating signal terminals with opposite phases to any one of the first to eighth gating signal terminals D0 can be added. For example, a ninth gating signal terminal D0' with an opposite phase to the first gating signal terminal D0 can be added. Alternatively, eight gating signal terminals, from the ninth gating signal terminal D0' to the sixteenth gating signal terminal D7', can be added, each with an opposite phase to the first to eighth gating signal terminals D0. One of each pair of gating signal terminals with opposite phases is selected to connect to the control electrode of the gating transistor. Taking eight pairs of gating signal terminals with opposite phases as an example, there can be 2... 8 Combining them can achieve 2 8 Effective output at different timings. Therefore, this application can achieve at least 2 8 High refresh rate for individual lines.

[0067] In one embodiment, reference Figure 4 As shown, this application also includes a third pull-down circuit, which is electrically connected to the second clock signal terminal CLKD2, the third clock signal terminal CLKD3, and the first node N, respectively, and controls the first node N according to the second clock signal terminal CLKD2 and the third clock signal terminal CLKD3.

[0068] The third pull-down circuit includes a ninth transistor T9. The control terminal, first terminal, and second terminal of the ninth transistor T9 are electrically connected to the second clock signal terminal CLKD2, the third clock signal terminal CLKD3, and the first node N, respectively. When the rising edge of the second clock signal terminal CLKD2 arrives, the ninth transistor T9 is turned on, and the potential of the first node N is pulled low.

[0069] In one embodiment, reference Figure 5As shown, the output sub-circuit includes a capacitor, an output transistor, and a pull-down transistor. The first terminal of the capacitor and the control terminal of the output transistor are electrically connected to the third node Q(n) as the control terminals of the output sub-circuit. The first terminal of the output transistor is electrically connected to the fifth clock signal terminal CLKE(n). The second terminal of the capacitor and the second terminal of the output transistor together serve as the output terminal. The first control terminal and the first terminal of the pull-down transistor are electrically connected to the fourth node QB and the second terminal of the output transistor, respectively. The second terminal of the pull-down transistor serves as the third terminal of the output sub-circuit and is electrically connected to the fifth level signal terminal VGL1.

[0070] In one exemplary embodiment, reference is made to... Figure 5 As shown, the output circuit 400 includes four output sub-circuits. The first output sub-circuit includes capacitor C2, 40th transistor T40, and 41st transistor T41. The first terminal of capacitor C2 and the control terminal of 40th transistor T40 serve as the control terminals of the output sub-circuit and are electrically connected to the third node Q1. The first terminal of 40th transistor T40 is electrically connected to the fifth clock signal terminal CLKE1. The second terminals of capacitor C2 and 40th transistor T40 together serve as the output terminal. The first control terminal and the first terminal of 41st transistor T41 are electrically connected to the fourth node QB and the second terminal of 40th transistor T40, respectively. The second terminal of 41st transistor T41 serves as the third terminal of the output sub-circuit and is electrically connected to the fifth level signal terminal VGL1. The second output sub-circuit includes capacitor C3, 42nd transistor T42, and 43rd transistor T43. The third output sub-circuit includes capacitor C4, 44th transistor T44, and 45th transistor T45. The fourth output sub-circuit includes capacitor C5, 46th transistor T46, and 47th transistor T47. The connection methods for each output sub-circuit are the same, and will not be described in detail here.

[0071] Based on the above description, when the voltage of the fourth node QB is positive, all output sub-circuits are pulled low to prevent erroneous output.

[0072] In one embodiment, reference Figure 5 As shown, the pull-down sub-circuit 700 includes a first pull-down sub-circuit 710 and a second pull-down sub-circuit 720; the first pull-down sub-circuit 710 is electrically connected to the fourth node QB, the third node Q(n), the fourth level signal terminal LVGL, and the fifth node X, respectively, and controls the third node Q(n) according to the fourth node QB; the second pull-down sub-circuit 720 is electrically connected to the third node Q(n), the fifth node X, and the third clock signal terminal CLKD3, respectively, and controls the third node Q(n) according to the third clock signal terminal CLKD3.

[0073] Specifically, the first pull-down circuit 710 includes multiple transistors, the control terminal of the transistor is electrically connected to the fourth node QB, the first terminal of the transistor is electrically connected to the third node Q(n), and the second terminal of the transistor is electrically connected to the fourth level signal terminal LVGL.

[0074] refer to Figure 5 As shown, when the output circuit 400 includes four output sub-circuits, the first sub-pull-down sub-circuit 710 includes the thirty-sixth transistor T36, the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, and the thirtieth transistor T30. The control terminals of the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, and the thirtieth transistor T30 are electrically connected to the fourth node QB, respectively. The first terminals of the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, and the thirtieth transistor T30 are electrically connected to the third nodes Q1-Q4, respectively. The second terminals of the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, and the thirtieth transistor T30 are electrically connected to the first terminal of the thirty-sixth transistor T36, respectively. The control terminal of the thirty-sixth transistor T36 is electrically connected to the fourth node QB, and the second terminal of the thirty-sixth transistor T36 is electrically connected to the fourth level signal terminal LVGL.

[0075] Based on the above description, when the fourth node QB is energized, the thirty-sixth transistor T36 turns on and is electrically connected to the fourth-level signal terminal LVGL. Simultaneously, the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, and the thirtieth transistor T30 are also turned on and connected to the thirty-sixth transistor T36. Therefore, the third nodes Q1-Q4, which are connected to the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, and the thirtieth transistor T30, are all directly connected to the fourth-level signal terminal LVGL, thus maintaining a low potential.

[0076] Specifically, the second sub-pull-down circuit 720 includes multiple transistors, the control terminal of the transistors is electrically connected to the third clock signal terminal CLKD3, the first terminal of the transistors is electrically connected to the third node Q(n), and the second terminal of the transistors is electrically connected to the fifth node X.

[0077] refer to Figure 5As shown, when the output circuit 400 includes four output sub-circuits, the second sub-pull-down sub-circuit 720 includes the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, the thirty-fourth transistor T34, and the thirty-fifth transistor T35. The control terminals of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, the thirty-fourth transistor T34, and the thirty-fifth transistor T35 are electrically connected to the third clock signal terminal CLKD3. The first terminals of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, and the thirty-fourth transistor T34 are electrically connected to the third nodes Q1-Q4. The second terminals of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, and the thirty-fourth transistor T34, as well as the first terminal of the thirty-fifth transistor T35, are electrically connected to the fifth node X. The second terminal of the thirty-fifth transistor T35 is connected to the fourth level signal terminal LVGL.

[0078] Based on the above description, when the rising edge of the third clock signal terminal CLKD3 arrives, the thirty-fifth transistor T35 turns on and is electrically connected to the fourth level signal terminal LVGL. Simultaneously, the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, and the thirty-fourth transistor T34 are also turned on and connected to the thirty-fifth transistor T35. Therefore, the third nodes Q1-Q4, connected to the thirty-first transistor T31, the thirty-second transistor T32, the thirty-third transistor T33, and the thirty-fourth transistor T34, are all directly connected to the fourth level signal terminal LVGL, thus maintaining a low potential.

[0079] In one embodiment, reference Figure 5 As shown, the input sub-circuit 200 includes a first capacitor C1, a tenth transistor T10, and an eleventh transistor T11. The first and second terminals of the first capacitor C1 are connected to the first level signal terminal GVDD1 and the second node P, respectively. The control electrode, the first electrode, and the second electrode of the eleventh transistor T11 are electrically connected to the second clock signal terminal CLKD2, the first level signal terminal GVDD1, and the second node P, respectively. The control electrode, the first electrode, and the second electrode of the tenth transistor T10 are electrically connected to the first node N, the second clock signal terminal CLKD2, and the second node P, respectively.

[0080] The circuit can also connect the twelfth transistor T12 and the thirteenth transistor T13 in series or parallel to prevent leakage. After the rising edge of the second clock signal terminal CLKD2 arrives, the eleventh transistor T11 turns on, the first capacitor C1 charges, and the second node P is set to a high potential.

[0081] In one embodiment, reference Figure 5As shown, the output control sub-circuit 300 includes multiple control transistors, and the control electrode, first electrode, and second electrode of the control transistors are electrically connected to the fourth clock signal terminal CLKD4, the second node P, and the third node Q(n), respectively.

[0082] like Figure 5 As shown, the output control sub-circuit 300 includes a 21st transistor T21, a 23rd transistor T23, a 24th transistor T24, a 25th transistor T25, and a 26th transistor T26. The control electrode and first electrode of the 21st transistor T21 are connected to the second node P and the first level signal terminal GVDD1, respectively. The second electrode of the 21st transistor T21 is connected to the first electrode of the 23rd transistor T23, the 24th transistor T24, the 25th transistor T25, and the 26th transistor T26. The control electrode of the 23rd transistor T23, the 24th transistor T24, the 25th transistor T25, and the 26th transistor T26 is electrically connected to the fourth clock signal terminal CLKD4. The second electrodes of the 23rd transistor T23, the 24th transistor T24, the 25th transistor T25, and the 26th transistor T26 are connected to the third nodes Q1-Q4, respectively. When the second node P is set to a high potential and the rising edge of the fourth clock signal terminal CLKD4 arrives, the third nodes Q1-Q4 are set to a high potential.

[0083] In other embodiments, such as Figure 9 and Figure 10 As shown, the output control sub-circuit 300 also includes a newly added transistor T21'. The first and control terminals of the newly added transistor T21' are both connected to the fourth clock signal terminal CLKD4. The second terminal of the newly added transistor T21' replaces the original first-level signal terminal GVDD1 and is connected to the twenty-first transistor T21. The addition of the new transistor T21' prevents leakage at the fourth clock signal terminal CLKD4, thereby preventing the third nodes Q1-Q4 from being placed at a high potential, thus maximizing the protection of the third nodes Q1-Q4.

[0084] In one embodiment, such as Figure 5 and Figure 6As shown, the first pull-down control sub-circuit 500 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17. The control electrode and the first electrode of the fourteenth transistor T14 are electrically connected to the second-level signal terminal GVDD2, respectively. The second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15. The control electrode of the fifteenth transistor T15 is electrically connected to the second-level signal terminal GVDD2. The second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the seventeenth transistor T17. The second electrode of the sixteenth transistor T16 is electrically connected to the third-level signal terminal VGL2. The control electrode of the sixteenth transistor T16 serves as the first control terminal of the pull-down control sub-circuit and is electrically connected to the third node Q(n). The first electrode of the seventeenth transistor T17 is connected to the second-level signal terminal GVDD2. The second electrode of the seventeenth transistor T17 is electrically connected to the fourth node QB.

[0085] like Figure 5 As shown, when the output circuit 400 includes four output sub-circuits, the third node Q(n) includes Q1-Q4, and Q2 is selected here as an example. When Q2 is low, the fourth node QB is set to high potential; when Q2 is low-high level, the fourth node QB is set to low.

[0086] In other embodiments, such as Figure 7 As shown, the first pull-down control sub-circuit 500 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17. The control electrode and the first electrode of the fourteenth transistor T14 are electrically connected to the second level signal terminal GVDD2, respectively. The second electrode of the fourteenth transistor T14 is electrically connected to the first electrode and the control electrode of the fifteenth transistor T15. The second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the seventeenth transistor T17. The second electrode of the sixteenth transistor T16 is electrically connected to the third level signal terminal VGL2. The control electrode of the sixteenth transistor T16 serves as the first control terminal of the pull-down control sub-circuit and is electrically connected to the third node Q(n). The first electrode of the seventeenth transistor T17 is connected to the second level signal terminal GVDD2, and the second electrode of the seventeenth transistor T17 is electrically connected to the fourth node QB.

[0087] This embodiment can achieve the same effect, but the control electrode charge of the fifteenth transistor T15 here comes from the second electrode of the fourteenth transistor T14. Therefore, the pressure on the fifteenth transistor T15 is reduced, thereby ensuring the reliability of the fifteenth transistor T15.

[0088] Furthermore, in this embodiment, the first pull-down control sub-circuit 500 may also include an eighteenth transistor T18, the control electrode, the first electrode, and the second electrode of the eighteenth transistor T18 being electrically connected to the third node Q(n), the fourth node QB, and the fourth level signal terminal LVGL, respectively.

[0089] At this time, the control electrodes of the sixteenth transistor T16 and the eighteenth transistor T18 are connected to Q2 and Q3 respectively. As long as either Q2 or Q3 has current, the fourth node QB can be pulled low, thereby obtaining double protection.

[0090] In one embodiment, reference Figure 8 , Figure 9 , Figure 10 As shown, there are multiple first pull-down control sub-circuit 500, second pull-down control sub-circuit 600, and pull-down sub-circuit 700.

[0091] As shown in the figure, the first pull-down control sub-circuit 500 is preferably two, the output circuit 400 includes four output sub-circuits, and the third node Q(n) includes Q1-Q4. The first pull-down control sub-circuit 500 includes the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, and the fourteenth additional transistor T14', the fifteenth additional transistor T15', the sixteenth additional transistor T16', the seventeenth additional transistor T17', and the eighteenth additional transistor T18'. The control electrodes of the sixteenth transistor T16, the eighteenth transistor T18, the sixteenth additional transistor T16', and the eighteenth additional transistor T18' are respectively connected to the third nodes Q1-Q4. Thus, as long as there is current at any point of the third node Q(n), the fourth node QB can be pulled low, thereby obtaining maximum protection.

[0092] In one embodiment, the second pull-down control sub-circuit 600 includes a thirty-seventh transistor T37 and a thirty-eighth transistor T38. The control terminal and the first terminal of the thirty-seventh transistor T37 are connected to the second node P and the fourth node QB, respectively. The second terminal of the thirty-seventh transistor T37 is electrically connected to the second terminal of the thirty-eighth transistor T38. The control terminal and the second terminal of the thirty-eighth transistor T38 are electrically connected to the fourth clock signal terminal CLKD4 and the fourth level signal terminal LVGL, respectively. When both the second node P and the fourth clock signal terminal CLKD4 are present, the voltage of the fourth node QB is pulled low.

[0093] In one embodiment, the second pull-down control sub-circuit 600 can be configured as multiple, such as... Figure 9 As shown, by selecting two second pull-down control sub-circuits 600, multi-layer protection can be provided.

[0094] In one embodiment, such as Figure 5 As shown, the integrated circuit unit further includes a reset sub-circuit 1000, which is electrically connected to the reset signal terminal TRS, the first level signal terminal GVDD1, the second node P, the fourth node QB, and the fourth level signal terminal LVGL.

[0095] like Figure 5 As shown, the reset sub-circuit 1000 includes a nineteenth transistor T19, a twentieth transistor T20, and a twenty-second transistor T22. The control terminals of the nineteenth transistor T19, the twentieth transistor T20, and the twenty-second transistor T22 are electrically connected to the reset signal terminal TRS. The first terminal of the nineteenth transistor T19 is electrically connected to the first level signal terminal GVDD1, and the second terminal of the nineteenth transistor T19 is electrically connected to the fourth node QB. The first terminal of the twenty-second transistor T22 is electrically connected to the second node P, and the second terminal of the twenty-second transistor T22 is electrically connected to the first terminal of the twentieth transistor T20. The second terminal of the twentieth transistor T20 is electrically connected to the fourth level signal terminal LVGL. When the rising edge of the reset signal TRS arrives, the second node P is pulled low, and the fourth node QB is set to a high potential.

[0096] In one embodiment, according to Figure 5 and Figure 6 As shown, the integrated circuit unit also includes a leakage protection electronic circuit. The first control electrode, the first terminal, and the second terminal of the leakage protection electronic circuit 800 are electrically connected to the third node Q(n), the first level signal terminal GVDD1, and the pull-down sub-circuit 700, respectively.

[0097] The leakage protection electronic circuit 800 includes a 39th transistor T39 and a 48th transistor T48. The first terminals of the 39th transistor T39 and the 48th transistor T48 are electrically connected to the first level signal terminal GVDD1, the second terminals of the 39th transistor T39 and the 48th transistor T48 are electrically connected to the fifth node X, and the control terminals of the 39th transistor T39 and the 48th transistor T48 are electrically connected to the third node Q(n). The 39th transistor T39 and the 48th transistor T48 are connected in parallel.

[0098] Of course, in other embodiments, according to Figure 5 and Figure 6 As shown, the thirty-ninth transistor T39 and the forty-eighth transistor T48 can also be connected in series.

[0099] like Figure 4 As shown, Figure 4This is a timing diagram for one optional embodiment. The reset signal TRS first resets the circuit, pulling the fourth node QB to a high level, thus ensuring that the third node Q(n) remains low. Simultaneously, it pulls the second node P low, ensuring the entire timing sequence proceeds correctly.

[0100] In the first stage S1, the rising edge of the second clock signal terminal CLKD2 arrives, and the second node P is set to a high level. At this time, although the strobe signal DA is high, the third clock signal terminal CLKD3 has not yet arrived, so the first node N remains low.

[0101] In the second stage S2, the rising edge of the third clock signal terminal CLKD3 arrives, and the second node P remains in a high position. Although the third clock signal terminal CLKD3 arrives at this time, the strobe signal DA is in a low position, so the first node N remains in a low position.

[0102] In the third stage S3, the rising edge of the fourth clock signal terminal CLKD4 arrives, the third node Q(n) is set to a high potential, and the fourth node QB is pulled low.

[0103] In the fourth stage S4, the fourth clock signal terminal CLKD4 is turned off, and multiple fifth clock signal terminals CLKE(n) arrive sequentially with rising edges, and the integrated circuit unit outputs; after the integrated circuit unit outputs, the third clock signal terminal CLKD3 arrives with rising edges, and the third node Q(n) is pulled low.

[0104] like Figure 10 and Figure 11 As shown, this application also discloses a gate driving circuit, which includes multiple integrated circuit unit groups. Each integrated circuit unit group includes at least one of the aforementioned integrated circuit units. Each integrated circuit unit includes n gating transistors. The gate driving circuit includes 2n gating signal terminals, of which 2n gating signal terminals include 16 signal terminals: D0, D0', D1, D1', D2, D2', D3, D3', D4, D4', D5, D5', ..., Dn, D'n. D0', D1', D2', D3', D4', D5', ..., Dn' are the inverted signals of D0, D1, D2, D3, D4, D5, ..., Dn, respectively. The pulse width of Da is twice the pulse width of Da-1, where a is 2, 3, to n. The connections between different groups of integrated circuit units and the gating signal terminals are different. The number of gating transistors in this application can be set according to requirements.

[0105] In one optional embodiment, the control terminal of the a-th gating transistor among the n gating transistors is selectively connected to either Da or Da', where a is greater than 0 and less than n. The connection method between the integrated circuit units and the gating signal terminals within the same integrated circuit unit group is the same. By analogy, 2...n+1 Each integrated circuit unit group operates independently. Optionally, an integrated circuit unit group includes four integrated circuit units, which achieve shift output through a different connection order with each clock signal terminal. Furthermore, in this application, one integrated circuit unit can have four output ports. Therefore, the gate drive circuit of this embodiment can achieve 2... n+5 The row shifting operation is independent. During the row shifting phase, the gate drive circuit can control the sequential row shifting of the signal outputs at the strobe and clock signals. During the blanking phase, the gate drive circuit can control the random frame shifting of the signal outputs at the strobe and clock signals to achieve random external compensation.

[0106] This application also discloses a display panel including the aforementioned gate driving circuit.

[0107] The display device, gate driving circuit, integrated circuit unit and driving method provided in the embodiments of this application belong to the same inventive concept. The descriptions of related details and beneficial effects can be referred to each other and will not be repeated here.

[0108] The above description is merely a preferred embodiment of this application and is not intended to limit this application in any way. Although this application has disclosed the preferred embodiment as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An integrated circuit unit, characterized in that, include: The input control sub-circuit is electrically connected to the gating signal terminal, the third clock signal terminal, and the first node, and controls the first node according to the gating signal terminal and the third clock signal terminal. The input sub-circuit is electrically connected to the second clock signal terminal, the first node, the first level signal terminal, and the second node, and controls the second node according to the second clock signal terminal and the first node. The output control sub-circuit is electrically connected to the fourth clock signal terminal, the second node, the first level signal terminal, and multiple third nodes, and controls the multiple third nodes according to the fourth clock signal terminal and the second node. The output circuit includes multiple output sub-circuits, which are electrically connected to multiple third nodes, multiple fifth clock signal terminals, multiple output terminals, and a fifth level signal terminal, and output drive signals under the control of the third nodes and the fifth clock signal terminals. The first pull-down control sub-circuit is electrically connected to the third node, the second level signal terminal, the third level signal terminal, and the fourth node, and controls the fourth node according to the third node. The second pull-down control sub-circuit is electrically connected to the second node, the fourth clock signal terminal, the fourth node, and the fourth level signal terminal, and controls the fourth node according to the second node and the fourth clock signal terminal. The pull-down sub-circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the third clock signal terminal, and controls the third node according to the fourth node and the third clock signal terminal. The input control sub-circuit includes a number of gating transistors connected in parallel. The number of gating transistors is less than or equal to the number of gating signal terminals. The control electrode of each gating transistor is connected to one gating signal terminal. The first terminal of the several parallel-connected gating transistors is electrically connected to the third clock signal terminal, the second terminal of the gating transistors is electrically connected to the first node, and the control terminal of the gating transistors is electrically connected to the gating signal to control the first node. In the gating signal terminals connected to the plurality of gating transistors, the pulse width of the gating signal of the nth gating signal terminal is twice the pulse width of the gating signal of the (n-1)th gating signal terminal, where n is an integer greater than 1.

2. The integrated circuit unit according to claim 1, characterized in that, The pull-down sub-circuit includes a first pull-down sub-circuit and a second pull-down sub-circuit; The first sub-pull-down sub-circuit is electrically connected to the fourth node, the third node, the fourth level signal terminal, and the fifth node, and controls the third node according to the fourth node; The second sub-pull-down circuit is electrically connected to the third node, the fifth node, and the third clock signal terminal, and controls the third node according to the third clock signal terminal.

3. The integrated circuit unit according to claim 2, characterized in that, The first pull-down circuit includes multiple transistors, the control electrode of the transistor is electrically connected to the fourth node, the first terminal of the transistor is electrically connected to the third node, and the second terminal of the transistor is electrically connected to the fourth level signal terminal.

4. The integrated circuit unit according to claim 2, characterized in that, The second sub-pull-down circuit includes multiple transistors, the control terminal of which is electrically connected to the third clock signal terminal, the first terminal of which is electrically connected to the third node, and the second terminal of which is electrically connected to the fifth node.

5. The integrated circuit unit according to claim 1, characterized in that, The input sub-circuit includes a first capacitor and a tenth transistor and an eleventh transistor. The first terminal and the second terminal of the first capacitor are respectively connected to a first level signal terminal and a second node. The control electrode, the first electrode, and the second electrode of the eleventh transistor are respectively electrically connected to a second clock signal terminal, a first level signal terminal, and a second node. The control electrode, the first electrode, and the second electrode of the tenth transistor are respectively electrically connected to a first node, a second clock signal terminal, and a second node.

6. The integrated circuit unit according to claim 1, characterized in that, The output control sub-circuit includes multiple control transistors, and the control electrode, first electrode, and second electrode of the control transistors are electrically connected to the fourth clock signal terminal, the second node, and the third node, respectively.

7. The integrated circuit unit according to claim 1, characterized in that, The output sub-circuit includes a capacitor, an output transistor, and a pull-down transistor. The first terminal of the capacitor and the control terminal of the output transistor are electrically connected to the third node as the control terminal of the output sub-circuit. The first terminal of the output transistor is electrically connected to the fifth clock signal terminal. The second terminal of the capacitor and the second terminal of the output transistor together serve as the output terminal. The first control terminal and the first terminal of the pull-down transistor are electrically connected to the fourth node and the second terminal of the output transistor, respectively. The second terminal of the pull-down transistor is the third terminal of the output sub-circuit and is electrically connected to the fifth level signal terminal.

8. The integrated circuit unit according to claim 1, characterized in that, The first pull-down control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The control electrode and the first electrode of the fourteenth transistor are electrically connected to the second-level signal terminal, respectively. The second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor. The control electrode of the fifteenth transistor is electrically connected to the second-level signal terminal. The second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor. The second electrode of the sixteenth transistor is electrically connected to the third-level signal terminal. The control electrode of the sixteenth transistor serves as the first control terminal of the pull-down control sub-circuit and is electrically connected to the third node. The first electrode of the seventeenth transistor is connected to the second-level signal terminal, and the second electrode of the seventeenth transistor is electrically connected to the fourth node.

9. The integrated circuit unit according to claim 1, characterized in that, The first pull-down control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The control electrode and the first electrode of the fourteenth transistor are electrically connected to the second-level signal terminal, respectively. The second electrode of the fourteenth transistor is electrically connected to the first electrode and the control electrode of the fifteenth transistor. The second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the seventeenth transistor. The second electrode of the sixteenth transistor is electrically connected to the third-level signal terminal. The control electrode of the sixteenth transistor serves as the first control terminal of the pull-down control sub-circuit and is electrically connected to the third node. The first electrode of the seventeenth transistor is connected to the second-level signal terminal. The second electrode of the seventeenth transistor is electrically connected to the fourth node.

10. The integrated circuit unit according to claim 8 or 9, characterized in that, The first pull-down control sub-circuit also includes an eighteenth transistor, whose control electrode, first electrode, and second electrode are electrically connected to the third node, the fourth node, and the fourth level signal terminal, respectively.

11. The integrated circuit unit according to claim 1, characterized in that, The number of the first pull-down control sub-circuit, the second pull-down control sub-circuit, and the pull-down sub-circuit is multiple.

12. The integrated circuit unit according to claim 1, characterized in that, The second pull-down control sub-circuit includes a 37th transistor and a 38th transistor. The control electrode and the first electrode of the 37th transistor are respectively connected to the second node and the fourth node. The second electrode of the 37th transistor is electrically connected to the second electrode of the 38th transistor. The control electrode and the second electrode of the 38th transistor are respectively electrically connected to the fourth clock signal terminal and the fourth level signal terminal.

13. The integrated circuit unit according to claim 1, characterized in that, The integrated circuit unit further includes a reset sub-circuit, which is electrically connected to the reset signal terminal, the first level signal terminal, the second node, the fourth node, and the fourth level signal terminal, respectively.

14. The integrated circuit unit according to claim 13, characterized in that, The reset sub-circuit includes a nineteenth transistor, a twentieth transistor, and a twenty-second transistor. The control electrodes of the nineteenth, twentieth, and twenty-second transistors are electrically connected to the reset signal terminal. The first electrode of the nineteenth transistor is electrically connected to the first level signal terminal. The second electrode of the nineteenth transistor is electrically connected to the fourth node. The first electrode of the twenty-second transistor is electrically connected to the second node. The second electrode of the twenty-second transistor is electrically connected to the first electrode of the twentieth transistor. The second electrode of the twentieth transistor is electrically connected to the fourth level signal terminal.

15. The integrated circuit unit according to claim 1, characterized in that, The integrated circuit unit also includes a leakage protection electronic circuit, wherein the first control electrode, the first terminal, and the second terminal of the leakage protection electronic circuit are electrically connected to the third node, the first level signal terminal, and the pull-down sub-circuit, respectively.

16. The integrated circuit unit according to claim 1, characterized in that, The integrated circuit unit further includes a third pull-down sub-circuit, which is electrically connected to the second clock signal terminal, the third clock signal terminal, and the first node, respectively, and controls the first node according to the second clock signal terminal and the third clock signal terminal.

17. The integrated circuit unit according to claim 1, characterized in that, In one cycle of each of the aforementioned strobe signal terminals, the high-level width of the strobe signal is equal to the low-level width.

18. A gate driving circuit, characterized in that, It includes multiple integrated circuit unit groups, each group including at least one integrated circuit unit as described in any one of claims 1-17, wherein the number of gating signal terminals is twice the number of gating transistors, and each gating signal terminal includes a plurality of positive gating signal terminals and a plurality of inverse gating signal terminals whose signals are opposite to those of the positive gating signal terminals.

19. The gate driving circuit according to claim 18, characterized in that, The integrated circuit unit group includes four integrated circuit units. The integrated circuit units in the same group are connected to the selected communication terminal in the same way, but the connection order of the integrated circuit units in the same group to each clock signal terminal is different.

20. The gate driving circuit according to claim 19, characterized in that, The connections between the integrated circuit units in different groups and the strobe signal terminals are different.

21. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 18-20.

Images