Gate drive circuit

Abstract

The application provides a gate driving circuit, and belongs to the technical field of display. An alternating switching module outputs a first n-th stage switching signal according to an n-th stage reverse signal and a first local clock signal. The alternating switching module outputs a second n-th stage switching signal according to the n-th stage reverse signal and a second local clock signal. The first local clock signal is opposite to the second local clock signal. A pull-down maintaining module pulls down and maintains the potential of an n-th stage control signal and the potential of an n-th stage gate driving signal to a reference low potential according to the first n-th stage switching signal or the second n-th stage switching signal. Under the control of the first n-th stage switching signal or the second n-th stage switching signal alternately output by the alternating switching module, each transistor in the pull-down maintaining module can be alternately turned on and operated, so that the problem of forward drift of threshold voltage caused by the long-time opening of the transistor in the pull-down maintaining module is solved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a gate driving circuit. Background Technology

[0002] The Gate Driver on Array (GOA) circuit integrates the gate driver circuit of the display panel onto the glass substrate, forming a scanning driver for the display panel. The GOA driving circuit significantly reduces manufacturing costs and allows for a reduction in the bezel size of the display panel.

[0003] In traditional circuits, the thin-film transistor (TFT) in the pull-down sustaining module is kept on for a long time, which causes the threshold voltage (Vth) of the TFT to drift forward quickly, which can easily lead to the failure of the pull-down sustaining function and cause abnormalities in the GOA driving circuit. Utility Model Content

[0004] The purpose of this application is to provide a gate drive circuit that aims to solve the problem of pull-down sustaining function failure caused by the rapid positive drift of the threshold voltage of the thin-film transistor in the pull-down sustaining module of a conventional circuit.

[0005] This application provides a gate driving circuit, including a multi-stage sub-driving circuit connected in cascades, wherein the nth stage sub-driving circuit includes:

[0006] The pull-up control module is used to output the nth-level control signal based on the (n-3)th-level gate drive signal of the (n-3)th-level sub-drive circuit; where n is an integer greater than 3.

[0007] A pull-up module, connected to the pull-up control module, is used to output the nth-stage gate drive signal according to the nth-stage control signal and the nth-stage clock signal;

[0008] An inverter module is used to obtain an nth-stage inverted signal based on a reference high-potential signal and the nth-stage control signal.

[0009] An alternating switching module, connected to the inverter module, is used to output a first nth-level switching signal based on the nth-level inverted signal and a first local clock signal. The alternating switching module is also used to output a second nth-level switching signal based on the nth-level inverted signal and a second local clock signal; wherein the first local clock signal is opposite to the second local clock signal.

[0010] A pull-down sustaining module, connected to the alternating switching module and the pull-up module, is used to pull down and maintain the potential of the nth level control signal to a reference low potential according to the first nth level switching signal or the second nth level switching signal, and to pull down and maintain the potential of the nth level gate drive signal to the reference low potential.

[0011] In one embodiment, the nth-level sub-driving circuit further includes:

[0012] A pull-down module, connected to the pull-up module, is used to pull down the potential of the nth stage control signal to the reference low potential according to the gate drive signal of the (n+4)th stage of the (n+4)th stage sub-drive circuit.

[0013] In one embodiment, the nth-level sub-driving circuit further includes:

[0014] The first reset module, connected to the pull-up module, is used to reset the potentials of the nth stage control signal and the nth stage gate drive signal to the reference low potential according to the reset signal during the reset time.

[0015] In one embodiment, the nth-level sub-driving circuit further includes:

[0016] The second reset module, connected to the inverter module, is used to reset the potential of the nth-stage inverted signal to the reference low potential according to the reset signal within the reset time.

[0017] In one embodiment, the inverter module includes:

[0018] A first transistor, wherein a first terminal and a second terminal of the first transistor are connected, is used to acquire the reference high potential signal;

[0019] The second transistor has a first terminal connected to the third terminal of the first transistor. The second terminal of the second transistor is used to acquire the reference high-potential signal, and the third terminal of the second transistor is used to output the nth-level inverted signal.

[0020] The third transistor has a first terminal for acquiring the nth stage control signal, a second terminal for being connected to the first terminal of the second transistor, and a third terminal for acquiring the reference low potential.

[0021] A fourth transistor, wherein the first terminal of the fourth transistor is used to acquire the nth stage control signal, the second terminal of the fourth transistor is connected to the third terminal of the second transistor, and the third terminal of the fourth transistor is used to acquire the reference low potential.

[0022] In one embodiment, the alternation module includes:

[0023] The fifth transistor has a first terminal for acquiring the first local clock signal, a second terminal connected to the third terminal of the second transistor for acquiring the nth-stage inverted signal, and a third terminal for outputting the first nth-stage switching signal.

[0024] The sixth transistor has a first terminal for acquiring the second local clock signal, a second terminal connected to the third terminal of the second transistor for acquiring the nth-stage inverted signal, and a third terminal for outputting the second nth-stage switching signal.

[0025] In one embodiment, the pull-down sustaining module includes:

[0026] The seventh transistor has its first terminal connected to the third terminal of the fifth transistor for acquiring the first nth stage switching signal, its second terminal connected to the pull-up control module for acquiring the nth stage control signal, and its third terminal for acquiring the reference low potential.

[0027] The eighth transistor has its first terminal connected to the third terminal of the fifth transistor for acquiring the first nth stage switching signal, its second terminal connected to the pull-up module for acquiring the nth stage gate drive signal, and its third terminal for acquiring the reference low potential.

[0028] In one embodiment, the pull-down sustaining module includes:

[0029] The ninth transistor has its first terminal connected to the third terminal of the sixth transistor for acquiring the second nth stage switching signal, its second terminal connected to the pull-up control module for acquiring the nth stage control signal, and its third terminal for acquiring the reference low potential.

[0030] The tenth transistor has its first terminal connected to the third terminal of the sixth transistor for acquiring the second nth stage switching signal, its second terminal connected to the pull-up module for acquiring the nth stage gate drive signal, and its third terminal for acquiring the reference low potential.

[0031] In one embodiment, the first reset module includes:

[0032] The eleventh transistor has a first terminal for acquiring the reset signal, a second terminal for being connected to the pull-up module for acquiring the nth gate drive signal, and a third terminal for acquiring the reference low potential.

[0033] The twelfth transistor has a first terminal for acquiring the reset signal, a second terminal connected to the pull-up control module for acquiring the nth stage control signal, and a third terminal for acquiring the reference low potential.

[0034] In one embodiment, the second reset module includes:

[0035] The thirteenth transistor has a first terminal for acquiring the reset signal, a second terminal for being connected to the inverter module for acquiring the nth-stage inverted signal, and a third terminal for acquiring the reference low potential.

[0036] The beneficial effects of this utility model embodiment compared with the prior art are:

[0037] The (n-3)th stage gate drive signal Gn-3 of the (n-3)th stage sub-driver circuit is input to the pull-up control module as the start signal of the current stage n sub-driver circuit. The pull-up control module outputs the nth stage control signal Qn based on the (n-3)th stage gate drive signal Gn-3 to activate the pull-up module. Then, the pull-up module outputs the nth stage gate drive signal Gn based on the nth stage control signal Qn and the nth stage clock signal CLK. Both the nth stage control signal Qn and the nth stage gate drive signal Gn are signals from the current stage n sub-driver circuit.

[0038] The nth-stage control signal Qn serves as the main input signal of the inverter module. The nth-stage inverting signal Kn serves as the output signal of the inverter module. The inverter module reverses the nth-stage control signal Qn and the nth-stage inverting signal Kn; that is, when the nth-stage control signal Qn is high, the nth-stage inverting signal Kn is low, and vice versa. The inverter module charges the transistors in the inverter module based on the reference high-level signal VGH, causing the nth-stage inverting signal Kn to become high, thus enabling the alternating switching module to operate.

[0039] The first local clock signal LC1 and the second local clock signal LC2 are two opposite clock signals, which can also be understood as a set of signals that alternately switch between high and low levels. When the first local clock signal LC1 is high, the second local clock signal LC2 is low. When the first local clock signal LC1 is low, the second local clock signal LC2 is high. The alternating switching module outputs the first nth-level switching signal Pn1 based on the nth-level inverted signal Kn and the first local clock signal LC1. The alternating switching module outputs the second nth-level switching signal Pn2 based on the nth-level inverted signal Kn and the second local clock signal LC2. By making the first local clock signal LC1 and the second local clock signal LC2 opposite, the alternating switching module can alternately output the first nth-level switching signal Pn1 and the second nth-level switching signal Pn2 under the control of the first local clock signal LC1 and the second local clock signal LC2, respectively.

[0040] Furthermore, under the control of the first nth-stage switching signal Pn1 or the second nth-stage switching signal Pn2 alternately output by the alternating switching module, the pull-down sustaining module pulls down and maintains the potential of the nth-stage control signal Qn and the potential of the nth-stage gate drive signal Gn to the reference low potential VSS. Under the control of the first nth-stage switching signal Pn1 or the second nth-stage switching signal Pn2 alternately output by the alternating switching module, the transistors in the pull-down sustaining module can be controlled to conduct alternately, reducing the forward bias effect on the transistors in the pull-down sustaining module, solving the problem of forward drift of the threshold voltage (Vth) caused by the transistors being in the on state for a long time in the pull-down sustaining module, and extending the life of each transistor.

[0041] Therefore, the pull-down sustaining module pulls down and maintains the potentials of the nth-stage control signal Qn and the nth-stage gate drive signal Gn to a reference low potential VSS according to the first nth-stage switching signal Pn1 or the second nth-stage switching signal Pn2, ensuring the gate drive circuit can guarantee the function of the pull-down sustaining module. Thus, the gate drive circuit provided in this application can more stably and reliably turn the thin-film transistors of the display panel on or off, avoiding malfunctions in the gate drive circuit. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1The circuit structure diagrams of the gate drive circuits in some embodiments provided in this application are shown.

[0044] Figure 2 The circuit connection structure diagrams of the inverter module, the alternation switching module, and the pull-down sustaining module in some embodiments provided in this application are shown.

[0045] Figure 3 A schematic diagram of the circuit connection structure between the pull-down module and the first reset module in some embodiments provided in this application.

[0046] Figure 4 The circuit connection structure diagram of the second reset module, the pull-up control module, and the pull-up module in some embodiments provided in this application is shown.

[0047] Figure 5 The following are schematic diagrams of signal input waveforms in some embodiments provided in this application. Detailed Implementation

[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0050] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. Additionally, in the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items that have substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution, and that "first" and "second" do not necessarily imply difference.

[0052] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0053] Please see Figure 1 This application provides a gate driving circuit. The gate driving circuit includes cascaded multi-stage sub-driving circuits. The nth stage sub-driving circuit includes a pull-up control module 10, a pull-up module 20, an inverter module 30, an alternating switching module 40, and a pull-down sustaining module 50. The pull-up control module 10 is used to output the nth stage control signal Qn according to the (n-3)th stage gate driving signal Gn-3 of the (n-3)th stage sub-driving circuit. The pull-up module 20 is connected to the pull-up control module 10 and is used to output the nth stage gate driving signal Gn according to the nth stage control signal Qn and the nth stage clock signal CLK. The inverter module 30 is used to obtain the nth stage inverted signal Kn according to the reference high potential signal VGH and the nth stage control signal Qn.

[0054] The alternating switching module 40 is connected to the inverter module 30 and is used to output a first nth-stage switching signal Pn1 based on the nth-stage inverted signal Kn and the first local clock signal LC1. The alternating switching module 40 is also used to output a second nth-stage switching signal Pn2 based on the nth-stage inverted signal Kn and the second local clock signal LC2. The first local clock signal LC1 and the second local clock signal LC2 are opposite.

[0055] The pull-down sustaining module 50 is connected to the alternating switching module 40 and the pull-up module 20, and is used to pull down and maintain the potential of the nth stage control signal Qn and the potential of the nth stage gate drive signal Gn to a reference low potential VSS according to the first nth stage switching signal Pn1 or the second nth stage switching signal Pn2. Here, n is an integer greater than 3.

[0056] In this embodiment, the nth-level gate drive signal Gn output by the nth-level sub-driving circuit can drive the pixel units of a row. Multiple sub-driving circuits are cascaded to form a gate drive circuit. Furthermore, gate drive signals are transmitted between the multiple sub-driving circuits. The (n-3)th-level gate drive signal Gn-3 of the (n-3)th-level sub-driving circuit is input to the pull-up control module 10 as the start signal of the current nth-level sub-driving circuit. The pull-up control module 10 outputs the nth-level control signal Qn based on the (n-3)th-level gate drive signal Gn-3 to activate the pull-up module 20. Then, the pull-up module 20 outputs the nth-level gate drive signal Gn based on the nth-level control signal Qn and the nth-level clock signal CLK. Both the nth-level control signal Qn and the nth-level gate drive signal Gn are signals from the current nth-level sub-driving circuit.

[0057] The nth-stage control signal Qn serves as the main input signal of the inverter module 30. The nth-stage inverted signal Kn serves as the output signal of the inverter module 30. The inverter module 30 reverses the nth-stage control signal Qn and the nth-stage inverted signal Kn; that is, when the nth-stage control signal Qn is high, the nth-stage inverted signal Kn is low, and vice versa. The inverter module 30 can charge the transistors in the inverter module 30 according to the reference high-level signal VGH, causing the nth-stage inverted signal Kn to become high, thus enabling the alternation module 40 to operate.

[0058] The first local clock signal LC1 and the second local clock signal LC2 are two opposite clock signals, which can also be understood as a set of signals that alternately switch between high and low levels. When the first local clock signal LC1 is at a high level, the second local clock signal LC2 is at a low level. When the first local clock signal LC1 is at a low level, the second local clock signal LC2 is at a high level. The alternating switching module 40 outputs the first nth level switching signal Pn1 based on the nth level inverted signal Kn and the first local clock signal LC1. The alternating switching module 40 outputs the second nth level switching signal Pn2 based on the nth level inverted signal Kn and the second local clock signal LC2. By making the first local clock signal LC1 and the second local clock signal LC2 opposite, the alternating switching module 40 can alternately output the first nth level switching signal Pn1 and the second nth level switching signal Pn2 under the control of the first local clock signal LC1 and the second local clock signal LC2, respectively.

[0059] Furthermore, under the control of the first nth-stage switching signal Pn1 or the second nth-stage switching signal Pn2 alternately output by the alternating switching module 40, the pull-down sustaining module 50 pulls down and maintains the potential of the nth-stage control signal Qn and the potential of the nth-stage gate drive signal Gn to the reference low potential VSS. Under the control of the first nth-stage switching signal Pn1 or the second nth-stage switching signal Pn2 alternately output by the alternating switching module 40, the transistors in the pull-down sustaining module 50 can be controlled to conduct alternately, reducing the forward bias effect on the transistors in the pull-down sustaining module 50, solving the problem of forward drift of the threshold voltage (Vth) caused by the transistors in the pull-down sustaining module 50 being in the on state for a long time, and extending the life of each transistor.

[0060] Therefore, the pull-down sustaining module 50 pulls down and maintains the potentials of the nth-stage control signal Qn and the nth-stage gate drive signal Gn to a reference low potential VSS according to the first nth-stage switching signal Pn1 or the second nth-stage switching signal Pn2, ensuring the gate drive circuit can guarantee the function of the pull-down sustaining module 50. Thus, the gate drive circuit provided in this application can more stably and reliably turn the thin-film transistors of the display panel on or off, avoiding malfunctions in the gate drive circuit.

[0061] In one embodiment, the nth-level sub-driving circuit further includes a pull-down module 60. The pull-down module 60 is connected to the pull-up module 20 and is used to pull down the potential of the nth-level control signal Qn to a reference low potential VSS according to the (n+4)th-level gate drive signal Gn+4 of the (n+4)th-level sub-driving circuit.

[0062] In this embodiment, the pull-down module 60 pulls down the nth-level control signal Qn, ensuring that when the nth-level control signal Qn needs to be at a low potential, it can be accurately set to a low potential, thus ensuring the stability of the nth-level control signal Qn and preventing pixel malfunctions or leakage. The pull-down maintenance module 50 and the pull-down module 60 complement each other functionally and coordinate in timing. After the pull-down module 60 pulls the potential down, it continuously maintains a low potential state, effectively suppressing various parasitic capacitances and external interference in the circuit, ensuring stability at a low potential during the required time period, and improving the stability and reliability of the gate drive circuit.

[0063] In one embodiment, the nth-stage sub-driving circuit further includes a first reset module 70. The first reset module 70 is connected to the pull-up module 20 and is used to reset the potentials of the nth-stage control signal Qn and the nth-stage gate drive signal Gn to a reference low potential VSS according to the reset signal Reset during the reset time.

[0064] In this embodiment, the input terminal of the first reset module 70 is connected to the reset signal Reset. During the reset time, the first reset module 70 resets the potentials of the nth stage control signal Qn and the nth stage gate drive signal Gn to the reference low potential VSS, achieving a low-potential reset. The first reset module 70 eliminates signal residue in the nth stage control signal Qn and the nth stage gate drive signal Gn of the gate drive circuit, effectively clearing residual charge on the nodes, enhancing the stability of the gate drive circuit, and ensuring that the gate drive circuit can start up normally and operate stably.

[0065] In one embodiment, the nth-stage sub-driving circuit further includes a second reset module 80. The second reset module 80 is connected to the inverter module 30 and is used to reset the potential of the nth-stage inverted signal Kn to the reference low potential VSS according to the reset signal Reset during the reset time.

[0066] In this embodiment, the input terminal of the second reset module 80 is connected to the reset signal Reset. During the reset time, the second reset module 80 resets the potential of the nth-stage inverted signal Kn to the reference low potential VSS, achieving a low-potential reset. The second reset module 80 eliminates the signal residue of the nth-stage inverted signal Kn in the gate drive circuit, effectively clearing residual charge on the node, enhancing the stability of the gate drive circuit, and ensuring that the gate drive circuit can start up normally and operate stably.

[0067] Please see Figure 2In one embodiment, the inverter module 30 includes a first transistor 310, a second transistor 320, a third transistor 330, and a fourth transistor 340. The first and second terminals of the first transistor 310 are connected to acquire a reference high-level signal VGH. The first terminal of the second transistor 320 is connected to the third terminal of the first transistor 310, the second terminal of the second transistor 320 is used to acquire the reference high-level signal VGH, and the third terminal of the second transistor 320 is used to output the nth-stage inverted signal Kn.

[0068] The first terminal of the third transistor 330 is used to acquire the nth-stage control signal Qn. The second terminal of the third transistor 330 is connected to the first terminal of the second transistor 320. The third terminal of the third transistor 330 is used to acquire the reference low potential VSS. The first terminal of the fourth transistor 340 is used to acquire the nth-stage control signal Qn. The second terminal of the fourth transistor 340 is connected to the third terminal of the second transistor 320. The third terminal of the fourth transistor 340 is used to acquire the reference low potential VSS.

[0069] In this embodiment, the inverter module 30 receives a reference high-potential signal VGH and an nth-stage control signal Qn, and outputs an nth-stage inverted signal Kn with a potential opposite to that of the nth-stage control signal Qn. The reference high-potential signal VGH is introduced by connecting the first and second terminals of the first transistor 310 in a diode configuration. The reference high-potential signal VGH is also connected to the second terminal of the second transistor 320. The reference high-potential signal VGH can charge the first transistor 310 and the second transistor 320, causing the nth-stage inverted signal Kn to become high, thus assisting the operation of the alternating switching module 40.

[0070] The nth-stage control signal Qn is introduced through the first terminal of the third transistor 330 and the first terminal of the fourth transistor 340. The second terminal of the fourth transistor 340 is connected to the third terminal of the second transistor 320, and the nth-stage inverted signal Kn is output to the alternating switching module 40 to assist the fifth transistor 410 and the sixth transistor 420 in the alternating switching module 40 to work.

[0071] In one embodiment, when the nth-stage control signal Qn in the inverter module 30 is high, the nth-stage inversion signal Kn is low, and the third transistor 330 and the fourth transistor 340 are turned on. When the nth-stage control signal Qn is low, the third transistor 330 and the fourth transistor 340 are turned off and do not conduct, and the nth-stage inversion signal Kn is high. When the nth-stage inversion signal Kn is high, the second terminals of the fifth transistor 410 and the sixth transistor 420 are high, and under the control of the first local clock signal LC1 and the second local clock signal LC2 respectively, the first nth-stage switching signal Pn1 and the second nth-stage switching signal Pn2 are alternately output.

[0072] In one embodiment, the alternating switching module 40 includes a fifth transistor 410 and a sixth transistor 420. The first terminal of the fifth transistor 410 is used to acquire a first local clock signal LC1, the second terminal of the fifth transistor 410 is connected to the third terminal of the second transistor 320, and is used to acquire the nth-level inverted signal Kn. The third terminal of the fifth transistor 410 is used to output the first nth-level switching signal Pn1.

[0073] The first terminal of the sixth transistor 420 is used to acquire the second local clock signal LC2. The second terminal of the sixth transistor 420 is connected to the third terminal of the second transistor 320 to acquire the nth stage inverted signal Kn. The third terminal of the sixth transistor 420 is used to output the second nth stage switching signal Pn2.

[0074] In this embodiment, a first local clock signal LC1 is introduced into the first terminal of the fifth transistor 410. Under the control of the first local clock signal LC1, the fifth transistor 410 is controlled to be turned on or off (not turned on). When the first local clock signal LC1 is at a high level, the fifth transistor 410 is controlled to be turned on. When the fifth transistor 410 is turned on, if the nth stage inverted signal Kn is at a high level, then the first nth stage switching signal Pn1 output is at a high level, controlling the seventh transistor 510 and the eighth transistor 520 to be turned on simultaneously. At this time, the first local clock signal LC1 is opposite to the second local clock signal LC2, and the second local clock signal LC2 is at a low level, controlling the sixth transistor 420 to be turned off (not turned on), thereby causing the ninth transistor 530 and the tenth transistor 540 to be turned off (not turned on) simultaneously.

[0075] When the first local clock signal LC1 is low, the fifth transistor 410 is turned off (not conducting), which in turn causes the seventh transistor 510 and the eighth transistor 520 to be turned off (not conducting) simultaneously. At this time, the second local clock signal LC2 is high, controlling the sixth transistor 420 to conduct. When the sixth transistor 420 is conducting, if the nth stage inverting signal Kn is high, then the output second nth stage switching signal Pn2 is high, controlling the ninth transistor 530 and the tenth transistor 540 to conduct simultaneously.

[0076] In one embodiment, the pull-down sustaining module 50 includes a seventh transistor 510 and an eighth transistor 520. The first terminal of the seventh transistor 510 is connected to the third terminal of the fifth transistor 410 for acquiring the first nth-stage switching signal Pn1, the second terminal of the seventh transistor 510 is connected to the pull-up control module 10 for acquiring the nth-stage control signal Qn, and the third terminal of the seventh transistor 510 is used to acquire the reference low potential VSS.

[0077] The first terminal of the eighth transistor 520 is connected to the third terminal of the fifth transistor 410 to obtain the first nth stage switching signal Pn1. The second terminal of the eighth transistor 520 is connected to the pull-up module 20 to obtain the nth stage gate drive signal Gn. The third terminal of the eighth transistor 520 is used to obtain the reference low potential VSS.

[0078] In this embodiment, by alternating the switching of the fifth transistor 410 and the sixth transistor 420 in the switching module 40, when the first local clock signal LC1 is at a high potential and the second local clock signal LC2 is at a low potential, the first nth level switching signal Pn1 is at a high potential and the second nth level switching signal Pn2 is at a low potential, controlling the seventh transistor 510 and the eighth transistor 520 to be turned on simultaneously, while the ninth transistor 530 and the tenth transistor 540 are turned off simultaneously (not turned on).

[0079] By alternating the switching of the fifth transistor 410 and the sixth transistor 420 in the alternating switching module 40, when the first local clock signal LC1 is at a low potential and the second local clock signal LC2 is at a high potential, the first nth level switching signal Pn1 is at a low potential and the second nth level switching signal Pn2 is at a high potential, the seventh transistor 510 and the eighth transistor 520 are controlled to be turned off simultaneously (not turned on), and the ninth transistor 530 and the tenth transistor 540 are turned on simultaneously.

[0080] Therefore, when the seventh transistor 510 is turned on, the nth stage control signal Qn is pulled down and maintained at the reference low potential VSS. When the eighth transistor 520 is turned on, the nth stage gate drive signal Gn is pulled down and maintained at the reference low potential VSS.

[0081] In one embodiment, the pull-down sustaining module 50 includes a ninth transistor 530 and a tenth transistor 540. The first terminal of the ninth transistor 530 is connected to the third terminal of the sixth transistor 420 for acquiring a second nth-stage switching signal Pn2. The second terminal of the ninth transistor 530 is connected to the pull-up control module 10 for acquiring an nth-stage control signal Qn. The third terminal of the ninth transistor 530 is used to acquire a reference low potential VSS.

[0082] The first terminal of the tenth transistor 540 is connected to the third terminal of the sixth transistor 420 to obtain the second nth stage switching signal Pn2. The second terminal of the tenth transistor 540 is connected to the pull-up module 20 to obtain the nth stage gate drive signal Gn. The third terminal of the tenth transistor 540 is used to obtain the reference low potential VSS.

[0083] In this embodiment, when the ninth transistor 530 is turned on, the nth stage control signal Qn is pulled down and maintained at the reference low potential VSS. When the tenth transistor 540 is turned on, the nth stage gate drive signal Gn is pulled down and maintained at the reference low potential VSS.

[0084] The seventh transistor 510 and the ninth transistor 530 operate alternately to pull down the potential of the nth stage control signal Qn and maintain it at the reference low potential VSS. The eighth transistor 520 and the tenth transistor 540 operate alternately to pull down the potential of the nth stage gate drive signal Gn and maintain it at the reference low potential VSS.

[0085] By alternating the operation of the seventh transistor 510 and the ninth transistor 530, and the eighth transistor 520 and the tenth transistor 540, the transistors in the pull-down sustaining module 50 are in the off state for half the time, which can reduce the forward bias voltage on the transistors and solve the problem of forward drift of the transistor threshold voltage (Vth).

[0086] Please see Figure 3 In one embodiment, the first reset module 70 includes an eleventh transistor 710 and a twelfth transistor 720. The first terminal of the eleventh transistor 710 is used to acquire a reset signal Reset, the second terminal of the eleventh transistor 710 is connected to the pull-up module 20 and is used to acquire the nth gate drive signal Gn, and the third terminal of the eleventh transistor 710 is used to acquire a reference low potential VSS.

[0087] The first terminal of the twelfth transistor 720 is used to obtain the reset signal Reset. The second terminal of the twelfth transistor 720 is connected to the pull-up control module 10 and is used to obtain the nth level control signal Qn. The third terminal of the twelfth transistor 720 is used to obtain the reference low potential VSS.

[0088] In this embodiment, when the reset signal Reset is high, the first terminal of the eleventh transistor 710 is turned on under the control of the reset signal Reset. During the reset time, the eleventh transistor 710 pulls the potential of the nth gate drive signal Gn down to the reference low potential VSS. When the reset signal Reset is low, the eleventh transistor 710 is turned off and does not conduct.

[0089] When the reset signal Reset is high, the first terminal of the twelfth transistor 720 is turned on under the control of the reset signal Reset. During the reset time, the twelfth transistor 720 pulls the potential of the nth stage control signal Qn down to the reference low potential VSS. When the reset signal Reset is low, the twelfth transistor 720 is turned off and does not conduct.

[0090] The eleventh transistor 710 and the twelfth transistor 720 respectively reset the nth-stage gate drive signal Gn and the nth-stage control signal Qn, which can more accurately and effectively clear the residual charge on the corresponding node, enhance the stability of the gate drive circuit, and ensure that the gate drive circuit can start up normally and work stably, thereby improving the display quality.

[0091] Please see Figure 4 In one embodiment, the second reset module 80 includes a thirteenth transistor 810. The first terminal of the thirteenth transistor 810 is used to acquire a reset signal Reset, the second terminal of the thirteenth transistor 810 is connected to the inverter module 30 and is used to acquire an nth-stage inverted signal Kn, and the third terminal of the thirteenth transistor 810 is used to acquire a reference low potential VSS.

[0092] In this embodiment, when the reset signal Reset is high, the first terminal of the thirteenth transistor 810 is turned on under the control of the reset signal Reset. During the reset time, the potential of the nth stage inverted signal Kn is pulled down to the reference low potential VSS through the thirteenth transistor 810. When the reset signal Reset is low, the thirteenth transistor 810 is turned off and does not conduct.

[0093] In one embodiment, the pull-down module 60 includes a fourteenth transistor 610. A first terminal of the fourteenth transistor 610 is used to acquire the (n+4)th stage gate drive signal Gn+4, a second terminal of the fourteenth transistor 610 is used to acquire the nth stage control signal Qn, and a third terminal of the fourteenth transistor 610 is used to acquire a reference low potential VSS.

[0094] In this embodiment, when the (n+4)th stage gate drive signal Gn+4 is high, the fourteenth transistor 610 is turned on, pulling the potential of the nth stage control signal Qn down to the reference low potential VSS. When the (n+4)th stage gate drive signal Gn+4 is low, the fourteenth transistor 610 is turned off and not turned on. The (n+4)th stage gate drive signal Gn+4 enables the interaction of trigger signals in each cascaded circuit in the gate drive circuit, thereby achieving line-by-line scan drive, ensuring the accuracy of the timing of the cascaded circuits, and achieving synchronization between the cascaded circuits.

[0095] In one embodiment, the pull-up control module 10 includes a fifteenth transistor 110. The first and second terminals of the fifteenth transistor 110 are connected to acquire the (n-3)th stage gate drive signal Gn-3, and the third terminal of the fifteenth transistor 110 is used to output the nth stage control signal Qn.

[0096] In this embodiment, the fifteenth transistor 110 is connected in a diode configuration. The fifteenth transistor 110 is turned on by the (n-3)th stage gate drive signal Gn-3, outputting the nth stage control signal Qn of the control node. The nth stage control signal Qn serves as the input signal to the sixteenth transistor 210 in the pull-up module 20 and as the input signal to the third transistor 330 in the inverter module 30.

[0097] In one embodiment, the first terminal of each transistor in the above embodiment is the gate terminal, the second terminal of each transistor is the drain terminal, and the third terminal of each transistor is the source terminal.

[0098] In one embodiment, the pull-up module 20 includes a sixteenth transistor 210 and a capacitor 220. The first terminal of the sixteenth transistor 210 is used to acquire the nth-stage control signal Qn, the second terminal of the sixteenth transistor 210 is used to acquire the nth-stage clock signal CLK, and the third terminal of the sixteenth transistor 210 is used to output the nth-stage gate drive signal Gn.

[0099] One end of capacitor 220 is connected to the first end of sixteenth transistor 210, and the other end of capacitor 220 is connected to the third end of sixteenth transistor 210.

[0100] In this embodiment, the input signals of the pull-up module 20 are the nth-stage control signal Qn and the nth-stage clock signal CLK, and the output signal is the nth-stage gate drive signal Gn. The seventh transistor 510, the ninth transistor 530, and the fourteenth transistor 610 pull down the potential of the nth-stage control signal Qn input to the first terminal of the sixteenth transistor 210 and maintain it at a reference low potential VSS. The eighth transistor 520 and the tenth transistor 540 pull down the potential of the nth-stage gate drive signal Gn output from the third terminal of the sixteenth transistor 210 and maintain it at a reference low potential VSS.

[0101] The capacitor 220 is connected between the first and third terminals of the sixteenth transistor 210, that is, between the gate terminal and the source terminal, and plays the role of storing charge, stabilizing voltage, and coupling and transmitting signals.

[0102] Please see Figure 5 In one embodiment, the input waveforms of the various signals of the gate drive circuit are as follows: Figure 5As shown. The start signal STV is used to initialize the gate drive circuit and start the first-stage sub-drive circuit. Taking 6 CLKs as an example, such as CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6. The reference low potential VSS is always in a low-level state. During the reset time, the reset signal Reset is in a high-level state. The first local clock signal LC1 and the second local clock signal LC2 are a set of opposite local clock signals. When the first local clock signal LC1 is low, the second local clock signal LC2 is high. When the first local clock signal LC1 is high, the second local clock signal LC2 is low. The nth-stage control signal Qn and the nth-stage inverted signal Kn are inversely related. During the reset time, according to the high potential state of the reset signal Reset, the thirteenth transistor 810 resets the nth-stage inverted signal Kn to a low potential.

[0103] This application provides a display panel including the gate driving circuit of any of the above embodiments. This application can be widely applied to various display panels and devices having display panels, such as mobile phones, laptop computers, and LCD TVs.

[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0109] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The nth-level sub-drive circuit includes cascaded sub-drive circuits. Pull-up control module (10) is used to output the nth level control signal according to the n-3rd level gate drive signal of the n-3rd level sub-drive circuit; where n is an integer greater than 3; Pull-up module (20), connected to the pull-up control module (10), is used to output the nth gate drive signal according to the nth level control signal and the nth level clock signal; Inverter module (30) is used to obtain the nth stage inverted signal based on the reference high potential signal and the nth stage control signal; An alternating switching module (40), connected to the inverter module (30), is used to output a first nth-level switching signal based on the nth-level inverted signal and the first local clock signal. The alternating switching module (40) is also used to output a second nth-level switching signal based on the nth-level inverted signal and the second local clock signal. The first local clock signal is opposite to the second local clock signal. The pull-down sustaining module (50), connected to the alternating switching module (40) and the pull-up module (20), is used to pull down and maintain the potential of the nth level control signal and the potential of the nth level gate drive signal to a reference low potential according to the first nth level switching signal or the second nth level switching signal.

2. The gate driving circuit as described in claim 1, characterized in that, The nth-level sub-driving circuit also includes: The pull-down module (60), connected to the pull-up module (20), is used to pull down the potential of the nth level control signal to the reference low potential according to the gate drive signal of the n+4th level sub-drive circuit.

3. The gate driving circuit as described in claim 1, characterized in that, The nth-level sub-driving circuit also includes: The first reset module (70) is connected to the pull-up module (20) and is used to reset the potentials of the nth level control signal and the nth level gate drive signal to the reference low potential according to the reset signal during the reset time.

4. The gate driving circuit as described in claim 1, characterized in that, The nth-level sub-driving circuit also includes: The second reset module (80) is connected to the inverter module (30) and is used to reset the potential of the nth level inverted signal to the reference low potential according to the reset signal during the reset time.

5. The gate driving circuit as described in any one of claims 1 to 4, characterized in that, The inverter module (30) includes: A first transistor (310) is connected at its first and second ends to acquire the reference high potential signal; The second transistor (320) has a first terminal connected to the third terminal of the first transistor (310), a second terminal of the second transistor (320) for acquiring the reference high potential signal, and a third terminal of the second transistor (320) for outputting the nth level inverted signal. A third transistor (330) is used to acquire the nth level control signal. The second terminal of the third transistor (330) is connected to the first terminal of the second transistor (320). The third terminal of the third transistor (330) is used to acquire the reference low potential. A fourth transistor (340) is provided, the first terminal of which is used to acquire the nth level control signal, the second terminal of which is connected to the third terminal of the second transistor (320), and the third terminal of which is used to acquire the reference low potential.

6. The gate driving circuit as described in claim 5, characterized in that, The alternation switching module (40) includes: The fifth transistor (410) has a first terminal for acquiring the first local clock signal, a second terminal for connecting to the third terminal of the second transistor (320) for acquiring the nth level inverted signal, and a third terminal for outputting the first nth level switching signal. The sixth transistor (420) has a first terminal for acquiring the second local clock signal, a second terminal for connecting to the third terminal of the second transistor (320) for acquiring the nth level inverted signal, and a third terminal for outputting the second nth level switching signal.

7. The gate driving circuit as described in claim 6, characterized in that, The pull-down sustaining module (50) includes: The seventh transistor (510) has its first terminal connected to the third terminal of the fifth transistor (410) for acquiring the first nth stage switching signal, its second terminal connected to the pull-up control module (10) for acquiring the nth stage control signal, and its third terminal for acquiring the reference low potential. The eighth transistor (520) has its first terminal connected to the third terminal of the fifth transistor (410) for acquiring the first nth stage switching signal. The second terminal of the eighth transistor (520) is connected to the pull-up module (20) for acquiring the nth stage gate drive signal. The third terminal of the eighth transistor (520) is used to acquire the reference low potential.

8. The gate driving circuit as described in claim 6, characterized in that, The pull-down sustaining module (50) includes: The ninth transistor (530) has its first terminal connected to the third terminal of the sixth transistor (420) for acquiring the second nth stage switching signal. The second terminal of the ninth transistor (530) is connected to the pull-up control module (10) for acquiring the nth stage control signal. The third terminal of the ninth transistor (530) is used to acquire the reference low potential. The tenth transistor (540) has its first terminal connected to the third terminal of the sixth transistor (420) for acquiring the second nth stage switching signal. The second terminal of the tenth transistor (540) is connected to the pull-up module (20) for acquiring the nth stage gate drive signal. The third terminal of the tenth transistor (540) is used to acquire the reference low potential.

9. The gate driving circuit as described in claim 3, characterized in that, The first reset module (70) includes: The eleventh transistor (710) has a first terminal for acquiring the reset signal, a second terminal for being connected to the pull-up module (20) for acquiring the nth gate drive signal, and a third terminal for acquiring the reference low potential. The twelfth transistor (720) has a first terminal for acquiring the reset signal, a second terminal for being connected to the pull-up control module (10) for acquiring the nth level control signal, and a third terminal for acquiring the reference low potential.

10. The gate driving circuit as described in claim 4, characterized in that, The second reset module (80) includes: The thirteenth transistor (810) has a first terminal for acquiring the reset signal, a second terminal for being connected to the inverter module (30) for acquiring the nth-stage inverted signal, and a third terminal for acquiring the reference low potential.

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