A charging pile T-type three-level hybrid rectifier system and a control method thereof

Abstract

This invention discloses a T-type three-level hybrid rectification system and control method for charging piles. Addressing the issues of high switching losses in existing all-IGBT solutions and high costs in all-SiC solutions, this invention introduces a heterogeneous hybrid switching unit composed of parallel Si IGBTs and SiC MOSFETs in the vertical bridge arm of the T-type midpoint clamping topology. Through an RC hardware delay drive circuit, the SiC MOSFET is precisely controlled to turn on and off before switching transients, creating a zero-voltage turn-on and zero-current turn-off environment for the Si IGBT, completely eliminating the tail current loss of the IGBT. In the steady-state conduction, the Si IGBT bears the main load current. This invention has been verified by thermal loss modeling on the PLECS power electronics simulation platform, significantly reducing device costs while lowering switching losses by more than 80%, effectively improving the conversion efficiency and power density of the charging pile's rectifier stage.

Description

Technical Field

[0001] This invention belongs to the field of power electronic conversion and new energy vehicle infrastructure technology, specifically relating to a T-type three-level hybrid rectification system and control method for charging piles. More specifically, this invention relates to a T-type three-level topology based on heterogeneous hybrid parallel technology of silicon-based insulated-gate bipolar transistors (Si IGBTs) and silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), and a low-loss, low-cost timing control method adapted thereto. Background Technology

[0002] As the electric vehicle (EV) industry moves towards longer driving range and super-fast charging, charging infrastructure faces the triple challenges of high power density, high efficiency, and low cost. Current DC fast charging stations generally adopt a two-stage architecture of "three-phase AC / DC rectification + DC / DC conversion." The front-stage AC / DC rectifier is responsible for converting the 380V AC grid voltage into a stable DC bus voltage (typically 750V-1000V) and achieving unity power factor correction (PFC).

[0003] In existing rectifier technologies, the T-type three-level (T-NPC) topology has become the mainstream choice due to its combination of low conduction loss and good output waveform quality. However, as charging power increases to 40kW, 60kW, and even higher module levels, the limitations of traditional single-device solutions are gradually becoming apparent.

[0004] Bottlenecks in all-silicon insulated-gate bipolar transistor (Si IGBT) solutions: Si IGBT technology is mature, low-cost, and possesses strong surge current tolerance, making it suitable for handling high currents. However, as a bipolar device, Si IGBT exhibits a severe current tail effect during turn-off, leading to increased turn-off losses. The large size of the input boost inductor and EMI filter severely restricts the system switching frequency, which is typically limited to below 20kHz.

[0005] Challenges of Silicon Carbide (SiC) MOSFETs: While SiC devices offer advantages such as fast switching speeds and no reverse recovery current, significantly reducing switching losses and increasing frequencies above 50kHz, they currently face challenges including high cost (approximately 3-5 times that of Si devices of the same specifications) and weak surge protection (short short-circuit withstand time). Furthermore, SiC MOSFETs are unipolar devices, exhibiting a linear resistive voltage drop characteristic. Under heavy load and high current, its conduction loss increases sharply with temperature, and may even exceed that of IGBT. This represents the load current / drain current, which is the actual operating current flowing through the switching transistor. It represents the on-resistance, which is the equivalent static resistance between the drain and source of a MOSFET after an on-voltage is applied to the gate.

[0006] To balance performance and cost, existing technologies have proposed the concept of hybrid switches. However, current hybrid solutions mostly remain at the theoretical simulation level and have the following shortcomings:

[0007] Low topology matching: The differences in voltage stress and switching characteristics between the vertical and horizontal bridge arms in the T-type three-level topology are not specifically optimized, and often all bridge arms are replaced blindly, resulting in incomplete cost optimization.

[0008] Complex control timing: Existing hybrid drives often rely on controllers (DSP / FPGA) to generate complex multi-channel PWM signals, which places extremely high demands on the computing power and peripheral resources of the controller, and the software dead-time control is easily interfered with, leading to shoot-through risk.

[0009] Lack of engineered delay design: The lack of engineered formulas on how to accurately calculate the turn-on and turn-off delays between hybrid devices results in some hard switching losses in IGBTs in practical applications, or damage to SiC devices due to excessive overload time.

[0010] Therefore, there is an urgent need for an engineered rectification system solution that can combine the advantages of high current and low cost of Si IGBT with the advantages of high frequency and low loss of SiC MOSFET, and achieve the goal of "maximizing strengths and minimizing weaknesses" through reliable hardware circuitry. Summary of the Invention

[0011] The purpose of this invention is to provide a hybrid device T-type three-level rectifier system and its control method for electric vehicle charging piles. This invention aims to solve the problems of low efficiency and large size in existing all-Si solutions, and high cost and high conduction loss under heavy load in all-SiC solutions. Through innovative topology configuration and hardware timing control, a perfect balance between high efficiency, high power density, and low cost of the rectifier is achieved.

[0012] To achieve the above objectives, the present invention adopts the following technical solution: a charging pile T-type three-level hybrid rectification system, the system comprising: a three-phase input inductor, a three-phase T-type three-level rectifier bridge arm, a DC bus capacitor bank, and a main controller; each phase of the three-phase T-type three-level rectifier bridge arm includes a vertical bridge arm and a horizontal bridge arm; one end of the three-phase input inductor serves as an AC input terminal, and the other end is connected to the common connection point of the vertical bridge arm and the horizontal bridge arm of the corresponding phase; the DC bus capacitor bank is connected between the positive and negative terminals of the DC bus, and its voltage divider midpoint is connected to the horizontal bridge arm;

[0013] The vertical bridge arm is configured with a heterogeneous hybrid switching unit consisting of Si IGBT chips and SiC MOSFET chips connected in parallel. This unit is configured with a hardware delay drive circuit, which includes an RC delay network and logic gate circuits connected to the gates of the Si IGBT and SiC MOSFET respectively, for setting a fixed switching timing difference through hardware parameters.

[0014] The main controller outputs a PWM signal based on the load current magnitude, and the hardware delay drive circuit processes the PWM signal to generate Si IGBT and SiC MOSFET drive pulses with specific delays.

[0015] Furthermore, the system also includes a three-phase AC input port and an EMI filter; the three-phase AC input port is connected to the three-phase input inductor via the EMI filter.

[0016] Furthermore, the vertical bridge arm is composed of an upper bridge arm switch and a lower bridge arm switch connected in series, and is connected between the positive and negative terminals of the DC bus; the horizontal bridge arm is composed of two midpoint switches connected in reverse series; the switches of the vertical bridge arm all adopt heterogeneous hybrid switching units, and the gates of the Si IGBT chip and the SiC MOSFET core of the unit are independently led out.

[0017] Furthermore, the vertical bridge arm bears the full bus high voltage and is subjected to high-frequency chopping. The hybrid configuration utilizes SiC to handle the switching process and IGBT to handle the conduction current. The horizontal bridge arm only bears half the bus voltage and achieves freewheeling clamping when operating at unity power factor.

[0018] Furthermore, the hardware delay driving circuit includes:

[0019] First signal channel: directly connected or connected via a buffer to the SiC MOSFET gate driver;

[0020] The second signal channel consists of an RC delay network and a Schmitt trigger connected in series, which is then connected to the Si IGBT gate driver.

[0021] Furthermore, by adjusting the time constant of the RC delay network, the turn-on delay time and turn-off delay time of the Si IGBT relative to the SiC MOSFET are set.

[0022] On the other hand, the present invention also provides a control method for a charging pile T-type three-level hybrid rectifier system, the method comprising the following steps:

[0023] Step S1: Real-time detection of load current ;

[0024] Step S2: With the preset threshold current Comparison: If Upon entering light-load mode, the main controller only sends drive signals to the SiC MOSFETs, blocking the Si IGBT signals; if Upon entering the heavy-load hybrid mode, the main controller outputs a unified PWM control signal to the hardware delay drive circuit.

[0025] Step S3: The hardware delay drive circuit executes the following timing logic:

[0026] Turn-on process: Upon receiving the rising edge of the PWM signal, the SiC MOSFET is immediately turned on; after a turn-on delay... Then, the Si IGBT is turned on;

[0027] Turn-off process: Upon receiving the falling edge of the PWM signal, the Si IGBT is immediately driven to turn off; after a turn-off delay... Then, the SiC MOSFET is turned off.

[0028] Furthermore, the activation delay The turn-on time and voltage fall time of the SiC MOSFET need to be covered; the turn-off delay... The tail current time of the Si IGBT needs to be fully covered.

[0029] Furthermore, upon entering the heavy-load hybrid mode, the control process includes the following timing stages:

[0030] (1) Initial state: The system is in the dead zone or off interval of the PWM cycle, and the gate drive signals of IGBT and SiC MOSFET are both low level;

[0031] (2) SiC first turn-on: When the main controller issues the turn-on command, the hardware delay drive circuit first pulls up the gate signal of the SiC MOSFET;

[0032] (3) IGBT zero-voltage turn-on: After the SiC MOSFET has been turned on for a period of time, the gate drive signal of the IGBT becomes high; the load current flows through the SiC MOSFET channel completely;

[0033] (4) Hybrid conduction: Entering the steady-state conduction stage, both the IGBT and SiC MOSFET are in the conduction state simultaneously;

[0034] (5) Turn-off process: When the main controller issues a turn-off command, the hardware logic circuit first pulls down the gate signal of the IGBT while keeping the SiC MOSFET on. The current in the IGBT is transferred to the SiC MOSFET, so that the collector-emitter voltage of the IGBT is clamped at a low level during the turn-off process, thus achieving soft turn-off.

[0035] (6) SiC final turn-off: After the IGBT is completely turned off and a set delay has elapsed, the gate signal of the SiC MOSFET goes low, cutting off the remaining current.

[0036] Compared with the prior art, the present invention has the following significant advantages:

[0037] 1. Significantly reduced system losses and improved efficiency: PLECS simulation verification shows that, compared with the all-Si IGBT solution (20kHz) limited by thermal bottleneck under the same conditions, the hybrid switching solution of this invention is designed with a turn-off delay that completely covers the tail current time of the Si IGBT, ensuring that the SiC MOSFET remains on before the tail current of the IGBT completely disappears. In addition, the SiC MOSFET provides a low-impedance parallel bypass, and the current in the IGBT is quickly transferred to the SiC MOSFET, so that the collector-emitter voltage of the IGBT is clamped at a low level during the turn-off process, realizing soft turn-off. At a high frequency of 40kHz, the tail current problem of the IGBT is completely solved, reducing the total system loss by about 45% and improving the overall efficiency by about 1.2%.

[0038] 2. Significantly Reduced System Costs: Compared to an all-SiC solution, the current capacity of the auxiliary switch SiC MOSFET (23A) is only about 30% of that of the main switch Si IGBT (75A). This invention only requires SiC devices with approximately 1 / 4 to 1 / 3 of the current capacity to meet the switching transient requirements (the steady-state current is handled by inexpensive IGBTs). While meeting the high-frequency switching transient requirements, it avoids using expensive SiC devices for the entire capacity. Furthermore, the vertical bridge arm bears the full bus high voltage and performs high-frequency chopping. The hybrid configuration utilizes SiC to handle the switching process and IGBTs to handle the conduction current. The horizontal bridge arm retains all Si IGBTs, only bearing half the bus voltage, and mainly acts as a freewheeling clamp during unity power factor operation, exhibiting good soft-switching characteristics. Overall, the power semiconductor BOM cost can be reduced by more than 40%.

[0039] 3. Improved overall efficiency and thermal stability: The hybrid switch combines the low switching losses of SiC with the low conduction losses of IGBT (under high current), enabling the rectifier to maintain extremely high efficiency across the entire load range. Simultaneously, the parallel connection of the two devices distributes heat, reducing the risk of single-point overheating.

[0040] 4. High reliability and ease of implementation: The complex FPGA / DSP software logic is replaced by an RC hardware delay circuit to construct the driving timing of "SiC MOSFET enveloping IGBT". That is, the fast switching characteristics of the wide bandgap device SiC MOSFET are used as the "vanguard" and "rearguard" to carry the current before and after the IGBT operation, so that the IGBT can achieve zero voltage turn-on and zero voltage / zero current turn-off. This avoids the risk of failure caused by dead-time software calculation errors. Moreover, the circuit structure is simple and easy to integrate into existing charging pile control boards.

[0041] The advantages of the hardware logic of the RC hardware delay circuit are: First, the timing accuracy is determined by passive components and is not limited by software interrupt jitter or controller computing power, resulting in more accurate nanosecond-level delays; Second, it has extremely high anti-interference capability. Even under software crash or restart conditions, the hardware logic can still guarantee the safe timing of the "SiC envelope IGBT", avoiding overheating damage to the devices in hard switching state and significantly improving the engineering reliability of the charging pile rectifier module. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0043] Figure 1 This is a schematic diagram of the overall topology of a charging pile T-type three-level hybrid rectifier system proposed in this invention.

[0044] Figure 2 This is a schematic diagram of a hardware delay drive circuit based on RC.

[0045] Figure 3 It is a hybrid switching timing and soft-switching waveform diagram, showing that the SiC gate signal envelops the IGBT gate signal.

[0046] Figure 4 The control strategy flowchart is used to determine the load current magnitude and decide whether to enter hybrid mode or pure SiC mode.

[0047] Figure 5 The waveforms and histograms of switching losses and junction temperature in a PLECS according to an embodiment of the present invention are shown.

[0048] Figure 6 yes Figure 1 Detailed circuit connection diagram of the Hybrid Switch Unit.

[0049] Figure 7 The waveform diagram shows the driving timing and current commutation process of the IGBT and SiC MOSFET hybrid switch implemented based on hardware simulation delay logic in Embodiment 4 of the present invention. Detailed Implementation

[0050] The specific embodiments of the present invention will be described in detail using an example of a 40kW / 800V output electric vehicle charging module. For example... Figure 1 As shown, the T-type three-level (T-NPC) hybrid rectifier system for charging piles proposed in this invention includes a three-phase input and a bridge arm composed of a hybrid switch, as well as a three-phase AC input port and an EMI filter. The three-phase AC input port is connected to the three-phase input inductor via the EMI filter. Each phase of the three-phase T-type three-level rectifier bridge arm includes a vertical bridge arm and a horizontal bridge arm.

[0051] Vertical bridge arm (main switch): Two main switch transistors connecting the positive and negative terminals of the DC bus in each phase. All of them employ a heterogeneous hybrid switch unit (HSU). This unit consists of a high-capacity Si IGBT chip and a low-capacity SiC MOSFET chip connected in parallel (collector connected to drain, emitter connected to source), but their gates are independently led out. The specific design principle is as follows: the vertical bridge arm bears the high voltage of the entire bus and performs high-frequency chopping; the hybrid configuration utilizes SiC to handle the switching process and IGBTs to handle the conduction current.

[0052] Lateral arm (neutral clamp): A bidirectional switch connecting the AC input terminal and the DC neutral point of each phase. The design employs Si IGBT devices. The specific design principle is as follows: the transverse bridge arm only bears half the bus voltage, and mainly functions as a freewheeling clamp during unity power factor operation, exhibiting good soft-switching characteristics. Low-cost Si IGBTs can meet the requirements, eliminating the need for expensive SiC devices.

[0053] Example 1: Hybrid Device Selection and Hardware Circuit Design

[0054] To achieve optimal cost-effectiveness and thermal balance, this embodiment adopts a differentiated device configuration strategy.

[0055] 1. Vertical bridge arm (main hybrid switch): such as Figure 6 The diagram shows a detailed circuit connection of a hybrid switching module, which directly connects Si IGBTs and SiC MOSFETs in parallel.

[0056] Si IGBT (main current-carrying device): Infineon IKQ75N120CH3 is selected. This device is a high-speed 1200V / 75A IGBT with a positive temperature coefficient, suitable for parallel use, but its turn-off tail time can reach [value missing] at 125℃. .

[0057] SiC MOSFET (auxiliary switching device): Wolfspeed C3M0075120K is selected. This device is a 1200V / 23A silicon carbide MOSFET with a conduction resistance of... Its activation and deactivation times are both within 50ns.

[0058] Parallel structure optimization: Connecting Si IGBTs and SiC MOSFETs via a low-inductance stacked busbar ensures that the stray inductance of the commutation circuit between them is minimized. This is to suppress voltage spikes during the current transfer to SiC when the IGBT is turned off.

[0059] 2. Lateral arm (midpoint clamping):

[0060] Si IGBTs will be retained, with Infineon IKW50N65H5 (650V / 50A) selected. Since the neutral point switch only withstands 400V half bus voltage and mainly operates under zero-voltage switching (ZVS) or low hard-switching stress (freewheeling) conditions during unity power factor operation, there is no need to use expensive SiC devices.

[0061] 3. Capacity Ratio and Cost Analysis: In this hybrid switch embodiment, the current capacity of the auxiliary switch SiC MOSFET (23A) is only about 30% of that of the main switch Si IGBT (75A), which conforms to a ratio design of 1 / 4 to 1 / 3. This satisfies the transient requirements of high-frequency switching while avoiding the use of expensive SiC devices for the entire capacity. Combined with the strategy of retaining low-cost Si IGBTs in the lateral bridge arm, comprehensive calculations show that the power semiconductor BOM cost of this embodiment can be reduced by more than 40% compared to a full SiC rectification scheme of the same power level, achieving an optimal balance between cost and performance.

[0062] Example 2: Precise Calculation of RC Hardware Delay Parameters

[0063] This embodiment details how to set precise "SiC envelope" timing using RC circuit parameters. For example... Figure 2The diagram shows a hardware delay drive circuit based on RC, used to connect the PWM output of the main controller to the gate of the hybrid switching unit. Its core consists of a PWM input, an RC delay network, and a Schmitt trigger. The main controller outputs a PWM signal based on the load current. The hardware delay drive circuit processes this PWM signal to generate drive pulses for the Si IGBT and SiC MOSFET with specific delays. This circuit splits one PWM signal into two paths: one path is directly connected to or buffered to the SiC MOSFET gate driver, directly driving the SiC MOSFET; the other path passes through an RC integrator network and a Schmitt trigger before connecting to the Si IGBT gate driver, driving the Si IGBT.

[0064] By adjusting the parameters of the resistor R and capacitor C of the RC delay network, the turn-on delay time and turn-off delay time of the Si IGBT relative to the SiC MOSFET are set. The switching timing of the SiC envelope IGBT is physically locked at the hardware level, eliminating the need for complex software delay calculations by the DSP, which greatly improves the reliability and anti-interference capability of the system.

[0065] The power supply voltage for the drive logic circuit is set to The forward threshold voltage of the selected Schmitt trigger (such as 74LVC1G17) Negative threshold voltage .

[0066] 1. Activate delay ( )calculate:

[0067] Objective: To cover the turn-on time and voltage drop time of SiC MOSFETs, ensuring that the IGBT... Actions during time, among which This refers to the collector-emitter voltage of a silicon-based insulated-gate bipolar transistor (Si IGBT). During the turn-on process in heavy-load hybrid mode, the control strategy prioritizes the turn-on speed of the SiCMOSFET, rapidly pulling the voltage across the hybrid switch down to near zero volts. By driving the IGBT to turn on at the appropriate time, the IGBT can achieve zero-voltage turn-on (ZVS), thereby completely eliminating the IGBT's turn-on loss. Must meet: ,in This refers to the voltage fall time of the SiC MOSFET. Its time constant is set to ensure that the Si IGBT turns on at zero voltage. The target turn-on delay is set. .

[0068] Calculation: According to the formula

[0069]

[0070] in, , To control the turn-on timing, the resistor and capacitor values ​​are selected; capacitor values ​​are... (C0603 package, NP0 material).

[0071] Substitute the values: Solving for: In actual engineering projects, a 1.65kΩ / 1% precision resistor is selected.

[0072] 2. Shutdown delay ( )calculate:

[0073] Objective: To fully cover the tail current time of Si IGBTs. Must meet: ,in This is the tail current decay time of the Si IGBT, to ensure that the SiC MOSFET remains on until the IGBT tail current completely disappears. Referring to the IKQ75N120CH3 datasheet, the tail time at a junction temperature of 150°C is approximately 800ns. Considering a safety margin, the target turn-off delay is set. .

[0074] Calculation: According to the formula

[0075]

[0076] in, , To control the turn-off timing, the values ​​of the resistor and capacitor are selected; .

[0077] Substitute the values: Solving for: In actual engineering projects, a 2.1kΩ / 1% precision resistor is selected.

[0078] Example 3: Thermal Loss Simulation Verification Based on PLECS

[0079] To verify the effectiveness of the hybrid switching scheme in reducing losses, this invention established a detailed thermal domain model in the PLECS Blockset simulation environment.

[0080] 1. PLECS Thermal Modeling:

[0081] Multidimensional lookup tables (LUTs):

[0082] SiC MOSFET model: Import the PLECS XML thermal model file provided by Wolfspeed. Its switching losses... and Defined as relating to blocking voltage , conduction current and junction temperature A three-dimensional function.

[0083] Si IGBT Model (Special Handling): Because IGBTs implement soft switching in hybrid switching, the original manufacturer's hard switching loss data cannot be directly used. The IGBT's... Multiply all values ​​in the data table by 0.05 (simulating ZVS activation, retaining only a small amount of drive loss). Then multiply the IGBT's... Multiply all values ​​in the datasheet by 0.10 (simulating ZCS turn-off, the tail current is bypassed by SiC, retaining only a small amount of initial turn-off losses). The IGBT's on-state voltage drop is retained. ,in For collector current, To keep the junction temperature data constant, the steady-state conduction loss can be accurately calculated.

[0084] 2. Thermal Impedance Network Configuration: In PLECS, a Foster thermal network model (4th-order RC chain) is configured for each device. The parameters are derived from the transient thermal impedance curves in the device datasheet. Configure a unified heat sink module and set its thermal resistance. Ambient temperature .

[0085] 3. Simulation Execution and Result Analysis:

[0086] Operating conditions: AC input 380V, DC output 800V, load current 50A, switching frequency .

[0087] Waveform observation, such as Figure 5 The figure shows the switching loss and junction temperature waveforms and histograms in a PLECS according to an embodiment of the present invention:

[0088] Switching loss pulses: PLECS probes show that the pulses causing the total switching loss of the system are mainly concentrated on the SiC MOSFETs, with a single pulse energy of approximately The switching loss pulse of Si IGBT is almost zero.

[0089] Junction temperature distribution: The simulation reached thermal steady state after 1 second of operation. The junction temperature of the Si IGBT stabilized at 82℃, mainly due to conduction losses; the junction temperature of the SiC MOSFET stabilized at 88℃, mainly due to high-frequency switching losses. The temperature difference between the two was only 6℃, demonstrating that the hybrid switching strategy achieved good thermal stress balance.

[0090] Comparative data: Compared with the all-Si IGBT solution under the same conditions (which can only run at 20kHz due to thermal limitation), the solution of this invention reduces the total loss by 45% and improves the overall efficiency by 1.2% at 40kHz.

[0091] Example 4: Hybrid Device Driving Timing Control Method Based on Pure Hardware Logic

[0092] Based on the system architecture of Embodiments 1 to 3 above, in order to further reduce the computational burden of the controller and prevent the risk of pass-through caused by microprocessor (DSP or MCU) software malfunction, this embodiment uses a hardware analog logic circuit composed of "RC delay network + Schmitt trigger" to generate the timing signal of the hybrid switch.

[0093] like Figure 4 The control strategy flowchart shown illustrates that the system continuously monitors the load current during operation, compares it with a preset threshold, and determines whether to enter pure SiC mode (blocking IGBTs to reduce losses under light load) or hybrid mode (activating timings under heavy load). The specific control method is as follows:

[0094] 1. Load segmentation: Real-time monitoring of load current. When the current is lower than the preset threshold ( When the load is low, the Si IGBT drive is forcibly blocked, and only the SiC MOSFET is used. A drive signal is sent to the SiC MOSFET to improve the low-load efficiency by taking advantage of its tailless and linear on-state voltage drop characteristics.

[0095] 2. Timing envelope (overload mode): When the load current... Higher than the preset threshold When entering mixed mode, the main controller outputs a unified PWM control signal to the hardware delay drive circuit to execute the following logic:

[0096] Zero-Voltage Turn-On (ZVS): Upon receiving the rising edge of the PWM signal, the SiC MOSFET is turned on before the Si IGBT. Utilizing the extremely fast turn-on speed of SiC, the voltage across its terminals is rapidly pulled down to near zero volts, followed by a delay. Afterwards, the Si IGBT turns on under zero voltage conditions, eliminating turn-on losses.

[0097] Zero-current turn-off (ZCS): Upon receiving the falling edge of the PWM signal, the Si IGBT is turned off before the SiC MOSFET. When the Si IGBT turns off, the load current automatically transfers to the bypassed SiC MOSFET. After a delay... (Covering IGBT tailing time), after the IGBT current returns to zero, the SiC MOSFET is quickly turned off. This process completely eliminates the high-voltage tailing loss of the IGBT.

[0098] When entering heavy-load hybrid mode, combined with Figure 7 The diagram shows the timing and current commutation waveforms of the hybrid IGBT and SiCMOSFET switch driven based on hardware-simulated delay logic. Figure 3 The hybrid switching timing and soft-switching waveform diagrams shown illustrate that the core of the control strategy in this embodiment lies in constructing a "SiC MOSFET enveloping IGBT" drive timing sequence. This utilizes the fast switching characteristics of the wide-bandgap SiC MOSFET as both the "vanguard" and "rearguard," carrying current before and after IGBT operation, thereby enabling the IGBT to achieve zero-voltage turn-on (ZVS) and zero-voltage / zero-current turn-off (ZVS / ZCS). The specific control process includes the following six strict timing stages:

[0099] Step 1: Initial State (Full Shutdown Phase) )

[0100] During this stage, the system is in the dead zone or off interval of the PWM cycle, and the gate drive signals of both the IGBT and SiC MOSFET are low. , At this time, the hybrid switching unit is subjected to high voltage across its terminals. The current flowing through it is zero.

[0101] Step 2: SiC initial commissioning (ZVS preparatory stage) )

[0102] When the controller issues an on command, the drive circuit first pulls the gate signal of the SiC MOSFET high. Utilizing the characteristics of the SiC MOSFET—small junction capacitance and fast turn-on speed (nanosecond level)—the voltage across the mixed switch (…) The voltage is rapidly pulled down to near 0V. At this point, the load current flows entirely through the SiC MOSFET channel. This stage creates a zero-voltage condition for the IGBT to turn on.

[0103] Step 3: IGBT Zero Voltage Turn-On (ZVS Operation Phase) )

[0104] After the SiC MOSFET is turned on for a period of time ( After that, the IGBT gate drive signal goes high. This delay... The hardware circuitry is configured to ensure coverage of the SiC's turn-on transient process. At this time, because the SiC MOSFET has clamped its voltage across its terminals to an extremely low on-state voltage drop level, the collector-emitter voltage that the IGBT experiences at the moment of turn-on is... The voltage is approximately zero, thus achieving zero-voltage turn-on (ZVS) of the IGBT and completely eliminating the turn-on loss of the IGBT. ).

[0105] Step 4: Hybrid conduction (loss sharing stage) )

[0106] Upon entering the steady-state conduction phase, both the IGBT and SiC MOSFET are in the on-state. Since this invention is designed for medium-to-high power charging pile applications, the selected IGBT exhibits a lower saturation voltage drop under high current. SiC MOSFETs have a relatively constant on-resistance. According to the principle of parallel current sharing, most of the load current naturally shifts to the IGBT side with lower voltage drop, while only a small amount of current flows through the SiC MOSFET. This stage fully utilizes the advantage of low on-state loss of the IGBT, solving the problem of excessively high conduction loss under high current in the all-SiC solution.

[0107] Step 5: Shutdown process (IGBT soft shutdown stage) )

[0108] When the controller issues a turn-off command, the hardware logic circuit first pulls the IGBT's gate signal low while keeping the SiC MOSFET on. At this time, the IGBT turns off. Because the SiC MOSFET provides a low-impedance parallel bypass, the current in the IGBT quickly transfers to the SiC MOSFET, clamping the collector-emitter voltage at a low level during the IGBT turn-off process. This achieves soft turn-off and significantly reduces the IGBT's turn-off tail loss.

[0109] Step 6: SiC Final Turn-Off (Truncation Stage) )

[0110] After the IGBT is fully turned off and a set delay has elapsed, the gate signal of the SiC MOSFET goes low, cutting off the remaining current. Because SiC devices have no tail current characteristic, their turn-off losses are extremely low, thus completing the low-loss operation throughout the entire hybrid switching cycle.

[0111] Hardware implementation:

[0112] Unlike traditional methods that rely on DSP high-frequency interrupts to generate complex timing sequences, this embodiment designs a highly reliable hardware delay circuit. This circuit consists of an input buffer stage, an RC charging / discharging circuit, and a cascaded Schmidt trigger. The delay logic is as follows: the original PWM signal is directly fed into the SiC drive channel; simultaneously, the original PWM signal passes through a first-stage RC integrator circuit (the specific circuit topology of the RC delay network is implemented), and by adjusting the parameters of resistor R and capacitor C, the rise rate of the capacitor voltage is controlled. When the capacitor voltage reaches the positive threshold voltage of the Schmidt trigger (…),… When the output flips, an IGBT turn-on signal that lags behind the SiC signal is generated. Turn-off timing logic: Through a diode unidirectional conduction network and an RC circuit, an asymmetric delay logic of "fast discharge / slow charge" or "slow discharge / fast charge" is implemented to ensure that the IGBT turn-off edge occurs before the SiC MOSFET.

[0113] The advantages of using this hardware logic are: First, the timing accuracy is determined by passive components and is not limited by software interrupt jitter or controller computing power, resulting in more accurate nanosecond-level delays; Second, it has extremely high anti-interference capabilities. Even under software crash or restart conditions, the hardware logic can still guarantee the safe timing of the "SiC envelope IGBT", avoiding overheating damage to the devices in hard switching states and significantly improving the engineering reliability of the charging pile rectifier module.

[0114] The above embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A T-type three-level hybrid rectifier system for a charging pile, characterized in that, The system includes: a three-phase input inductor, a three-phase T-type three-level rectifier bridge arm, a DC bus capacitor bank, and a main controller; each phase of the three-phase T-type three-level rectifier bridge arm includes a vertical bridge arm and a horizontal bridge arm; one end of the three-phase input inductor serves as the AC input terminal, and the other end is connected to the common connection point of the vertical bridge arm and the horizontal bridge arm of the corresponding phase; the DC bus capacitor bank is connected between the positive and negative terminals of the DC bus, and its voltage divider midpoint is connected to the horizontal bridge arm; The vertical bridge arm is configured with a heterogeneous hybrid switching unit consisting of Si IGBT chips and SiC MOSFET chips connected in parallel. This unit is configured with a hardware delay drive circuit, which includes an RC delay network and logic gate circuits connected to the gates of the Si IGBT and SiC MOSFET respectively, for setting a fixed switching timing difference through hardware parameters. The main controller outputs a PWM signal based on the load current magnitude, and the hardware delay drive circuit processes the PWM signal to generate Si IGBT and SiC MOSFET drive pulses with specific delays.

2. The rectifier system according to claim 1, characterized in that, The system also includes a three-phase AC input port and an EMI filter; the three-phase AC input port is connected to the three-phase input inductor via the EMI filter.

3. The rectifier system according to claim 1, characterized in that, The vertical bridge arm consists of an upper bridge arm switch and a lower bridge arm switch connected in series, and is connected between the positive and negative terminals of the DC bus; the horizontal bridge arm consists of two midpoint switches connected in reverse series; the switches of the vertical bridge arm all adopt heterogeneous hybrid switching units, and the gates of the Si IGBT chip and the SiC MOSFET core of the unit are independently led out.

4. The rectifier system according to claim 1, characterized in that, The vertical bridge arm bears the full bus high voltage and is chopped at high frequency. The hybrid configuration uses SiC to handle the switching process and IGBT to handle the conduction current. The horizontal bridge arm only bears half the bus voltage and achieves freewheeling clamping when operating at unity power factor.

5. The rectifier system according to claim 1, characterized in that, The hardware delay driving circuit includes: First signal channel: directly connected or connected via a buffer to the SiC MOSFET gate driver; The second signal channel consists of an RC delay network and a Schmitt trigger connected in series, which is then connected to the Si IGBT gate driver.

6. The rectifier system according to claim 1, characterized in that, By adjusting the time constant of the RC delay network, the turn-on delay time and turn-off delay time of the Si IGBT relative to the SiC MOSFET are set.

7. A control method for a charging pile T-type three-level hybrid rectifier system according to any one of claims 1-6, characterized in that, The method includes the following steps: Step S1: Real-time detection of load current ; Step S2: With the preset threshold current Comparison: If Upon entering light-load mode, the main controller only sends drive signals to the SiC MOSFETs, blocking the Si IGBT signals; if Upon entering the heavy-load hybrid mode, the main controller outputs a unified PWM control signal to the hardware delay drive circuit. Step S3: The hardware delay drive circuit executes the following timing logic: Turn-on process: Upon receiving the rising edge of the PWM signal, the SiC MOSFET is immediately turned on; after a turn-on delay... Then, the Si IGBT is turned on; Turn-off process: Upon receiving the falling edge of the PWM signal, the Si IGBT is immediately driven to turn off; after a turn-off delay... Then, the SiC MOSFET is turned off.

8. The control method according to claim 7, characterized in that, The activation delay The turn-on time and voltage fall time of the SiC MOSFET need to be covered; the turn-off delay... The tail current time of the Si IGBT needs to be fully covered.

9. The control method according to claim 7, characterized in that, After entering the heavy-load hybrid mode, the control process includes the following timing stages: (1) Initial state: The system is in the dead zone or off interval of the PWM cycle, and the gate drive signals of IGBT and SiC MOSFET are both low level; (2) SiC first turn-on: When the main controller issues the turn-on command, the hardware delay drive circuit first pulls up the gate signal of the SiC MOSFET; (3) IGBT zero-voltage turn-on: After the SiC MOSFET has been turned on for a period of time, the gate drive signal of the IGBT becomes high; the load current flows through the SiC MOSFET channel completely; (4) Hybrid conduction: Entering the steady-state conduction stage, both the IGBT and SiC MOSFET are in the conduction state simultaneously; (5) Turn-off process: When the main controller issues a turn-off command, the hardware logic circuit first pulls down the gate signal of the IGBT while keeping the SiC MOSFET on. The current in the IGBT is transferred to the SiC MOSFET, so that the collector-emitter voltage of the IGBT is clamped at a low level during the turn-off process, thus achieving soft turn-off. (6) SiC final turn-off: After the IGBT is completely turned off and a set delay has elapsed, the gate signal of the SiC MOSFET goes low, cutting off the remaining current.

Images