A system on chip and related system power-up recovery method

Abstract

The embodiment of the application discloses a system on chip and a related power-on recovery method, and the system on chip comprises N processing units, and a target processing unit in the N processing units comprises a plurality of first memories, wherein the target processing unit is used for storing target repair information in an internal target storage area, the target repair information is information of a first memory which is faulty in the plurality of first memories; after the target processing unit is switched from a first mode to a second mode, the target repair information is read from the target storage area, and bad point repair is performed on the plurality of first memories; wherein in the first mode, parts or all components of the target processing unit except the target storage area are in a power-off state, and the target storage area is in a power-on state; in the second mode, the target processing unit as a whole is in a power-on state. The embodiment of the application can shorten the recovery time after the processing unit is powered on.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a power-on recovery method for a system-on-a-chip and related systems. Background Technology

[0002] A System-on-a-Chip (SOC) is a technology that integrates a complete system onto a single chip, grouping all or part of the necessary electronic circuitry. This means that a single chip can integrate multiple processing units such as a central processing unit, modem processing unit, image signal processing unit, video codec unit, and digital signal processing unit, as well as memory modules, power supply modules, etc. With the widespread application of SOCs, to reduce power consumption, each processing unit on the SOC can be powered down in an idle state and powered on again when needed, avoiding the problem of processing units consuming a large amount of power even when idle. However, after a processing unit is powered on again, a power-on recovery process is required (e.g., repairing bad pixels in the internal memory after power-on) before it can start working normally. In applications such as high frame rate games, virtual reality (VR) technology, or new wearable devices, a longer power-on recovery time for the processing units limits the scenarios where they can be used while idle, affecting the user experience.

[0003] Therefore, how to provide an on-chip system and related power-on recovery method to shorten the recovery time of the processing unit after power-on is an urgent problem to be solved. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of this application is to provide a power-on recovery method for a system-on-chip and related systems, so as to shorten the recovery time after the system is powered on.

[0005] In a first aspect, this application provides a system-on-a-chip (SoC), characterized in that the SoC includes N processing units, and a target processing unit among the N processing units includes a plurality of first memories, all of which are volatile memories. The target processing unit is any one of the N processing units, where N and M are integers greater than 0. The target processing unit is used to: store target repair information in an internal target storage area, the target repair information being information about a faulty first memory among the plurality of first memories; when the target processing unit switches from a first mode to a second mode, it reads the target repair information from the target storage area and performs bad pixel repair on the plurality of first memories; wherein, in the first mode, some or all components of the target processing unit, except for the target storage area, are in a power-off state, and the target storage area is in a power-on state; in the second mode, the entire target processing unit is in a power-on state.

[0006] In this embodiment of the invention, a target storage area is added or allocated within each processing unit of the system-on-a-chip (SoC) specifically for storing the target repair information of each processing unit. This target storage area is configured to remain powered on even when the processing unit is powered down. This allows each processing unit to directly repair memory faults based on its internal target repair information upon power-on, without needing to retrieve the corresponding target repair information from outside the processing unit, significantly shortening the memory fault repair time after power-on. Specifically, a target storage area is added or allocated within the processing unit specifically for storing the processing unit's own target repair information (i.e., information related to the first memory that has failed within the processing unit). This target storage area remains powered on even when the processing unit is powered down (e.g., a separate power supply is provided for the target storage area), ensuring that the target repair information stored in the target storage area is not lost when the processing unit is powered down. Furthermore, when the processing unit is powered off and then powered on again, since the target storage area remains powered on (i.e., the target repair information stored in the target storage area is not lost), the processing unit can directly obtain its own target repair information from the internal, powered-on target storage area without needing to obtain the corresponding target repair information from the external storage module. In the prior art, after each power-off, the processing unit does not store the target repair information. Therefore, when the processing unit is powered on again, it needs to obtain its own target repair information from the external storage module, resulting in excessively long memory fault repair time after power-on. In summary, in this embodiment of the invention, when the processing unit is powered on again, it can directly perform bad pixel repair on the first memory based on the internally stored target repair information without needing to obtain the target repair information from the external storage module. This reduces the time the processing unit spends repairing memory faults, allowing it to resume normal operation more quickly and shortening the system power-on recovery time.

[0007] In one possible implementation, the system-on-chip further includes a second memory, which is a non-volatile memory; the second memory is used to store the target repair information of each of the N processing units.

[0008] In this embodiment of the invention, before the on-chip system is first powered on, hardware testing can be performed on each processing unit to obtain target repair information for each processing unit. This target repair information can then be stored in a second memory. Since this second memory is non-volatile (i.e., data is not lost after power-off), the target repair information for each processing unit will not be lost when the second memory is powered off. Furthermore, when a processing unit is powered on, if there is no target repair information in the target storage area inside the processing unit, it can obtain its own target repair information from the second memory outside the processing unit. The processing unit can then perform memory fault repair based on this target repair information. Simultaneously, the target repair information can be stored in the target storage area so that when the processing unit is powered on again, it can directly perform memory fault repair based on the internally stored target repair information without needing to obtain the target repair information from outside the processing unit. This reduces the time spent by the processing unit on memory fault repair, allowing the processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0009] In one possible implementation, the system-on-chip further includes a third memory, which is a volatile memory; when the system-on-chip switches from a power-down state to a power-on state, the third memory is also used to: read the target repair information of the target processing unit from the second memory and store it.

[0010] In this embodiment of the invention, the third memory can be static random access memory (SRAM), i.e., volatile memory. When the on-chip system switches from a power-down state to a power-on state, the third memory can be used to read and store the target repair information of each processing unit from the second memory. This allows the processing unit to obtain its own target repair information from the external third memory when there is no target repair information in the target storage area inside the processing unit. Since the speed at which the processing unit accesses non-volatile memory is much slower than the speed at which it accesses volatile memory, loading the data in the non-volatile memory into the volatile memory first, and then having the processing unit read the target data from the volatile memory, can reduce the time it takes for the processing unit to read data from the outside.

[0011] In one possible implementation, the target processing unit is further configured to: if the target repair information is not present in the target storage area, obtain the target repair information of the target processing unit from the third memory and store it in the internal target storage area.

[0012] In this embodiment of the invention, if target repair information is not present in the target storage area of ​​the target processing unit, the target processing unit needs to obtain its own target repair information from the outside. That is, it can obtain its own target repair information from a third memory outside the target processing unit. Then, the target processing unit can perform memory bad point repair based on the target repair information. At the same time, it can also store the target repair information in the target storage area so that when the target processing unit is powered on again, the target processing unit can directly perform memory bad point repair based on the internally stored target repair information without having to obtain the target repair information from the outside of the target processing unit again. This reduces the time for the target processing unit to perform memory bad point repair, thereby enabling the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0013] In one possible implementation, the target processing unit further includes a first register; the target processing unit is specifically used to: store the target repair information in the first register as the target storage area.

[0014] In this embodiment of the invention, a first register is added internally to the target processing unit as a target storage area, specifically for storing target repair information of the target processing unit. This first register remains powered on even when the target processing unit is in an idle, power-off state, ensuring that the target repair information stored in the first register is not lost during this period. Therefore, when the target processing unit is powered on again, it can directly perform bad pixel repair on the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit. This reduces the time spent on memory bad pixel repair, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0015] In one possible implementation, the first register is powered by a dedicated power domain such that when some or all components of the target processing unit other than the first register are powered down, the first register is powered on; or the first register is powered by a normally open power domain of the target processing unit such that when some components of the target processing unit other than the first register are powered down, the first register is powered on.

[0016] In this embodiment of the invention, some or all components of the target processing unit, except for the first register, can be powered on and off by a first power domain, while the first register in the target processing unit can be powered on and off by other power domains. When the target processing unit is in an idle state, the first power domain can be disconnected to power off the target processing unit to save power, but the first register remains powered on to ensure that the stored target repair information is not lost. Furthermore, when the target processing unit is powered on again, it can directly perform bad pixel repair on the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit. This reduces the time for the target processing unit to perform bad pixel repair on the memory, thereby enabling the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0017] In one possible implementation, the target processing unit further includes a decoding module, and the target processing unit is further configured to: obtain the target repair information from the first register through the decoding module, and perform decoding configuration on the plurality of first memories based on the target repair information.

[0018] In this embodiment of the invention, when the target processing unit is powered on again, the target processing unit can directly configure multiple first memories in the target processing unit through the decoding module based on the target repair information stored in the first register, so as to avoid the target processing unit using the faulty first memory. Since the target processing unit does not need to obtain the target repair information from outside the target processing unit after power-on, the time for the target processing unit to repair bad points in the memory is reduced, so the target processing unit can resume normal operation more quickly and shorten the system power-on recovery time.

[0019] In one possible implementation, the target processing unit is specifically used to: store the target repair information in the plurality of first memories as the target storage area, wherein the plurality of first memories are powered by the normally open power domain of the target processing unit so that when some components in the target processing unit other than the plurality of first memories are in a power-off state, the plurality of first memories are in a power-on state.

[0020] In this embodiment of the invention, a target storage area is allocated among multiple first memories within the target processing unit, specifically for storing target repair information of the target processing unit. This storage area remains powered on even when the target processing unit is in an idle, power-off state, ensuring that the target repair information stored in the storage area is not lost during this period. Therefore, when the target processing unit is powered on again, it can directly perform bad pixel repair on the first memories based on the target repair information stored in the multiple first memories, without needing to retrieve the target repair information from outside the target processing unit. This reduces the time spent on memory bad pixel repair, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0021] In one possible implementation, the target processing unit includes a second register, and the target processing unit is further configured to: when the target processing unit switches from the first mode to the second mode, retrieve the target repair information from the plurality of first memories through the second register and store it.

[0022] In this embodiment of the invention, to facilitate subsequent decoding of the target repair information, a second register can be added to the target processing unit, and the second register is also powered off when the target processing unit is powered off. When the target processing unit is powered on again, the second register can retrieve the target repair information from the first memory and store it.

[0023] In one possible implementation, the target processing unit further includes a decoding module, and the target processing unit is further configured to: obtain the target repair information from the second register through the decoding module, and perform decoding configuration on the plurality of first memories based on the target repair information.

[0024] In this embodiment of the invention, when the target processing unit is powered on again, the target processing unit can configure multiple first memories in the target processing unit through a decoding module based on the target repair information in the second register, so as to avoid the target processing unit using the faulty first memory. Since the target processing unit does not need to obtain target repair information from outside the target processing unit after power-on, the time for the target processing unit to repair bad points in the memory is reduced, thereby enabling the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0025] In one possible implementation, the target processing unit further includes a backup memory; the target processing unit is specifically used to: determine the faulty first memory through the decoding module based on the target repair information; isolate bad pixels in the faulty first memory; and enable the backup memory.

[0026] In this embodiment of the invention, when the target processing unit is powered on again, the target processing unit can directly determine the faulty first memory among multiple first memories based on the target repair information stored in the target storage area through the decoding module, isolate the faulty first memory for bad points, and then activate the backup memory to avoid the target processing unit using the faulty first memory, which could lead to system abnormalities. Simultaneously, since the target processing unit does not need to obtain target repair information from outside the target processing unit after power-on, the time spent on memory bad point repair is reduced, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0027] Secondly, this application provides a system power-on recovery method, characterized in that it is applied to a system-on-a-chip (SoC), the SoC including N processing units, a target processing unit among the N processing units including a plurality of first memories, the plurality of first memories being volatile memories, the target processing unit being any one of the N processing units, where N and M are integers greater than 0, the method including: storing target repair information in an internal target storage area by the target processing unit, the target repair information being information of a faulty first memory among the plurality of first memories; when the target processing unit switches from a first mode to a second mode, reading the target repair information from the target storage area by the target processing unit, and performing bad pixel repair on the plurality of first memories; wherein, in the first mode, some or all components of the target processing unit except the target storage area are in a power-off state, and the target storage area is in a power-on state; in the second mode, the target processing unit as a whole is in a power-on state.

[0028] In one possible implementation, the on-chip system further includes a second memory, which is a non-volatile memory; the method further includes storing the target repair information of each of the N processing units in the second memory.

[0029] In one possible implementation, the system-on-chip further includes a third memory, which is a volatile memory; when the system-on-chip switches from a power-down state to a power-on state, the method further includes: reading the target repair information of the target processing unit from the second memory through the third memory and storing it.

[0030] In one possible implementation, the method further includes: if the target repair information is not present in the target storage area, then the target processing unit obtains the target repair information from the third memory and stores it in the internal target storage area.

[0031] In one possible implementation, the target processing unit further includes a first register; storing target repair information in an internal target storage area through the target processing unit includes: storing the target repair information in the first register as the target storage area.

[0032] In one possible implementation, the first register is powered by a dedicated power domain such that when some or all components of the target processing unit other than the first register are powered down, the first register is powered on; or the first register is powered by a normally open power domain of the target processing unit such that when some components of the target processing unit other than the first register are powered down, the first register is powered on.

[0033] In one possible implementation, the target processing unit further includes a decoding module, and the method further includes: obtaining the target repair information from the first register through the decoding module in the target processing unit, and performing decoding configuration on the plurality of first memories based on the target repair information.

[0034] In one possible implementation, storing target repair information in the target storage area within the target processing unit includes: storing the target repair information in the plurality of first memories as the target storage area, wherein the plurality of first memories are powered by the normally open power domain of the target processing unit so that when some components in the target processing unit other than the plurality of first memories are in a power-off state, the plurality of first memories are in a power-on state.

[0035] In one possible implementation, the target processing unit includes a second register, and the method further includes: when the target processing unit switches from the first mode to the second mode, obtaining the target repair information from the plurality of first memories through the second register and storing it.

[0036] In one possible implementation, the target processing unit further includes a decoding module, and the method further includes: obtaining the target repair information from the second register through the decoding module in the target processing unit, and performing decoding configuration on the plurality of first memories based on the target repair information.

[0037] In one possible implementation, the target processing unit further includes a backup memory; the bad pixel repair of the plurality of first memories includes: determining the faulty first memory through the decoding module based on the target repair information; isolating the faulty first memory for bad pixels and enabling the backup memory.

[0038] Thirdly, this application provides a computer storage medium, characterized in that the computer storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of the second aspects above.

[0039] Fourthly, embodiments of this application provide an electronic device including a processor configured to support the electronic device in implementing the corresponding functions of the system power-on recovery method provided in the second aspect. The electronic device may further include a memory coupled to the processor, which stores necessary program instructions and data of the electronic device. The electronic device may also include a communication interface for communicating with other devices or communication networks.

[0040] Fifthly, this application provides a chip system including a processor for supporting an electronic device in implementing the functions involved in the second aspect above, such as generating or processing information involved in the power-on recovery method described above. In one possible design, the chip system further includes a memory for storing necessary program instructions and data of the electronic device. This chip system may be composed of chips or may include chips and other discrete devices.

[0041] Sixthly, this application provides a computer program, characterized in that the computer program includes instructions that, when executed by a computer, cause the computer to perform the method described in any one of the third aspects above. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a system-on-a-chip provided in an embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram of a system-on-a-chip provided in an embodiment of the present invention.

[0044] Figure 3 This is a schematic diagram of a system-on-a-chip with a second memory provided in an embodiment of the present invention.

[0045] Figure 4 This is a schematic diagram of a system-on-a-chip with a third memory provided for an embodiment of the present invention.

[0046] Figure 5This is a schematic diagram of the internal structure of a processing unit provided in an embodiment of the present invention.

[0047] Figure 6 This is a schematic diagram of the internal structure of a target processing unit provided in an embodiment of the present invention.

[0048] Figure 7 This is a schematic diagram of the internal structure of another target processing unit provided in an embodiment of the present invention.

[0049] Figure 8 This is a schematic diagram of a target processing unit power-on recovery provided in an embodiment of the present invention.

[0050] Figure 9 This is a schematic diagram of power-on recovery of another target processing unit provided in an embodiment of the present invention.

[0051] Figure 10 This is a schematic diagram of the internal structure of another target processing unit provided in an embodiment of the present invention.

[0052] Figure 11 This is a schematic diagram of another target processing unit power-on recovery provided in an embodiment of the present invention.

[0053] Figure 12 This is a schematic diagram of a system power-on recovery process provided in an embodiment of the present invention.

[0054] Figure 13 This is a flowchart of a system power-on recovery method provided in an embodiment of the present invention. Detailed Implementation

[0055] The embodiments of this application will now be described with reference to the accompanying drawings.

[0056] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0057] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0058] Based on the above, embodiments of the present invention provide a system-on-a-chip. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of a system-on-a-chip (SoC) according to an embodiment of the present invention. A SoC refers to a technology that integrates a complete system onto a single chip, grouping all or part of the necessary electronic circuits. The SoC 10 generally includes a processor 100, an on-chip storage module 101, a built-in self-healing module 102, and peripheral component circuits, etc., and the SoC 10 can be built into various electronic devices, such as servers, personal computers, tablet computers, mobile phones, personal digital assistants, smart wearable devices, and other similar devices. Specifically,

[0059] The processor 100 can run an operating system, file system, or application programs to control multiple hardware or software components connected to it, and can process various data and perform operations. The processor 100 may include one or more processing units (also called processing cores), such as a Central Processing Unit (CPU), a modem processing unit, a graphics processing unit (GPU), an image signal processor (ISP), a video encoding / decoding unit, a digital signal processor (DSP), a baseband processing unit, and a neural network processing unit (NPU). Different processing units can be independent devices or integrated into one or more devices. Each processing unit (such as a CPU) in the processor 100 can load instructions or data stored in the on-chip storage module 101 into its internal memory, and retrieve the instructions or data to be processed by the computing unit. After the processing is completed, the computing unit temporarily stores the results in its internal memory and stores instructions or data that need to be stored long-term in the on-chip storage module 101. Furthermore, if the on-chip storage module 101 stores repair information for the memory of each of the multiple processing units, then each processing unit (such as the CPU) in the processor 100 can load the repair information stored in the on-chip storage module 101 into its internal processing unit and perform bad memory repair. Optionally, the repair information for one or more memories stored in the on-chip storage module 101 is unchangeable and indelible.

[0060] It should be noted that the memory inside each processing unit (such as the CPU) is typically volatile memory, meaning its contents are lost when power is off. The memory inside each processing unit can be used to temporarily store computational data from the processing unit (such as the CPU), as well as data exchanged with the on-chip storage module 101 or other external memory. It can serve as a storage medium for temporary data of the operating system or other running programs. For example, the operating system running on the CPU retrieves the data to be processed from the internal memory to the computing unit for computation. After the computation is completed, the computing unit sends the result back and temporarily stores it in the internal memory. The memory inside the processing unit may include Static Random Access Memory (SRAM), which can be further divided into single-port SRAM and dual-port SRAM.

[0061] The on-chip storage module 101 is a non-volatile memory that retains its contents even after power is lost. The on-chip storage module 101 can be used for long-term storage of instructions and data involved in the operation of the processor 100, such as repair information, boot programs, operating systems, applications, and data stored in the internal memory of each processing unit (e.g., the CPU) involved in this application. Since the processing units in the processor 100 cannot directly read instructions and data from the on-chip storage module 101, nor can they directly write instructions or data to the on-chip storage module 101, when a processing unit (e.g., the CPU) executes a read (or load) command, it actually temporarily loads the contents to be read (including instructions and / or data) stored in the on-chip storage module 101 into its internal memory, and then the CPU reads it from the internal memory. Conversely, when executing a write (i.e., store) command, the CPU actually temporarily writes the data to be stored (including instructions and / or data) into its internal memory, and then stores it from the internal memory into the on-chip storage module 101. The on-chip storage module 101 may include one or more of the following: Flash memory (e.g., NAND flash memory, NOR flash memory, etc.), universal flash storage (UFS), embedded multimedia card eMMC, universal flash storage multi-chip package (uMCP) memory, embedded multimedia card multi-chip package (eMCP) memory, solid-state drive (SSD), etc. The on-chip storage module 101 may also include a one-time programmable memory (eFuse), which can be specifically used to store repair information of the memory of each processing unit in the processor 100, so that the stored repair information of one or more memories is neither altered nor erased.

[0062] The built-in self-repair module 102, located outside the processor 100, may include static random access memory (SRAM). It can read and store repair information from the on-chip storage module 101 of the memory within each processing unit (such as the CPU), so that each processing unit can directly retrieve its internal memory repair information from the built-in self-repair module 102 upon power-up. Since unavoidable failures may occur in the memory within each processing unit during manufacturing, a backup memory can be designed during production to maintain normal operation when a memory fails. Before the first use of the system-on-a-chip 10, the hardware needs to be tested. If a memory failure is found during hardware testing, the failed memory can be marked to obtain repair information, which can then be stored in the on-chip storage module 101 (this information will not be lost after the SOC is powered off). After each processing unit powers on, it needs to repair bad sectors in its memory before it can resume normal operation (e.g., CPU). This requires each processing unit to first obtain repair information from its internal memory. Based on this information, it can isolate faulty memory and associate it with spare memory. Since processing units (e.g., CPUs) cannot directly read data from the on-chip storage module 101 after power-on, and to avoid loading data into faulty memory before obtaining repair information, processing units will not directly use their internal memory. Therefore, a built-in self-repair module 102 can first read and store the repair information of all processing units' internal memory from the on-chip storage module 101. This allows each processing unit to directly obtain its own memory repair information from the built-in self-repair module 102 after power-on, and then perform bad sector repair based on this information. In this embodiment of the invention, a storage module can be added or partitioned in the processing unit. This storage module is used to store the repair information of the internal memory. The repair information is not lost after the processing unit is powered off (i.e., the repair information is still stored inside the processing unit after the processing unit is powered off). Therefore, when the processing unit is powered on again, the processing unit can directly repair the bad points of the memory based on the stored repair information without having to obtain the repair information from outside the processing unit. This reduces the time for the processing unit to repair memory faults, thereby enabling the processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0063] Understandable Figure 1 The structure of the system-on-chip 10 in the present invention is only some exemplary implementations provided by the embodiments of the present invention. The structure of the system-on-chip 10 in the embodiments of the present invention includes, but is not limited to, the above implementation methods.

[0064] The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0065] Please see Figure 2 , Figure 2 This is a schematic diagram of a system-on-a-chip provided in an embodiment of the present invention. The following will refer to the accompanying drawings. Figure 2 The on-chip system in the embodiments of this application will be described in detail. For example... Figure 2 As shown, the system-on-a-chip 20 includes N processing units 201. A target processing unit among the N processing units includes multiple first memories, all of which are volatile memories. The target processing unit is any one of the N processing units, where N is an integer greater than 0. It should be noted that... Figure 2 The on-chip system 20 in the middle may include the above-mentioned Figure 1 The system-on-chip 10 may include some or all of the functions described above, and the N processing units 201 may include the above. Figure 1 The processor 100 contains all or part of the processing unit's functions.

[0066] The target processing unit is used to store target repair information in an internal target storage area. This target repair information is the information of the first memory that has failed among the plurality of first memories. Specifically, the system-on-chip 20 may include one or more processing units, such as a central processing unit (CPU), a modem processing unit, a graphics processing unit (GPU), an image signal processing unit (ISP), a video encoding / decoding unit, a digital signal processing unit (DSP), a baseband processing unit, and a neural network processing unit (NPU). Each processing unit may contain multiple first memories, and the number of first memories within each processing unit may be the same or different, without limitation. The first memories are typically volatile memory, losing their stored contents when power is lost. The function of the first memories is to temporarily store computational data (such as the computation results of the CPU's computing units) and data exchanged with on-chip storage modules or other external memories. They can serve as a storage medium for temporary data of the operating system or other running programs. Since the first memory within each processing unit may inevitably fail during the manufacturing process, the hardware needs to be tested before the system-on-chip 20 is first powered on. If a failure is found in a first memory during hardware testing, the faulty first memory can be marked to obtain target repair information. In this embodiment of the invention, a target storage area can be added or partitioned inside the target processing unit (such as a CPU) specifically for storing the target repair information of the target processing unit. The target repair information will not be lost after the target processing unit is powered off; that is, the target repair information remains stored inside the target processing unit after power-off.

[0067] The target processing unit is further configured to: when the target processing unit switches from the first mode to the second mode, read the target repair information from the target storage area and perform bad pixel repair on the plurality of first memories; wherein, in the first mode, some or all components of the target processing unit except the target storage area are in a power-off state, and the target storage area is in a power-on state; in the second mode, the target processing unit as a whole is in a power-on state. Specifically, the first mode of the target processing unit can be understood as the target processing unit being in an idle power-off state, but the target storage area inside the target processing unit is not powered off, such as the computing units and other components in the target processing unit being in a power-off state, but the target storage area is still in a power-on state, or the computing units and other components in the target processing unit being in a power-off state, but the target storage area and some devices (such as clock units) are still in a power-on state, so that the target repair information stored in the target storage area is not lost when the target processing unit is idle power-off; the second mode of the target processing unit can be understood as the target processing unit being in a working power-on state, that is, the computing units and other components in the target processing unit are all in a power-on state. Switching from the first mode to the second mode of the target processing unit can be understood as the target processing unit switching from an idle, power-off state to a working, power-on state. Since each processing unit needs to repair bad points in the first memory after switching from the first mode to the second mode before the processing unit (such as the CPU) can resume normal operation, each processing unit needs to first identify the faulty first memory after power-on before it can begin normal operation. This is to avoid storing the calculation results in the faulty first memory, which could cause the processing unit to malfunction. In this embodiment of the invention, a target storage area is added or partitioned inside the target processing unit specifically for storing the target repair information of the target processing unit. This target storage area remains powered on even when the target processing unit is in an idle, power-off state, ensuring that the target repair information stored in the target storage area is not lost when the target processing unit is idle and power-off. Therefore, when the target processing unit is powered on again, it can directly repair the bad points of the first memory based on the target repair information stored internally, without having to obtain the target repair information from outside the target processing unit. This reduces the time the target processing unit spends repairing bad points in the memory, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0068] In one possible implementation, the system-on-chip 20 further includes a second memory, which is a non-volatile memory. The second memory is used to store the target repair information for each of the N processing units. Specifically, before the system-on-chip 20 is first powered on, each processing unit can be hardware-tested to obtain its target repair information. This target repair information can then be stored in the second memory. Since the second memory is non-volatile (i.e., data is not lost after power-off), the target repair information for each processing unit will not be lost when the second memory is powered off. Optionally, the target repair information stored in one or more memories in the second memory is immutable and ineradicable. Furthermore, when the processing unit is powered on, if the target repair information is not stored in the target storage area inside the processing unit, it can obtain its own target repair information from the second memory outside the processing unit. Then, the processing unit can perform memory bad point repair based on the target repair information. At the same time, it can also store the target repair information in the target storage area so that when the processing unit is powered on again, it can directly perform memory bad point repair based on the internally stored target repair information without having to obtain the target repair information from outside the processing unit again. This reduces the time for the processing unit to perform memory fault repair, thereby enabling the processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0069] For example, such as Figure 3 As shown, Figure 3 This is a schematic diagram of a system-on-a-chip (SoC) with a second memory provided in an embodiment of the present invention. The on-chip storage module 202 of the SoC 20 in the diagram is the second memory mentioned in this embodiment (which may have the above-described...). Figure 1 The on-chip storage module 101 (which may contain some or all of the functions of the on-chip memory) can be a one-time programmable memory (eFuse). The processor 200 of the system-on-chip 20 may include a CPU and a GPU. Figure 3(Taking two processing units as an example), the target processing unit can be a CPU or a GPU; the CPU may include one or more first memories, and the GPU may also include one or more first memories; the on-chip storage module 202 stores the target repair information of the CPU and the target repair information of the GPU. When the CPU powers on, if the target repair information of the CPU is not stored in the target storage area inside the CPU, the CPU can obtain its own target repair information from the on-chip storage module 202 outside the CPU, and perform memory bad point repair based on the target repair information. At the same time, it can also store the target repair information in the target storage area inside the CPU, so that when the CPU powers on again, the CPU can directly perform memory bad point repair based on the internally stored target repair information, without having to obtain the target repair information from outside the CPU again, reducing the time for the CPU to perform memory bad point repair, thereby enabling the CPU to resume normal operation more quickly and shortening the system power-on recovery time.

[0070] In one possible implementation, the system-on-chip 20 further includes a third memory, which is a volatile memory. When the system-on-chip switches from a power-down state to a power-on state, the third memory is used to read and store the target repair information of the target processing unit from the second memory. Specifically, the third memory can be static random access memory (SRAM), i.e., volatile memory. When the system-on-chip 20 switches from a power-down state to a power-on state, the third memory can be used to read and store the target repair information of each processing unit from the second memory, so that when the target repair information is not stored in the target storage area inside the processing unit, the processing unit can obtain its own target repair information from the external third memory. Since the speed at which the processing unit accesses non-volatile memory is much slower than the speed at which it accesses volatile memory, loading the data in the non-volatile memory into the volatile memory first, and then having the processing unit read the target data from the volatile memory, can reduce the time it takes for the processing unit to read data from the outside.

[0071] For example, such as Figure 4 As shown, Figure 4 This is a schematic diagram of a system-on-a-chip (SoC) with a third memory provided in an embodiment of the present invention. The built-in self-repair module 203 of the SoC 20 in the diagram can be the third memory mentioned in the embodiment of the present invention (which may have the above-described...). Figure 1 The built-in self-healing module 102 in the system-on-a-chip 20 may include some or all of the functions of the CPU and GPU in the processor 200 of the system-on-a-chip 20. Figure 3(Taking two processing units as an example); the CPU may include one or more first memories, and the GPU may also include one or more first memories; the on-chip storage module 202 stores the target repair information of the CPU and the target repair information of the GPU. When the on-chip system 20 is powered on, the target repair information of the CPU and the target repair information of the GPU stored in the on-chip storage module 202 can be loaded into the built-in self-repair module 203 to reduce the time for the CPU or GPU to read data from the outside. Further, taking the CPU as the target processing unit as an example, when the CPU is powered on, if the target repair information of the CPU is not stored in the target storage area inside the CPU, the CPU can obtain its own target repair information from the built-in self-repair module 203 outside the CPU, and perform memory bad point repair based on the target repair information. At the same time, the target repair information can also be stored in the target storage area inside the CPU, so that when the CPU is powered on again, the CPU can directly perform memory bad point repair based on the internally stored target repair information, without having to obtain the target repair information from the outside of the CPU again, reducing the time for the CPU to perform memory bad point repair, so that the CPU can resume normal operation more quickly and shorten the system power-on recovery time.

[0072] In one possible implementation, the target processing unit is further configured to: if the target repair information is not present in the target storage area, obtain the target repair information of the target processing unit from the third memory and store it in the internal target storage area. Specifically, if the target repair information is not present in the target storage area of ​​the target processing unit, the target processing unit needs to obtain its own target repair information from the outside, that is, it can obtain its own target repair information from the third memory outside the target processing unit. Then, the target processing unit can perform memory bad pixel repair based on the target repair information, and can also store the target repair information in the target storage area, so that when the target processing unit is powered on again, the target processing unit can directly perform memory bad pixel repair based on the internally stored target repair information, without having to obtain the target repair information from the outside of the target processing unit again, reducing the time for the target processing unit to perform memory bad pixel repair, thereby enabling the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0073] For example, such as Figure 4As shown, taking the CPU as the target processing unit as an example, when the CPU is powered on, if the target repair information of the CPU is not stored in the target storage area inside the CPU, the CPU can obtain its own target repair information from the built-in self-repair module 203 outside the CPU, and perform memory bad point repair based on the target repair information. At the same time, the target repair information can also be stored in the target storage area inside the CPU, so that when the CPU is powered on again, the CPU can directly perform memory bad point repair based on the internally stored target repair information, without having to obtain the target repair information from outside the CPU again. This reduces the time for the CPU to perform memory bad point repair, so that the CPU can resume normal operation more quickly and shorten the system power-on recovery time.

[0074] It should be noted that, as Figure 5 As shown, Figure 5 This is a schematic diagram of the internal structure of a processing unit provided in an embodiment of the present invention. Each processing unit may include one or more SRAMs, and each SRAM is allocated or divided into a target storage area for storing its own repair information. The number of SRAMs can be adjusted according to application requirements and is not specifically limited here. It should be emphasized that the multiple first memories mentioned above can constitute one SRAM in the processing unit, and the target repair information can also represent the repair information of that SRAM. Since the workflow of each SRAM in the processing unit is similar, this embodiment of the present invention uses one SRAM as an example for detailed description, and the workflow of other SRAMs will not be repeated.

[0075] In one possible implementation, the target processing unit further includes a first register; specifically, the target processing unit is used to store the target repair information in the first register as the target storage area. Specifically, a first register is added internally to the target processing unit as a target storage area, dedicated to storing the target repair information of the target processing unit. This first register remains powered on even when the target processing unit is in an idle, power-off state, ensuring that the target repair information stored in the first register is not lost when the target processing unit is idle and powered off. Furthermore, when the target processing unit is powered on again, it can directly perform bad pixel repair on the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit. This reduces the time spent on memory bad pixel repair, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0076] In one possible implementation, the first register is powered by a dedicated power domain so that when some or all components of the target processing unit other than the first register are powered down, the first register is powered on. Alternatively, the first register is powered by a normally open power domain of the target processing unit so that when some components of the target processing unit other than the first register are powered down, the first register is powered on. Specifically, some or all components of the target processing unit other than the first register can be powered on and off by the first power domain, while the first register can be powered on and off by other power domains. When the target processing unit is idle, the first power domain can be disconnected to power down the target processing unit to save power, but the first register remains powered on to ensure that the stored target repair information is not lost. Furthermore, when the target processing unit is powered on again, it can directly perform bad pixel repair on the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit. This reduces the time for the target processing unit to perform bad pixel repair on the memory, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0077] For example, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the internal structure of a target processing unit according to an embodiment of the present invention. The target processing unit includes four first memories, namely C0, C1, C2, and C3; C4 is a spare memory; the first register is the target storage area, and the first register can be a reserved register; some or all of the components in the target processing unit except for the first register can be powered on and off by the first power domain VDDP, and the first register in the target processing unit can be powered on and off by the dedicated power domain VDD_ret and VDDP together. When the target processing unit is in an idle state, VDDP is powered off, and the computing unit and first memories in the target processing unit are powered off, but VDD_ret is not powered off, so that the target repair information stored in the first register is not lost.

[0078] It should be noted that the reserved register adopts a dual-power supply structure, with VDD_ret always powered. This type of register adds save and restore functions to the functions of ordinary registers. The save port pulse signal saves the data at its Q-end to the latch in its internal VDD_ret power domain; the restore port pulse signal returns the data registered in the VDD_ret power domain to the Q-end, and both operations are completed on the nanosecond scale. Therefore, to save power, before powering down VDDP and VDDC, the target repair information is first saved to the latch in the VDD_ret domain. Then, before the target processing unit is required to work, the target repair information is quickly restored to the Q-end, so that the target processing unit can obtain the target repair information from the reserved register after power-on.

[0079] For example, such as Figure 7 As shown, Figure 7 This is a schematic diagram of the internal structure of another target processing unit provided in an embodiment of the present invention. The target processing unit includes four first memories, namely C0, C1, C2, and C3; C4 is a spare memory; the first register is the target storage area, and the first register can be composed of VDDC domain registers; some or all of the components in the target processing unit, except for the first register and the multiple first memories, can be powered on and off by the first power domain VDDP, and the first register and the multiple first memories can be powered on and off by the second power domain VDDC. When the target processing unit is in an idle state, VDDP is powered off, and the computing units and other components in the target processing unit are powered off, but VDDC is not powered off, so that the target repair information stored in the first register is not lost.

[0080] It should be noted that the first register can consist of a VDDC domain register and a level shifter. The level shifter mainly performs the function of normal signal transmission between the VDDP and VDDC power supplies. Figure 7 The device can be applied to scenarios where the digital logic circuit is powered off but the data in the first memory needs to be saved; compared to the above Figure 6 The device's first register reduces save and restore operations, further reducing the power-on recovery time of the target processing unit, but requires VDDC to remain powered.

[0081] In one possible implementation, the target processing unit further includes a decoding module. The target processing unit is further configured to: obtain the target repair information from the first register through the decoding module, and decode and configure the plurality of first memories based on the target repair information. Specifically, when the target processing unit is powered on again, it can directly configure the plurality of first memories in the target processing unit through the decoding module based on the target repair information stored in the first register, thereby preventing the target processing unit from using the faulty first memory. Since the target processing unit does not need to obtain the target repair information from outside the target processing unit after power-on, the time for the target processing unit to repair memory bad points is reduced, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0082] For example, such as Figure 8 As shown, Figure 8 This diagram illustrates a power-on recovery process for a target processing unit according to an embodiment of the present invention. The diagram assumes the target processing unit includes four first memories, C0, C1, C2, and C3, where C1 is the faulty memory; C4 is the backup memory; and the first register is the target storage area. When the target processing unit is powered on again, the decoding module retrieves target repair information from the first register and decodes it, revealing that C1 is the faulty memory. Further, 0111 can be sent to the first memory in the target processing unit, and then C1 can be isolated via a selector. The backup memory C4 can then be enabled to prevent the target processing unit from using the faulty first memory.

[0083] For example, such as Figure 9 As shown, Figure 9 This diagram illustrates another power-on recovery process for a target processing unit according to an embodiment of the present invention. The diagram assumes the target processing unit includes four first memories, C0, C1, C2, and C3, where C1 is the faulty memory; C4 is the backup memory; and the first register is the target storage area. When the target processing unit is powered on again, the decoding module obtains target repair information from the first register and decodes it, revealing that C1 is the faulty memory. Further, 0111 can be sent to the first memory in the target processing unit, and then C1 can be isolated via a selector. Then, the backup memory C4 can be enabled to prevent the target processing unit from using the faulty first memory.

[0084] In one possible implementation, the target processing unit is specifically configured to: store the target repair information in the plurality of first memories as the target storage area. The plurality of first memories are powered by the normally-on power domain of the target processing unit, ensuring that when other components in the target processing unit are powered down, the plurality of first memories are powered on. Specifically, a target storage area is allocated within the plurality of first memories inside the target processing unit specifically for storing the target repair information of the target processing unit. This storage area remains powered on even when the target processing unit is in an idle, powered-off state, ensuring that the target repair information stored in the storage area is not lost when the target processing unit is idle and powered down. Therefore, when the target processing unit is powered on again, it can directly perform bad pixel repair on the first memories based on the target repair information stored in the plurality of first memories, without needing to obtain the target repair information from outside the target processing unit. This reduces the time spent on bad pixel repair, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0085] For example, such as Figure 10 As shown, Figure 10 This is a schematic diagram of the internal structure of a target processing unit according to another embodiment of the present invention. The target processing unit includes four first memories, namely C0, C1, C2, and C3; C4 is a spare memory; C0', C1', C2', and C3' are divided target storage areas; some or all of the components in the target processing unit, except for the first memories, can be powered on and off by VDDP, and the first memories in the target processing unit can be powered on and off by VDDC. When the target processing unit is in an idle state, VDDP is powered off, and the computing units and other components in the target processing unit are powered off, but VDDC is not powered off, so that the target repair information stored in the first memories is not lost.

[0086] It should be noted that SRAM is a device with extremely high area utilization. Figure 6 The device and the above Figure 7 Devices that can cause an increase in the invalid area of ​​SRAM can lead to a serious waste of SoC resources. Therefore, the above-mentioned Figure 10 The device directly utilizes multiple first memories to store target repair information, which has a relatively small impact on the area.

[0087] In one possible implementation, the target processing unit includes a second register, and the target processing unit is further configured to: when the target processing unit switches from the first mode to the second mode, retrieve and store the target repair information from the plurality of first memories through the second register. Specifically, to facilitate subsequent decoding of the target repair information, a second register can be added to the target processing unit, and the second register is also powered off when the target processing unit is powered on. When the target processing unit is powered on again, the second register can retrieve and store the target repair information from the first memories. For example, as... Figure 10 As shown, when the target processing unit is powered on again, the second register first obtains the target repair information from C0', C1', C2' and C3' and saves it so that the subsequent decoding module can decode the target repair information.

[0088] In one possible implementation, the target processing unit further includes a decoding module. The target processing unit is further configured to: obtain the target repair information from the second register through the decoding module, and decode and configure the plurality of first memories based on the target repair information. Specifically, when the target processing unit is powered on again, the target processing unit can configure the plurality of first memories in the target processing unit through the decoding module based on the target repair information in the second register, thereby preventing the target processing unit from using the faulty first memory. Since the target processing unit does not need to obtain target repair information from outside the target processing unit after power-on, the time for the target processing unit to repair memory bad points is reduced, thus enabling the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0089] For example, such as Figure 11 As shown, Figure 11 This is a schematic diagram illustrating another power-on recovery of a target processing unit according to an embodiment of the present invention. The diagram assumes the target processing unit includes four first memories, namely C0, C1, C2, and C3, where C1 is the faulty memory; C4 is the backup memory; and C0', C1', C2', and C3' are divided target storage areas. When the target processing unit is powered on again, the second register first reads and stores target repair information from C0', C1', C2', and C3'. Then, the decoding module obtains the target repair information from the second register and decodes it, revealing that C1 is the faulty memory. Further, 0111 can be sent to the first memory in the target processing unit, and then C1 can be isolated via a selector. The backup memory C4 can then be enabled to prevent the target processing unit from using the faulty first memory.

[0090] In one possible implementation, the target processing unit further includes a backup memory; specifically, the target processing unit is used to: determine the faulty first memory through the decoding module based on the target repair information; isolate the faulty first memory for bad pixels; and enable the backup memory. Specifically, when the target processing unit is powered on again, the target processing unit can directly determine the faulty first memory among multiple first memories through the decoding module based on the target repair information stored in the target storage area, isolate the faulty first memory for bad pixels, and then enable the backup memory to avoid the target processing unit using the faulty first memory, which could lead to system abnormalities.

[0091] For example, such as Figure 12 As shown, Figure 12 This is a schematic diagram of a system power-on recovery process provided by an embodiment of the present invention. When it is detected that the module (i.e., the processing unit) needs to work, the module is first powered on, and then it is determined whether it is a power-on scenario. If not, the processing unit directly obtains the local target repair information from the target storage area and inputs it into the SRAM. After the module completes the configuration information recovery, it starts to work normally. If it is, it can obtain its own target repair information from the on-chip storage module and serially input the target repair information into each SRAM of the module. After the module completes the configuration, it starts to work normally. At the same time, the configuration information needs to be saved, and the target repair information is stored inside the processing unit.

[0092] Through the embodiments of the present invention, a target storage area is added or partitioned within the target processing unit specifically for storing the target repair information of the target processing unit. This target storage area remains powered on even when the target processing unit is in an idle, power-off state, ensuring that the target repair information stored in the target storage area is not lost when the target processing unit is idle and powered off. Therefore, when the target processing unit is powered on again, it can directly perform bad pixel repair on the first memory based on the internally stored target repair information, without needing to obtain the target repair information from outside the target processing unit. This reduces the time spent on memory bad pixel repair, allowing the target processing unit to resume normal operation more quickly and shortening the system power-on recovery time.

[0093] The on-chip system of the present invention has been described in detail above. The related methods of the present invention are provided below.

[0094] Please see Figure 13 , Figure 13 This is a flowchart of a system power-on recovery method provided in an embodiment of the present invention. This method is applicable to the above-mentioned... Figure 2A system-on-chip (SoC) and a device comprising the SoC are described. The method may include steps S301-S302. The SoC includes N processing units, a target processing unit among the N processing units includes a plurality of first memories, all of which are volatile memories, and the target processing unit is any one of the N processing units, where N and M are integers greater than 0. Detailed description follows:

[0095] Step S301: The target processing unit stores target repair information in the internal target storage area, wherein the target repair information is information of the first memory that has failed among the plurality of first memories.

[0096] Step S302: When the target processing unit switches from the first mode to the second mode, the target processing unit reads the target repair information from the target storage area and performs bad pixel repair on the plurality of first memories.

[0097] Specifically, in the first mode, some or all components of the target processing unit, except for the target storage area, are in a power-off state, and the target storage area is in a power-on state; in the second mode, the entire target processing unit is in a power-on state.

[0098] In one possible implementation, the on-chip system further includes a second memory, which is a non-volatile memory; the method further includes storing the target repair information of each of the N processing units in the second memory.

[0099] In one possible implementation, the system-on-chip further includes a third memory, which is a volatile memory; when the system-on-chip switches from a power-down state to a power-on state, the method further includes: reading the target repair information of the target processing unit from the second memory through the third memory and storing it.

[0100] In one possible implementation, the method further includes: if the target repair information is not present in the target storage area, then the target processing unit obtains the target repair information from the third memory and stores it in the internal target storage area.

[0101] In one possible implementation, the target processing unit further includes a first register; storing target repair information in an internal target storage area through the target processing unit includes: storing the target repair information in the first register as the target storage area.

[0102] In one possible implementation, the first register is powered by a dedicated power domain such that when some or all components of the target processing unit other than the first register are powered down, the first register is powered on; or the first register is powered by a normally open power domain of the target processing unit such that when some components of the target processing unit other than the first register are powered down, the first register is powered on.

[0103] In one possible implementation, the target processing unit further includes a decoding module, and the method further includes: obtaining the target repair information from the first register through the decoding module in the target processing unit, and performing decoding configuration on the plurality of first memories based on the target repair information.

[0104] In one possible implementation, storing target repair information in the target storage area within the target processing unit includes: storing the target repair information in the plurality of first memories as the target storage area, wherein the plurality of first memories are powered by the normally open power domain of the target processing unit so that when some components in the target processing unit other than the plurality of first memories are in a power-off state, the plurality of first memories are in a power-on state.

[0105] In one possible implementation, the target processing unit includes a second register, and the method further includes: when the target processing unit switches from the first mode to the second mode, obtaining the target repair information from the plurality of first memories through the second register and storing it.

[0106] In one possible implementation, the target processing unit further includes a decoding module, and the method further includes: obtaining the target repair information from the second register through the decoding module in the target processing unit, and performing decoding configuration on the plurality of first memories based on the target repair information.

[0107] In one possible implementation, the target processing unit further includes a backup memory; the bad pixel repair of the plurality of first memories includes: determining the faulty first memory through the decoding module based on the target repair information; isolating the faulty first memory for bad pixels and enabling the backup memory.

[0108] The method provided by the embodiments of the present invention can shorten the recovery time of the processing unit after power-on.

[0109] This application provides a computer storage medium, characterized in that the computer storage medium stores a computer program, which, when executed by a processor, implements any of the above-described system power-on recovery methods.

[0110] This application provides an electronic device including a processor configured to support the implementation of corresponding functions in any of the above-described system power-on recovery methods. The electronic device may also include a memory coupled to the processor, which stores necessary program instructions and data. The electronic device may also include a communication interface for communication with other devices or communication networks.

[0111] This application provides a chip system including a processor for supporting an electronic device in implementing the functions described above, such as generating or processing information involved in the power-on recovery method described above. In one possible design, the chip system further includes a memory for storing necessary program instructions and data of the electronic device. This chip system may be composed of chips or may include chips and other discrete devices.

[0112] This application provides a computer program, characterized in that the computer program includes instructions that, when executed by a computer, cause the computer to perform the aforementioned system power-on recovery method.

[0113] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0114] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0116] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0118] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0119] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A system-on-a-chip, characterized in that, The system-on-a-chip includes a processor, which includes N processing units. A target processing unit among the N processing units includes multiple first memories, all of which are volatile memories. The target processing unit is any one of the N processing units, where N is an integer greater than 1. The target processing unit is used for: Target repair information is stored in the internal target storage area. The target repair information is information about the first memory that has failed among the plurality of first memories. When the target processing unit switches from the first mode to the second mode, it reads the target repair information from the target storage area and performs bad pixel repair on the plurality of first memories; wherein, in the first mode, some or all of the components of the target processing unit except for the target storage area are in a power-off state, and the target storage area is in a power-on state; in the second mode, the target processing unit as a whole is in a power-on state; The on-chip system further includes a second memory, which is a non-volatile memory; the second memory is used for: The target repair information of each of the N processing units is stored.

2. The system as described in claim 1, characterized in that, The system-on-chip further includes a third memory, which is a volatile memory; when the system-on-chip switches from a power-down state to a power-on state, the third memory is used for: The target repair information of the target processing unit is read from the second memory and stored.

3. The system as described in claim 2, characterized in that, The target processing unit is further configured to: If the target repair information is not present in the target storage area, the target repair information of the target processing unit is obtained from the third memory and stored in the internal target storage area.

4. The system according to any one of claims 1-3, characterized in that, The target processing unit further includes a first register; the target processing unit is specifically used for: The first register is used as the target storage area to store the target repair information.

5. The system as described in claim 4, characterized in that, The first register is powered by a dedicated power domain so that when some or all components of the target processing unit other than the first register are powered down, the first register is powered on; or the first register is powered by a normally open power domain of the target processing unit so that when some components of the target processing unit other than the first register are powered down, the first register is powered on.

6. The system as described in claim 5, characterized in that, The target processing unit further includes a decoding module, and the target processing unit is further configured to: The decoding module obtains the target repair information from the first register and performs decoding configuration on the plurality of first memories based on the target repair information.

7. The system according to any one of claims 1-3, characterized in that, The target processing unit is specifically used for: The plurality of first memories are used as the target storage area to store the target repair information. The plurality of first memories are powered by the normally open power domain of the target processing unit so that when some components in the target processing unit other than the plurality of first memories are in a power-off state, the plurality of first memories are in a power-on state.

8. The system as described in claim 7, characterized in that, The target processing unit includes a second register, and the target processing unit is further configured to: When the target processing unit switches from the first mode to the second mode, it retrieves the target repair information from the plurality of first memories through the second register and stores it.

9. The system as described in claim 8, characterized in that, The target processing unit further includes a decoding module, and the target processing unit is further configured to: The target repair information is obtained from the second register through the decoding module, and the multiple first memories are decoded and configured based on the target repair information.

10. The system as described in claim 9, characterized in that, The target processing unit further includes a backup memory; the target processing unit is specifically used for: Based on the target repair information, the first memory that has malfunctioned is determined by the decoding module; The faulty first memory is isolated for bad spots, and the backup memory is then enabled.

11. A system power-on recovery method, characterized in that, The method is applied to a system-on-a-chip (SoC), wherein the SoC includes a processor, the processor includes N processing units, a target processing unit among the N processing units includes a plurality of first memories, all of which are volatile memories, and the target processing unit is any one of the N processing units, where N is an integer greater than 1. The target processing unit stores target repair information in its internal target storage area. The target repair information is information about the first memory that has failed among the plurality of first memories. When the target processing unit switches from the first mode to the second mode, it reads the target repair information from the target storage area and performs bad pixel repair on the plurality of first memories. In the first mode, some or all components of the target processing unit except the target storage area are in a power-off state, and the target storage area is in a power-on state. In the second mode, the target processing unit is in a power-on state. The on-chip system further includes a second memory, which is a non-volatile memory; the method further includes: The target repair information of each of the N processing units is stored in the second memory.

12. The method as described in claim 11, characterized in that, The system-on-chip also includes a third memory, which is a volatile memory; When the on-chip system switches from a power-down state to a power-on state, the method further includes: The target repair information of the target processing unit is read from the second memory through the third memory and stored.

13. The method as described in claim 12, characterized in that, The method further includes: If the target repair information is not present in the target storage area, the target repair information of the target processing unit is obtained from the third memory by the target processing unit and stored in the internal target storage area.

14. The method according to any one of claims 11-13, characterized in that, The target processing unit further includes a first register; the storage of target repair information in the internal target storage area by the target processing unit includes: The first register is used as the target storage area to store the target repair information.

15. The method as described in claim 14, characterized in that, The first register is powered by a dedicated power domain so that when some or all components of the target processing unit other than the first register are powered down, the first register is powered on; or the first register is powered by a normally open power domain of the target processing unit so that when some components of the target processing unit other than the first register are powered down, the first register is powered on.

16. The method as described in claim 15, characterized in that, The target processing unit further includes a decoding module, and the method further includes: The target repair information is obtained from the first register by the decoding module in the target processing unit, and the multiple first memories are decoded and configured based on the target repair information.

17. The method according to any one of claims 11-13, characterized in that, The storage of target repair information in the internal target storage area by the target processing unit includes: The plurality of first memories are used as the target storage area to store the target repair information. The plurality of first memories are powered by the normally open power domain of the target processing unit so that when some components in the target processing unit other than the plurality of first memories are in a power-off state, the plurality of first memories are in a power-on state.

18. The method as described in claim 17, characterized in that, The target processing unit includes a second register, and the method further includes: When the target processing unit switches from the first mode to the second mode, it retrieves the target repair information from the plurality of first memories through the second register and stores it.

19. The method as described in claim 18, characterized in that, The target processing unit further includes a decoding module, and the method further includes; The target repair information is obtained from the second register by the decoding module in the target processing unit, and the multiple first memories are decoded and configured based on the target repair information.

20. The method as described in claim 19, characterized in that, The target processing unit further includes a backup memory; the bad pixel repair of the plurality of first memories includes: Based on the target repair information, the first memory that has malfunctioned is determined by the decoding module; The faulty first memory is isolated for bad spots, and the backup memory is then enabled.

21. A computer storage medium, characterized in that, The computer storage medium stores a computer program that, when executed by a processor, implements the method described in any one of claims 11-20.

22. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a computer or processor, causes the computer or processor to perform the method as described in any one of claims 11-20.

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