Chip design reorganization method, electronic device, and medium
By establishing interconnections through a high-level abstraction layer and using the bus to reconstruct structural attribute information to generate chip design RTL code, the problems of low chip design efficiency and poor scalability in existing technologies are solved, and efficient and scalable chip design is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
- Filing Date
- 2022-05-19
- Publication Date
- 2026-06-19
AI Technical Summary
In existing chip design technologies, manually establishing interconnects is inefficient and difficult to maintain. Excel descriptions are simple but difficult to customize interconnect rules. Low-level signal code processing is cumbersome, resulting in low design efficiency, poor scalability, and difficulty in achieving flexible configuration and reconfiguration.
Interconnects are established based on a high-level abstraction layer. Chip design RTL code is generated through bus interconnect definitions, avoiding the need to process low-level code. Interconnect relationships are established by reconstructing structural attribute information using the bus, resulting in an efficient and scalable chip design.
It improves chip reconfiguration efficiency, reduces errors, and enables efficient, scalable, and configurable chip design.
Smart Images
Figure CN117131834B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a chip design reconfiguration method, electronic device, and medium. Background Technology
[0002] In chip design, interconnections between multiple modules and layers are typically required, especially for large-scale chip designs like GPUs. Manually establishing these interconnections is extremely inefficient, necessitating automated interconnection. Current technologies often employ scripts (e.g., Excel) using pin-based interconnects. For example, all pins are listed in an Excel file, and the script retrieves signals from the Excel file for appropriate interconnection. However, this approach has several drawbacks: storing all signals in an Excel file makes maintenance difficult, Excel processing is very slow, and the simplistic nature of Excel makes it difficult to define custom interconnection rules, resulting in poor scalability. Furthermore, current technologies establish interconnections based on the underlying signal layer. Using these methods for chip design requires writing extensive low-level signal code (e.g., Verilog code), leading to low design efficiency, error susceptibility, and poor scalability, hindering flexible configuration and reconfiguration. Therefore, providing an error-resistant, efficient, scalable, reconfigurable, and configurable chip design technology is a pressing technical challenge. Summary of the Invention
[0003] The purpose of this invention is to provide a chip design reconfiguration method, electronic device, and medium. Based on a high-level abstraction layer, interconnection is established. During the chip reconfiguration process, there is no need to process the low-level code. Only the high-level reconfiguration rules need to be modified according to the reconfiguration information, which reduces the risk of errors and improves the chip reconfiguration efficiency, thereby improving the chip design efficiency.
[0004] According to a first aspect of the present invention, a chip design reconfiguration method is provided, applied to the reconfiguration process of chip logic interconnects to physical interconnects, comprising:
[0005] Step D1: Obtain the original target design information {DIY1, DIY2, ... DIY} N IDF 01 IDF 02 ...IDF 0R DIY n This represents the interconnect information of the nth design, where n ranges from 1 to N, and N is the number of the original target design levels. (IDF) 0r This represents the attribute information of the bus description reconfiguration structure corresponding to the r-th bus interconnect structure, where R is the total number of bus interconnects in the original target design information.
[0006] Step D2: Obtain chip design reconfiguration information, parse the original target design information, determine the target reconfiguration starting level y based on the chip design reconfiguration information, 1≤y≤N, and parse the DIY... y DIY y+1 , ...DIY N Generate a database of information on units to be recombined;
[0007] Step D3: Based on the chip design reconfiguration information, the reconfigurable cell information database, and the IDF... 01 IDF 02 ...IDF 0R DIY generated by layer-by-layer recombination y DIY y+1 ', ...DIY T ', among which, DIY u ' represents the u-th design interconnection information after reorganization, where u ranges from y to T, and T is the number of target design levels after reorganization. DIY y DIY y+1 ', ...DIY T 'Bus interconnection relationship of information to be reassembled in the middle and DIY y DIY y+1 , ...DIY N The bus interconnection relationship of the corresponding unit information to be reassembled remains unchanged;
[0008] Step D4: Generate recombination target design information {DIY1, DIY2, ... DIY} y-1 DIY y DIY y+1 ', ...DIY T ';IDF 01 IDF 02 ...IDF 0R}
[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being configured to perform the method described in the first aspect of the present invention.
[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer instructions are configured to perform the method described in the first aspect of the present invention.
[0011] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the chip design reconfiguration method, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It possesses at least the following advantages:
[0012] This invention establishes interconnections based on a high-level abstraction layer. During chip reconfiguration, there is no need to process the underlying code; only the high-level reconfiguration rules need to be modified according to the reconfiguration information. This reduces the risk of errors and increases reconfiguration efficiency, thereby improving chip design efficiency.
[0013] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0014] Figure 1 A flowchart of a method for automatically generating RTL code for chip design provided in Example 1;
[0015] Figure 2 This is a flowchart of the method for automatically generating empty chip casings provided in Embodiment 2;
[0016] Figure 3 A flowchart of the chip weak drive shell generation method provided in Example 3;
[0017] Figure 4 The flowchart of the chip design reconfiguration method provided in Example 4. Detailed Implementation
[0018] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, describes in detail the specific implementation methods and effects of a chip design reconfiguration method, electronic device, and medium proposed according to the present invention.
[0019] Example 1
[0020] Embodiment 1 of the present invention provides a method for automatically generating RTL code for chip design, such as... Figure 1 As shown, it includes:
[0021] Step A1: Obtain multiple basic unit information from a preset basic unit information library as first basic unit information; generate first design interconnect information by defining the first basic unit information through bus interconnection; add the first design interconnect information to a preset custom design interconnect information library; the basic unit information library stores multiple basic unit information, and the basic unit information is RTL code.
[0022] It should be noted that the basic unit information is pre-written RTL code, such as RTL code written in Verilog, VHDL, or SystemVerilog. The basic unit information library can pre-set multiple common basic unit information entries, and new basic unit information can be added according to new design requirements. In other words, the basic unit information library is customizable and has good extensibility. The first basic unit information is used to form the first design interconnect information. The first basic unit information can be any basic unit information entry in the basic unit information library; multiple first basic units can use the same basic unit information or different basic unit information entries. Each design interconnect information entry can be defined as a DIY (DesignInterconnect assembly).
[0023] Step A2: Obtain multiple i-th design interconnection information from the custom design interconnection information library, and generate j-th design interconnection information by defining the multiple i-th design interconnection information through bus interconnection; or, obtain at least one i-th design interconnection information from the custom design interconnection information library, and obtain at least one basic unit information from the preset basic unit information library as j-th basic unit information, generate j-th design interconnection information by defining the i-th design interconnection information and j-th basic unit information through bus interconnection, and add j-th design interconnection information to the preset custom design interconnection information library. The value of j ranges from 2 to N, where N is the total number of target design levels, and the value of i ranges from 1 to j-1.
[0024] It is understandable that the first design interconnect information is composed of interconnected basic unit information. Starting from the second design interconnect information, the components of each level of design interconnect information can include the currently generated design interconnect information and basic unit information as components. All components are interconnected through bus interconnect definitions, requiring only simple bus interconnect definitions and eliminating the need to write extensive low-level signal code. The j-th basic unit information is used to compose the j-th design interconnect information. Specifically, it can be any basic unit information from the basic unit information library. Multiple j-th basic units can be the same basic unit information or different basic unit information. Each generated design interconnect information, i.e., each DIY, can serve as a component of subsequent levels of design interconnect information.
[0025] Step A3: Generate chip design RTL code based on the Nth design interconnect information.
[0026] Chip design RTL code can specifically be Verilog code, System Verilog code, or VHDL code, etc. As an example, in steps A1 and A2, generating corresponding design interconnect information through bus interconnect definitions includes: configuring corresponding bus reconfiguration structures for each basic unit information and design interconnect information; configuring attribute information of the corresponding interconnect bus reconfiguration structure for each initiating end; and establishing interconnection relationships between corresponding bus reconfiguration structures based on the interconnection relationships corresponding to each design interconnect information, thereby generating corresponding design interconnect information. It should be noted that the attribute information of the interconnect bus reconfiguration structure refers to the detailed parameter information of the interconnect bus reconfiguration structure. Configuring the corresponding bus reconfiguration structure includes: defining the name of the bus reconfiguration structure and selecting the corresponding bus reconfiguration structure type from a preset bus description reconfiguration library. It should be noted that each component may have one or more bus reconfiguration structures. A component refers to the hierarchical interconnect information generated by a basic unit or a certain level. Two components can be interconnected through one or more sets of bus reconfiguration structures. Design interconnect information and its components can also be interconnected through one or more sets of bus reconfiguration structures, and based on this, interconnect with other design interconnect information via the bus.
[0027] As an example, in steps A1 and A2, establishing the interconnection relationship between corresponding bus reconfiguration structures based on the interconnection relationship corresponding to each design interconnection information, and generating the corresponding design interconnection information, includes: defining the interconnection relationship between bus reconfiguration structures, and the interconnection relationship between signal lines in connected bus reconfiguration structures; establishing the corresponding interconnection relationship between bus reconfiguration structures based on the interconnection relationship between all bus reconfiguration structures; establishing the connection between each initiating bus reconfiguration structure and the corresponding receiving bus reconfiguration structure; and adaptively establishing the connection between signal lines based on the attribute information of the interconnected bus reconfiguration structure stored at the initiating end, and the interconnection relationship between signal lines in connected bus reconfiguration structures, thereby generating the corresponding design interconnection information. It should be noted that between two components with an interconnection relationship, one is the initiating end and the other is the receiving end. The distinction between the initiating end and the receiving end is common knowledge in the art and will not be described further here. In this embodiment of the invention, only the attribute information of the interconnected bus reconfiguration structure stored at each initiating end is needed; the initiating end and the receiving end establish an interconnection relationship and share the attribute information of the corresponding interconnected bus reconfiguration structure.
[0028] As an example, in step A1, the first basic unit information is used to generate first design interconnect information through bus interconnect definition, which may specifically include:
[0029] Step A11: Based on the preset bus description reconfiguration library, configure one or more corresponding bus reconfiguration structures for each first basic unit information and first design interconnection information, and configure the attribute information of the corresponding interconnection bus reconfiguration structure for each initiating end;
[0030] Step A12: Based on the interconnection relationship between the first basic unit information and the interconnection relationship between the first basic unit information and the first design interconnection information bus reconfiguration structure, establish the interconnection between the corresponding bus reconfiguration structures and generate the first design interconnection information.
[0031] As an example, in step A2, generating j-th design interconnect information from the plurality of i-th design interconnect information through bus interconnect definition includes:
[0032] Step A21: Based on the preset bus description reconfiguration library, configure one or more bus reconfiguration structures corresponding to the interconnection information of the j-th design, and configure the attribute information of the corresponding interconnection bus reconfiguration structure for each initiating end;
[0033] Step A22: Based on the interconnection relationship between the plurality of i-th design interconnection information and the interconnection relationship between the plurality of i-th design interconnection information and the j-th design interconnection information bus reconfiguration structure, establish the interconnection between the corresponding bus reconfiguration structures and generate the j-th design interconnection information.
[0034] As an example, in step A2, generating the j-th design interconnect information by defining the i-th design interconnect information and the j-th basic unit information through bus interconnection includes:
[0035] Step A23: Based on the preset bus description reconfiguration library, configure one or more corresponding bus reconfiguration structures for each j-th basic unit information and j-th design interconnection information, and configure the attribute information of the corresponding interconnection bus reconfiguration structure for each initiator.
[0036] Step A24: Based on the interconnection relationship between the i-th design interconnection information and the j-th basic unit information, and the interconnection relationship between the i-th design interconnection information, the j-th basic unit information and the j-th design interconnection information bus reconfiguration structure, establish the interconnection between the corresponding bus reconfiguration structures and generate the j-th design interconnection information.
[0037] As one embodiment, the preset bus description refactoring library includes one or more predefined bus refactoring structures IDF (Interface Description Refactor), and uses IDF. mThis represents the m-th bus reconfiguration structure, where m ranges from 1 to M, and M is the number of bus reconfiguration structures. It's understandable that the IDFs in the bus description reconfiguration library can be added to or removed according to specific application requirements; they are customizable and highly extensible. Once an IDF is defined, it can be directly called and used without needing to be redefined in the design.
[0038] The IDF follows any one of the preset bus protocols. The bus protocol can be an existing industry standard bus protocol, such as AMBA (Arm Microcontroller Bus Architecture) or PCI-Express (Peripheral Component Interconnect Express). Alternatively, it can be a custom bus protocol based on design requirements. The bus reconfiguration structure is generated according to the preset bus description reconfiguration structure. m The corresponding bus description reconfiguration structure attribute information includes mX information segments {S1} m S2 m ,…S mX m}, where S mx m S represents the information segment corresponding to the mx-th signal line in the m-th bus reconfiguration structure. mx m This includes signal description information, timing diagram information, direction information, signal width information, reset value, and default value. The value of `mx` ranges from 1 to `mX`. It can be understood that different IDFs can correspond to different numbers of signals, with each signal corresponding to an information segment; that is, the value of `mX` may differ for different IDFs. The signal description information describes the signal and can be used to generate documentation. The direction information includes input, output, and inout, configured according to the specific direction of the signal. The signal width information can be a fixed value or a configurable value. The reset value and default value are pre-configured according to the specific signal. The reset value is used to generate a reasonable drive value, serving as a weak drive value. In complex signal application scenarios, S... mx m It also includes a structure describing the signal, according to S mx mThe corresponding application scenario is configured with a structure describing the signal, for example, a structure describing 256 bits of data, where different data segments represent different meanings. IDF, basic unit information, and generated hierarchical design information are all universal and reusable. Furthermore, detailed parameters in the IDF can be configured to adapt to design requirements without affecting high-level descriptions. Since the IDF framework, most parameters, and basic unit information are predetermined, they can be directly called during the design process, resulting in high design efficiency and reduced error rates. It should be noted that for the same type of bus reconfiguration structure, details such as signal width and address width may differ in different applications. In such cases, feature variables can be used to adapt the attribute information within the IDF.
[0039] During the interconnection process between corresponding bus structures, if there are end interconnection ports in the interconnection chain, the end interconnection port of type output will be set to a floating state, and the end interconnection port of type input will be set to a corresponding default value, or the signal port corresponding to the end interconnection port of type input will be set to a corresponding custom value. It should be noted that one interconnection port corresponds to a group of signal ports.
[0040] Most existing bus interconnects are handled manually or by scripts using Verilog itself. This involves processing signal lines, which are the lowest-level signals. Even buses are expanded; for example, a bus may contain 100 signal lines. Existing technologies require processing each of these 100 signal lines individually. In the embodiments of this invention, by defining an IDF (Integrated Data Framework), interconnect relationships are defined. Interconnect relationships can be established using only a high-level abstract description, a concise description, declaring the bus type, defining the bus name, and defining the interconnect relationships. All bus details are defined in the IDF, greatly improving the efficiency and accuracy of interconnect design, thereby improving chip design efficiency.
[0041] It should be noted that any existing implementation of chip design RTL code based on Nth design interconnect information falls within the protection scope of this invention. Those skilled in the art will also understand that any technology implemented after this application that generates chip design RTL code based on Nth design interconnect information also falls within the protection scope of this invention. As a preferred example, in step A3,
[0042] Step A31: Based on the RTL code corresponding to the basic unit information of each component in the Nth design interconnection information, the interconnection relationship between each generated part, and the reconfiguration structure information of each bus, generate the target design RTL code according to the preset RTL code format template.
[0043] In the Nth design interconnection information, each basic unit information corresponds to a pre-written RTL code. The interconnection relationship between each component is obtained from the bus reconfiguration structure information, and the corresponding bus attribute information is obtained. The target design RTL code is generated by expanding layer by layer according to the preset RTL code format template.
[0044] The preset RTL code format template can be a Verilog code format template, a SystemVerilog code format template, or a VHDL RTL code format template.
[0045] It should be noted that if it is necessary to generate corresponding design RTL code from the design interconnection information of a certain level in the Nth design interconnection information, then the design interconnection information of that level can be obtained, and the corresponding design RTL code can be generated according to the process in step A31.
[0046] In Example 1, only low-level RTL code needs to be written for the basic unit information. Then, based on the basic unit information, the first design interconnect information, i.e., the first-level design interconnect information, is formed through bus interconnection. Subsequent levels of design interconnect information are all stacked from the generated design interconnect information and basic unit information. All components are defined through bus interconnection to generate the design interconnect information for each level. That is, each level of design interconnect information can be generated through only high-level abstract descriptions and simple bus interconnection definitions, without the need to write a large amount of low-level signal code, and without errors, thus improving chip design efficiency. It should be noted that the relevant technical details in other subsequent examples are also applicable to the relevant steps in this example, and will not be repeated here.
[0047] Example 2
[0048] Example 1 can generate a complete target design RTL code. However, in some application scenarios, such as accelerated regrouping, importing the entire target design is very time-consuming. For some designs, only the port information corresponding to the design is needed, without concern for the specific information of the internal components. In this case, generating an empty shell (Stub or Interface Module) containing only the port information of the design is sufficient. It should be noted that each level of design interconnect information can correspond to a design and a chip. Based on this, Example 2 provides a method for automatically generating chip empty shells, such as... Figure 2 As shown, it includes:
[0049] Step B1: Obtain multiple basic unit information from the preset basic unit information library as the first basic unit information. Based on the bus interconnection definition of the first basic unit information, generate a first design shell that only includes the first basic unit port information and the first design interconnection port information. Add the first design shell to the preset custom design shell library.
[0050] It is understood that the chip shell referred to in this embodiment only includes port information and does not include detailed RTL information of the specific components within the chip. The custom design shell library stores all generated design shells for direct use by subsequent design shells. In other words, generated design shells can be used as components in subsequent design shells, avoiding redundant design and improving chip design efficiency.
[0051] Step B2: Obtain multiple p-th design shells from the custom design shell library, and generate a q-th design shell that includes only the p-th design shell and the q-th design interconnection port information based on the multiple p-th design shells through bus interconnection definition;
[0052] or,
[0053] At least one p-th design shell is obtained from the custom design shell library, and at least one basic unit information is obtained from the preset basic unit information library as the q-th basic unit information. Based on the p-th design shell and at least one q-th basic unit information, a q-th design shell is generated by bus interconnection definition, which only includes the p-th design shell, the q-th basic unit port information and the q-th design interconnection port information.
[0054] The q-th empty design shell is added to the preset custom empty design shell library. The value of q ranges from 2 to N, where N is the total number of target design levels, and the value of p ranges from 1 to q-1.
[0055] Based on the q-th empty shell design, the RTL code of the q-th empty shell design can be generated according to the preset RTL code format template. It can be Verilog code, System Verilog code, or VHDL code, etc.
[0056] It should be noted that steps B1-B2 describe the method of generating corresponding empty design shells for each design level. However, it can be understood that if only some design levels need to be generated as empty design shells, while other design levels still require specific information about their internal components, then the parts requiring internal components can be generated according to steps A1 and A2 in Embodiment 1, which will not be repeated here. For design levels that require empty design shells, they should be generated according to steps B1-B2. That is, Embodiment 1 and Embodiment 2 can be combined and applied in chip design according to specific application requirements.
[0057] As an example, steps B1 and B2 include:
[0058] Step B10: Configure the information of each basic unit based on the preset bus description reconfiguration library, and design the bus reconfiguration structure corresponding to the interconnection information;
[0059] Bus description reconfiguration library, and IDF m The details of the corresponding bus description and reconfiguration structure, such as attribute information, have been described in detail in Example 1 and will not be repeated here.
[0060] Step B20: Based on the interconnection relationship corresponding to each design interconnection information, establish the interconnection relationship between the corresponding bus reconfiguration structures, and generate the corresponding design shell based on the interconnection relationship between the corresponding bus reconfiguration structures.
[0061] It should be noted that each component may have one or more bus reconfiguration structures. A component refers to a basic unit or hierarchical interconnection information generated at a certain level. Two components can be interconnected through one or more sets of bus reconfiguration structures. Design interconnection information and its components can also be interconnected through one or more sets of bus reconfiguration structures, and based on this, interconnect with other design interconnection information via buses. Correspondingly, each component and each level of interconnection information has one or more port information.
[0062] As an example, in step B10, configuring the corresponding bus reconfiguration structure includes:
[0063] Step B101: Define the name of the bus reconfiguration structure and select the corresponding bus reconfiguration structure type from the preset bus description reconfiguration library, and configure the attribute information of the corresponding interconnect bus reconfiguration structure for each initiating end.
[0064] It should be noted that among the two interconnected components, one is the initiator and the other is the receiver. The distinction between the initiator and the receiver is common knowledge in the art and will not be described in detail here. In this embodiment of the invention, only the attribute information of the interconnect bus reconfiguration structure needs to be stored at each initiator. The initiator and the receiver establish an interconnection relationship and share the attribute information of the corresponding interconnect bus reconfiguration structure.
[0065] As an example, step B20 includes:
[0066] B201. Based on the interconnection relationship corresponding to each design interconnection information and the attribute information of the interconnection bus reconstruction structure configured at each initiating end, the corresponding design module and the input, output, and inout port information of each level of the design module contained therein are generated according to the preset RTL code structure to obtain the corresponding design shell.
[0067] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.
[0068] Example 2 can generate empty chip design shells, which can accelerate chip design redesign and improve the efficiency of design redesign.
[0069] Example 3
[0070] Example 2 can be applied to chip reassembly scenarios, accelerating the reassembly process. However, in functional simulation and verification applications, while simply generating an empty chip shell can speed up chip design efficiency, it cannot achieve simulation and verification functions. This is because retaining only port information without port drivers leads to floating components of the received signal (e.g., a Verilog port's "Z state" causing "X state" propagation; "Z state" represents a high-impedance state, and "X state" represents an uncertain or unknown logic state). Therefore, to set corresponding reasonable drivers for each port information on the empty chip shell, i.e., weak drivers, thus enabling normal chip simulation and verification functions while accelerating the simulation and verification process and improving chip design efficiency, Example 3 provides a method for generating a chip weak-driver shell, including:
[0071] Step C1: Obtain multiple basic unit information from a preset basic unit information library as first basic unit information. Based on the bus interconnection definition of the first basic unit information, generate a first design weak drive shell including first basic unit port information, first design interconnection port information, and weak drive information corresponding to each port information. Add the first design weak drive shell to a preset custom design weak drive shell library. The basic unit information library stores multiple basic unit information, and the basic unit information is RTL code.
[0072] It is understood that the weak design shell referred to in this embodiment refers to a chip shell that includes port information and the corresponding reasonable driver information, but does not include detailed RTL information of the specific components in the chip. The custom weak design shell library stores all generated weak design shells for direct use by subsequent levels of weak design shells. That is, the generated weak design shells can be used as components in subsequent levels of weak design shells, avoiding redundant design and improving chip design efficiency.
[0073] Step C2: Obtain multiple p-th weak drive shell designs from the custom weak drive shell design library. Based on the multiple p-th weak drive shell designs, define a bus interconnection to generate a q-th weak drive shell design, including the p-th weak drive shell design, the q-th interconnection port information, and the weak drive information corresponding to each port information.
[0074] or,
[0075] At least one p-th weak drive shell is obtained from the custom weak drive shell library, and at least one basic unit information is obtained from the preset basic unit information library as the q-th basic unit information. Based on the p-th weak drive shell and at least one q-th basic unit information, a q-th weak drive shell is generated through bus interconnection definition, including the p-th weak drive shell, the q-th basic unit port information, the q-th design interconnection port information, and the weak drive information corresponding to each port information.
[0076] The qth weak drive shell design is added to the preset custom weak drive shell design library. The value of q ranges from 2 to N, where N is the total number of target design levels, and the value of p ranges from 1 to q-1.
[0077] Based on the design of the qth weak shell, the RTL code of the qth weak shell can be generated according to the preset RTL code format template. It can be Verilog code, System Verilog code, or VHDL code, etc.
[0078] It should be noted that steps C1-C2 describe the method of generating a corresponding weak design shell for each design level. However, it is understandable that if only some design levels need to be generated as weak design shells, while other design levels still require specific information about their internal composition, then the parts requiring internal composition information can be generated according to steps A1 and A2 in Embodiment 1, which will not be repeated here. For design levels that need to generate empty design shells, they should be generated according to steps B1-B2 in Embodiment 2, which will not be repeated here. For design levels that need to generate weak design shells, they should be generated according to steps C1-C2. That is, Embodiments 1, 2, and 3 can be combined and applied in chip design according to specific application requirements.
[0079] As an example, steps C1 and C2 include:
[0080] Step C10: Configure the information of each basic unit based on the preset bus description reconfiguration library, and design the bus reconfiguration structure corresponding to the interconnection information;
[0081] Bus description reconfiguration library, and IDF m The details of the corresponding bus description and reconfiguration structure, such as attribute information, have been described in detail in Example 1 and will not be repeated here.
[0082] Step C20: Based on the interconnection relationship corresponding to each design interconnection information, establish the interconnection relationship between the corresponding bus reconfiguration structures, generate each design generation unit and port information corresponding to the design interconnection information based on the interconnection relationship between the corresponding bus reconfiguration structures, obtain the weak drive information corresponding to each port information, add the weak drive information to the corresponding port information, and generate the corresponding design weak drive shell.
[0083] It should be noted that each component may have one or more bus reconfiguration structures. A component refers to a basic unit or hierarchical interconnection information generated at a certain level. Two components can be interconnected through one or more sets of bus reconfiguration structures. Design interconnection information and its components can also be interconnected through one or more sets of bus reconfiguration structures, and based on this, interconnect with other design interconnection information via buses. Correspondingly, each component and each level of interconnection information has one or more port information. By adding corresponding weak driver information to the port information, instead of generating the specific component information of each design interconnection information, the simulation and verification speed can be accelerated while ensuring the accuracy of simulation and verification, thereby improving the efficiency of chip design.
[0084] As an example, in step C10, configuring the corresponding bus reconfiguration structure includes:
[0085] Step C101: Define the name of the bus reconfiguration structure and select the corresponding bus reconfiguration structure type from the preset bus description reconfiguration library, and configure the attribute information of the corresponding interconnect bus reconfiguration structure for each initiating end.
[0086] It should be noted that among the two interconnected components, one is the initiator and the other is the receiver. The distinction between the initiator and the receiver is common knowledge in the art and will not be described in detail here. In this embodiment of the invention, only the attribute information of the interconnect bus reconfiguration structure needs to be stored at each initiator. The initiator and the receiver establish an interconnection relationship and share the attribute information of the corresponding interconnect bus reconfiguration structure.
[0087] As an example, the weak drive value corresponding to the port can be set directly based on the reset value corresponding to the signal in the IDF. In step C20, obtaining the weak drive information corresponding to each port information includes:
[0088] Step C201: Obtain the reset value corresponding to the output direction from the attribute information of the interconnect bus reconstruction structure configured at the initiating end, and use it as the weak drive information corresponding to the output port of the initiating end; obtain the reset value corresponding to the input direction, and use it as the weak drive information corresponding to the output port of the receiving end.
[0089] As an example, each DIY can also set an extended field (tied off). The weak drive value can be linearly set through the extended field, thus overriding the corresponding reset value. This allows scenarios where a reset value is typically required as the weak drive value to be set directly using step C201. For special scenarios requiring weak drive value settings, the weak drive value can be set through the extended field without changing the reset value, i.e., without changing the corresponding IDF. This satisfies the weak drive value acquisition needs in all scenarios while ensuring the universality of the IDF. Specifically, in step C20, generating the interconnection relationship between the corresponding bus reconfiguration structures also includes setting a custom weak drive value for each port in the preset extended field. Step C20 also involves obtaining the weak drive information corresponding to each port, including:
[0090] Step C202: Determine whether the corresponding custom weak drive value is set in the preset extended domain. If it exists, proceed to step C203.
[0091] Step C203: Obtain the corresponding custom weak drive value as the weak drive information corresponding to the port information. If it does not exist, obtain the reset value corresponding to the output direction from the attribute information of the interconnect bus reconstruction structure configured at the initiating end, and use it as the weak drive information corresponding to the output port at the initiating end. Obtain the reset value corresponding to the input direction, and use it as the weak drive information corresponding to the output port at the receiving end.
[0092] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.
[0093] Example 3 can generate a weak shell for chip design, which can accelerate the simulation and verification process and improve design efficiency.
[0094] Example 4
[0095] In the chip design process, the initial target design information is typically generated based on logical interconnects. However, during the establishment of physical interconnects, depending on factors such as the physical location of the layout and synthesis requirements, the reconfiguration of some components is often necessary. Existing EDA companies usually need to parse the lowest-level code of the design (such as Verilog) and deduce the reconfiguration design rules from the lowest-level code to design the reconfigured chip. This process is time-consuming and error-prone. Example 4 provides a chip design reconfiguration method applied to the chip logic interconnect to physical interconnect reconfiguration process, including:
[0096] Step D1: Obtain the original target design information {DIY1, DIY2, ... DIY} N IDF 01 IDF 02 ...IDF0R DIY n This represents the interconnect information of the nth design, where n ranges from 1 to N, and N is the number of the original target design levels. (IDF) 0r This represents the attribute information of the bus description reconfiguration structure corresponding to the r-th bus interconnect structure, where R is the total number of bus interconnects in the original target design information.
[0097] The original target design information is generated based on logical interconnections. When n=1, DIY n It is generated by interconnecting multiple basic unit information via a bus. When n>1, DIY n Composed of multiple DIY s Generated via bus interconnect definition, or by at least one DIY s It is generated by interconnecting at least one basic unit of information via a bus. Each DIY n The specific generation process can be achieved through steps A1-A3 in Example 1, and will not be repeated here. Furthermore, to accelerate the reassembly process, without requiring detailed composition information within the design hierarchy, corresponding empty design shells can be generated as corresponding DIY components according to steps B1-B2 in Example 2. n This will not be elaborated further here. If a weak drive is required, the corresponding weak drive shell can be generated according to steps C1-C2 in Example 3 as the corresponding DIY solution. n The configuration process for the attribute information of the bus description reconfiguration structure is also described in detail in Embodiment 1, and will not be repeated here.
[0098] Step D2: Obtain chip design reconfiguration information, parse the original target design information, determine the target reconfiguration starting level y based on the chip design reconfiguration information, 1≤y≤N, and parse the DIY... y DIY y+1 , ...DIY N Generate a database of information on units to be recombined;
[0099] The chip design reconfiguration information is generated based on physical interconnect relationships. Specifically, the reconfiguration information can be determined according to the physical location of the design layout, overall requirements, etc., and new constituent units can be introduced into the reconfiguration information. (DIY analysis step by step) y DIY y+1 , ...DIY N Generate information for all cells to be reassembled and add this information to the cell information database. It can be understood that the cell information to be reassembled is either basic cell information or DIY1, DIY2, ... DIY. y-1 During the reorganization process, the DIY1, DIY2, ... DIY in the target design information y-1 Keep it unchanged, DIYy DIY y+1 , ...DIY N The components are broken down and reassembled, and the interconnection relationship is kept unchanged after reassembly, thereby ensuring the accuracy of logical interconnection.
[0100] Step D3: Based on the chip design reconfiguration information, the reconfigurable cell information database, and the IDF... 01 IDF 02 ...IDF 0R DIY generated by layer-by-layer recombination y DIY y+1 ', ...DIY T ', among which, DIY u ' represents the u-th design interconnection information after reorganization, where u ranges from y to T, and T is the number of target design levels after reorganization. DIY y DIY y+1 ', ...DIY T 'Bus interconnection relationship of information to be reassembled in the middle and DIY y DIY y+1 , ...DIY N The bus interconnection relationship of the corresponding unit information to be reassembled remains unchanged;
[0101] Step D4: Generate recombination target design information {DIY1, DIY2, ... DIY} y-1 DIY y DIY y+1 ', ...DIY T ';IDF 01 IDF 02 ...IDF 0R}
[0102] As an example, step D3 includes:
[0103] Step D31: Initialize u = y;
[0104] Step D32: Based on the chip design reconfiguration information, obtain the cell information to be reconfigured required for reconfiguring the u-th design interconnection information from the cell information database, and define the bus interconnection according to the interconnection relationship of the cell information to be reconfigured required for the u-th design interconnection information in the original target design information, and from {IDF 01 IDF 02 ...IDF 0R The system retrieves the attribute information of the bus description reconfiguration structure corresponding to all initiators in the reconfiguration of the u-th design interconnection information, configures it into the corresponding initiator information, and generates the DIY reconfiguration of the u-th design interconnection information. u ', will DIY u'Add to the information database of the unit to be reassembled;'
[0105] It should be noted that details such as the bus interconnection definition, the attribute information of the bus description reconfiguration structure at the initiating end, and the attribute information of the bus description reconfiguration structure have been described in detail in Embodiment 1, and will not be repeated here.
[0106] Step D33: Determine if u is less than T. If it is less, set u = u + 1 and return to step D32.
[0107] New constituent units may be introduced during the reorganization process. If the design reorganization information includes information on newly added reorganization units {F1, F2, ... F...}, then... Z}, F z As an example, step D3 includes: (The information for the z-th newly added recombination unit is provided.)
[0108] Step D301: Set {F1, F2, ... F... Z Add the unit to be recombined information database and initialize u = y;
[0109] Step D32: Based on the chip design reconfiguration information, obtain the cell information to be reconfigured required for reconfiguring the u-th design interconnection information from the cell information database, and define the bus interconnection according to the interconnection relationship of the cell information to be reconfigured required for the u-th design interconnection information in the original target design information, and from {IDF 01 IDF 02 ...IDF 0R The system retrieves the attribute information of the bus description reconfiguration structure corresponding to all initiating ends in the reconfiguration design interconnection information, and configures it into the corresponding initiating end information. If new reconfiguration unit information is involved, the system adds the new generation unit information F according to the design reconfiguration information. z The corresponding interconnection relationship establishes a corresponding bus interconnection with the corresponding unit to be reassembled, and sets the corresponding bus description reconstruction structure attribute information IDF. z ', Generate and reorganize the u-th design interconnection information DIY u ', will DIY u 'Add to the information database of the unit to be reassembled;'
[0110] Step D33: Determine if u is less than T. If it is less, set u = u + 1 and return to step D32.
[0111] If the design reorganization information includes information on newly added reorganization units, then in step D4, the generated reorganization target design information is {DIY1, DIY2, ... DIY}. y-1 DIY y DIY y+1 ', ...DIY T ';IDF01 IDF 02 ...IDF 0R , IDF1', IDF2', ... IDF Z '}.
[0112] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.
[0113] In Example 4, the reassembly process does not require processing the underlying code; only the high-level reassembly rules need to be modified based on the reassembly information. This reduces the risk of errors and increases reassembly efficiency, thereby improving chip design efficiency.
[0114] It should be noted that all the above embodiments are applicable to the design process of all types of chips, and are especially applicable to agile chip design methods.
[0115] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0116] Those skilled in the art will understand that all instances of setting information on the initiating end mentioned throughout the text can be replaced with setting the corresponding information on the receiving end. That is, one can choose to set all information on the initiating end or all information on the receiving end, which will not be elaborated further here.
[0117] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being configured to perform the methods described in this invention.
[0118] This invention also provides a computer-readable storage medium, wherein the computer instructions are used to execute the methods described in this invention.
[0119] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A chip design reconfiguration method, applied to the reconfiguration process from chip logic interconnects to physical interconnects, characterized in that, include: Step D1: Obtain the original target design information {DIY1, DIY2, ... DIY} N ;IDF 01 IDF 02 ...IDF 0R DIY n This represents the interconnect information of the nth design, where n ranges from 1 to N, and N is the number of the original target design levels. (IDF) 0r This represents the attribute information of the bus description reconfiguration structure corresponding to the r-th bus interconnect structure. The value of r ranges from 1 to R, where R is the total number of bus interconnects in the original target design information. Step D2: Obtain chip design reconfiguration information, parse the original target design information, determine the target reconfiguration starting level y based on the chip design reconfiguration information, 1≤y≤N, and parse the DIY... y DIY y+1 , ...DIY N Generate a database of information on units to be recombined; Step D3: Based on the chip design reconfiguration information, the reconfigurable cell information database, and the IDF... 01 IDF 02 ...IDF 0R DIY generated by layer-by-layer recombination y DIY y+1 ', ...DIY T ', among which, DIY u ' represents the u-th design interconnection information after reorganization, where u ranges from y to T, and T is the number of target design levels after reorganization. DIY y DIY y+1 ', ...DIY T 'Bus interconnection relationship of information to be reassembled in the middle and DIY y DIY y+1 , ...DIY N The bus interconnection relationship of the corresponding unit information to be reassembled remains unchanged; Step D4: Generate recombination target design information {DIY1, DIY2, ... DIY} y-1 DIY y ' , DIY y+1 ', ...DIY T ';IDF 01 IDF 02 ...IDF 0R } 2. The method according to claim 1, characterized in that, When n=1, DIY n It is generated by interconnecting multiple basic unit information via a bus. When n>1, DIY n Composed of multiple DIY s Generated via bus interconnect definition, or by at least one DIY s The information of at least one basic unit is defined and generated through bus interconnection. The value of s ranges from 1 to N-1, and s <n。 3. The method according to claim 1, characterized in that, The original target design information is generated based on logical interconnection relationships, and the chip design reconfiguration information is generated based on physical interconnection relationships.
4. The method according to claim 1, characterized in that, Step D3 includes: Step D31: Initialize u=y; Step D32: Based on the chip design reconfiguration information, obtain the cell information to be reconfigured required for reconfiguring the u-th design interconnection information from the cell information database, and define the bus interconnection according to the interconnection relationship of the cell information to be reconfigured required for the u-th design interconnection information in the original target design information, and from {IDF 01 IDF 02 ...IDF 0R The system retrieves the attribute information of the bus description reconfiguration structure corresponding to all initiators in the reconfiguration of the u-th design interconnection information, configures it into the corresponding initiator information, and generates the DIY reconfiguration of the u-th design interconnection information. u ', will DIY u 'Add to the information database of the unit to be reassembled;' Step D33: Determine if u is less than T. If it is less, set u = u + 1 and return to step D32.
5. The method according to claim 1, characterized in that, If the design reorganization information includes information on newly added reorganization units {F1, F2, ... F} Z }, F z This indicates the information of the z-th newly added recombination unit. Step D3 includes: Step D301: Set {F1, F2, ... F... Z Add the unit to be recombined information database and initialize u=y; Step D32: Based on the chip design reconfiguration information, obtain the cell information to be reconfigured required for reconfiguring the u-th design interconnection information from the cell information database, and define the bus interconnection according to the interconnection relationship of the cell information to be reconfigured required for the u-th design interconnection information in the original target design information, and from {IDF 01 IDF 02 ...IDF 0R The system retrieves the attribute information of the bus description reconfiguration structure corresponding to all initiating ends in the reconfiguration design interconnection information, and configures it into the corresponding initiating end information. If new reconfiguration unit information is involved, the system adds the new generation unit information F according to the design reconfiguration information. z The corresponding interconnection relationship establishes a corresponding bus interconnection with the corresponding unit to be reassembled, and sets the corresponding bus description reconstruction structure attribute information IDF. z ', Generate and reorganize the u-th design interconnection information DIY u ', will DIY u 'Add to the information database of the unit to be reassembled;' Step D33: Determine if u is less than T. If it is less, set u = u + 1 and return to step D32.
6. The method according to claim 5, characterized in that, If the design reorganization information includes information on newly added reorganization units, then in step D4, the generated reorganization target design information is {DIY1, DIY2, ... DIY}. y-1 DIY y ' , DIY y+1 ', ...DIY T ';IDF 01 IDF 02 ...IDF 0R , IDF1', IDF2', ... IDF Z '}.
7. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in any one of claims 1-6.
8. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-6.