A method of loading a circuit with a run configuration

Abstract

The present application relates to the technical field of hardware design, and provides a circuit loading method for running configuration, which comprises the following steps: defining a configuration file, wherein the format of the configuration file is determined based on a configuration circuit of an ASIC chip, and the content of the configuration file is determined based on a functional circuit of the chip; the configuration circuit reads the configuration file from a FLASH, and acquires operation control information in the configuration file, wherein the operation control information comprises one or more; the configuration circuit performs integrity check on the operation control information, and if the check is passed, performs a configuration loading operation according to a loading mode in the operation control information, otherwise, the configuration circuit indicates a loading error. The present application can complete the loading of configuration parameters during power-on initialization in the circuit of an ASIC, and realizes a flexible circuit loading mode.

Description

Technical Field

[0001] This invention relates to the field of hardware design technology, and more specifically to a method for loading circuit configurations. Background Technology

[0002] When an FPGA or ASIC chip (collectively referred to as an ASIC) that performs a specific function is powered on and initialized, it generally needs to be given its operating parameters or configuration. Normally, this process is handled by software running on the processor, which reads the configuration from non-volatile memory and loads the configuration parameters, making it simple and flexible. However, in certain scenarios, there are strict requirements on the time it takes for the ASIC to reach its operating state, and it is desirable for the ASIC to continue operating normally even in the event of a processor failure. Therefore, existing processor software loading methods require modifications to the circuitry that performs the configuration loading when the ASIC's configuration registers are changed, making ASIC configuration relatively complex. Summary of the Invention

[0003] In view of this, the present invention provides a circuit loading method for running configuration to solve the technical problem in the prior art that when the configuration register of an ASIC is modified, the circuit implementation for executing configuration loading needs to be changed, making ASIC configuration relatively complex.

[0004] The circuit loading method for operation configuration provided by the present invention includes:

[0005] Define a configuration file, the format of which is determined based on the configuration circuit of the ASIC chip, and the content of which is determined based on the functional circuit of the chip;

[0006] The configuration circuit reads the configuration file from the FLASH and obtains operation control information from the configuration file, the operation control information including one or more.

[0007] The configuration circuit performs integrity verification on the operation control information. If the verification is successful, the configuration loading operation is executed according to the loading mode in the operation control information; otherwise, the configuration circuit indicates a loading error.

[0008] Furthermore, the operation control information includes the following fields: ASIC start address AADDR; FLASH start address FADDR; operation type OP_TYPE, which includes opcode OP_CODE, fixed ASIC start address OP_AA_FIXED, fixed FLASH start address OP_FA_FIXED, number of parameter items OP_ITEMS, selection bits OP_SEL_BITS, shift bits OP_MOV_BITS; operation length OP_LEN; loop count OP_TIMES; content check CT_CHK; operation check OP_CHK.

[0009] Furthermore, the configuration circuit performs a configuration loading operation, including:

[0010] Step 1: Set the read base address FA = FADDR and the write base address AA = AADDR;

[0011] Step 2: If OP_ITEMS = 1, read 1 configuration parameter from the address (ADDR&MSK)|(FA&~MSK) in FLASH; if OP_ITEMS > 1, read OP_ITEMS+1 configuration parameters sequentially starting from the address (ADDR&MSK)|(FA&~MSK) in FLASH, and use the last item to verify the previous OP_ITEMS configuration parameters. If the verification is successful, continue to execute the configuration loading operation; otherwise, the configuration circuit indicates a loading error.

[0012] Step 3: Write the OP_ITEMS configuration parameters read in Step 2 into the ASIC address space starting at AA, and increase the values ​​of the read base address FA and the write base address AA by POWER(2,OP_SEL_BITS)*4;

[0013] Step 4: Repeat steps 2 and 3 until the number of repetitions j equals OP_LEN, and read a total of OP_LEN configuration parameters; when OP_ITEMS equals 1, use CT_CHK to verify OP_LEN configuration parameters. If the verification passes, continue to execute the configuration loading operation; otherwise, the configuration circuit indicates a loading error.

[0014] Step 5: If OP_FA_FIXED is 1, set the read base address FA = FADDR; if OP_AA_FIXED is 1, set the write base address AA = AADDR; repeat steps 2, 3, and 4 until the number of repetitions k equals OP_TIMES, and complete the configuration loading operation.

[0015] Furthermore, in step three, the configuration parameters of the FLASH address FA+x are written to the corresponding ASIC address (AA+F(x)); F(x) indicates that the bits [OP_SEL_BITS+1:2] of x are shifted to the left by OP_MOV_BITS. OP_ITEMS+1<=POWER(2, OP_SEL_BITS).

[0016] Furthermore, the configuration parameters, FLASH address space, and ASIC address space are all in 4-byte independent units.

[0017] Furthermore, when OP_CODE indicates clear mode, the configuration circuit uses the FADDR value instead of the data read from FLASH to perform the configuration loading operation.

[0018] Furthermore, the configuration file includes multiple configuration files, the space occupied by a single configuration file is greater than or equal to the file size of the single configuration file, and the space occupied is equal to a power of 2, where n is the smallest integer; a single configuration file includes a configuration header and multiple configuration areas, the multiple configuration areas are stored sequentially or in parameter grouping order; the configuration header includes a configuration table identifier, ASIC hardware circuit version, configuration table version, configuration table production time, space mask, number of operations, and header checksum.

[0019] Furthermore, the configuration circuit first verifies the configuration header, and after the verification is successful, reads the operation control information according to the number of operations.

[0020] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted by the present invention include: the present invention adopts a relatively flexible circuit loading method, which can realize the loading of configuration parameters during power-on initialization in the ASIC circuit, and supports loading modes such as clearing, sequential loading, cyclic sequential loading, and cyclic cross loading. Even if the configuration register of the ASIC is modified, only the corresponding configuration file needs to be modified, without modifying the circuit implementation that performs configuration loading. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the configuration file format provided in an embodiment of the present invention;

[0023] Figure 2This is a schematic diagram of the group loading address translation mechanism provided in an embodiment of the present invention. Detailed Implementation

[0024] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] This invention employs a relatively flexible circuit loading method, which can realize the loading of configuration parameters during power-on initialization in ASIC circuits. It supports loading modes such as clearing, sequential loading, cyclic sequential loading, and cyclic cross loading. Even if the configuration register of the ASIC is modified, only the corresponding configuration file needs to be modified, without modifying the circuit implementation that performs the configuration loading.

[0027] The circuit loading method for operation configuration provided by the present invention specifically includes:

[0028] Step S100: Define a configuration file. The format of the configuration file is determined based on the configuration circuit of the ASIC chip, and the content of the configuration file is determined based on the functional circuit of the chip.

[0029] Specifically, the ASIC chip is either an FPGA or an ASIC chip. The configuration circuit within the ASIC chip reads the configuration file (containing the space mask MSK) from a specific address ADDR in the FLASH memory according to an indication signal. The space mask is used to protect the configuration parameters so that they can only be read from this configuration file. The configuration file format is as follows: Figure 1 As shown.

[0030] Step S200: The configuration circuit reads the configuration file from the FLASH and obtains operation control information from the configuration file, wherein the operation control information includes one or more.

[0031] Furthermore, the configuration circuit first verifies the configuration header, and after the verification is successful, reads the operation control information according to the number of operations.

[0032] Furthermore, the operation control information includes the following fields: ASIC start address AADDR; FLASH start address FADDR; operation type OP_TYPE, which includes opcode OP_CODE, fixed ASIC start address OP_AA_FIXED, fixed FLASH start address OP_FA_FIXED, number of parameter items OP_ITEMS, selection bits OP_SEL_BITS, shift bits OP_MOV_BITS; operation length OP_LEN; loop count OP_TIMES; content check CT_CHK; operation check OP_CHK.

[0033] Step S300: The configuration circuit performs an integrity check on the operation control information. If the check passes, the configuration loading operation is executed according to the loading mode in the operation control information; otherwise, the configuration circuit indicates a loading error.

[0034] Specifically, the configuration circuit reads a single operation control message, uses OP_CHK to verify the complete control information, and can only execute it after the verification is successful; otherwise, it indicates a loading error.

[0035] Furthermore, when OP_CODE represents the loading mode (including sequential loading, cyclic sequential loading, and cyclic interleaved loading), the configuration circuit performs a configuration loading operation, such as... Figure 2 As shown, it includes:

[0036] Step 1: Initialize, set the read base address FA = FADDR, and the write base address AA = AADDR;

[0037] Step 2: If OP_ITEMS = 1, read 1 configuration parameter from the address (ADDR&MSK)|(FA&~MSK) in FLASH; if OP_ITEMS > 1, read OP_ITEMS+1 configuration parameters sequentially starting from the address (ADDR&MSK)|(FA&~MSK) in FLASH, and use the last item to verify the previous OP_ITEMS configuration parameters. If the verification is successful, continue to execute the configuration loading operation; otherwise, the configuration circuit indicates a loading error.

[0038] Step 3: Write the OP_ITEMS configuration parameters read in Step 2 into the ASIC address space starting at AA, and increase the values ​​of the read base address FA and the write base address AA by POWER(2,OP_SEL_BITS)*4;

[0039] Furthermore, in step three, the configuration parameters of the FLASH address FA+x are written to the corresponding ASIC address (AA+F(x)); F(x) indicates that the bits [OP_SEL_BITS+1:2] of x are shifted to the left by OP_MOV_BITS. OP_ITEMS+1<=POWER(2, OP_SEL_BITS).

[0040] Step 4: Repeat steps 2 and 3 until the number of repetitions j equals OP_LEN, and read a total of OP_LEN configuration parameters; when OP_ITEMS equals 1, use CT_CHK to verify OP_LEN configuration parameters. If the verification passes, continue to execute the configuration loading operation; otherwise, the configuration circuit indicates a loading error.

[0041] Step 5: If OP_FA_FIXED is 1, set the read base address FA = FADDR; if OP_AA_FIXED is 1, set the write base address AA = AADDR; repeat steps 2, 3, and 4 until the number of repetitions k equals OP_TIMES, and complete the configuration loading operation.

[0042] Furthermore, such as Figure 2 As shown, the configuration parameters, FLASH address space and ASIC address space are all in 4-byte independent units, but the addresses are still byte-addressed.

[0043] Furthermore, when OP_CODE indicates clear mode, the configuration circuit uses the FADDR value instead of the data read from FLASH to perform the configuration loading operation.

[0044] Furthermore, the configuration file includes multiple configuration files, the space occupied by a single configuration file is greater than or equal to the file size of the single configuration file, and the space occupied is equal to a power of 2, where n is the smallest integer; a single configuration file includes a configuration header and multiple configuration areas, the multiple configuration areas are stored sequentially or in parameter grouping order; the configuration header includes a configuration table identifier, ASIC hardware circuit version, configuration table version, configuration table production time, space mask, number of operations, and header checksum.

[0045] The present invention achieves the following technical effects through the above embodiments:

[0046] This invention implements the loading of configuration parameters during power-on initialization in ASIC circuits, supporting loading modes such as clearing, sequential loading, cyclic sequential loading, and cyclic cross loading. Even if the ASIC's configuration registers are modified, only the corresponding configuration file needs to be modified, without changing the circuit implementation that performs the configuration loading, thus achieving a relatively flexible circuit loading method.

[0047] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for loading a circuit configuration, characterized in that, The method includes: Define a configuration file, the format of which is determined based on the configuration circuit of the ASIC chip, and the content of which is determined based on the functional circuit of the chip; The configuration circuit reads the configuration file from the FLASH and obtains operation control information from the configuration file, the operation control information including one or more. The configuration circuit performs integrity verification on the operation control information. If the verification is successful, the configuration loading operation is executed according to the loading mode in the operation control information; otherwise, the configuration circuit indicates a loading error. Operation control information includes the following fields: ASIC start address AADDR; FLASH start address FADDR; operation type OP_TYPE, which includes opcode OP_CODE, fixed ASIC start address OP_AA_FIXED, fixed FLASH start address OP_FA_FIXED, number of parameters OP_ITEMS, selection bits OP_SEL_BITS, and shift bits OP_MOV_BITS; operation length OP_LEN; loop count OP_TIMES; content check CT_CHK; and operation check OP_CHK. The configuration circuit performs a configuration loading operation, including: Step 1: Set the read base address FA=FADDR and the write base address AA=AADDR; Step 2: If OP_ITEMS=1, read one configuration parameter from the address (ADDR&MSK)|(FA&~MSK) in FLASH; if OP_ITEMS>1, read OP_ITEMS+1 configuration parameters sequentially starting from the address (ADDR&MSK)|(FA&~MSK) in FLASH, and use the last item to verify the previous OP_ITEMS configuration parameters. If the verification is successful, continue to execute the configuration loading operation; otherwise, the configuration circuit indicates a loading error. Step 3: Write the configuration parameters of the first OP_ITEMS item read in Step 2 into the ASIC address space starting at AA, and increment the values ​​of the read base address FA and the write base address AA by POWER(2,OP_SEL_BITS). 4; Step 4: Repeat steps 2 and 3 until the number of repetitions j equals OP_LEN, and read a total of OP_LEN configuration parameters; when OP_ITEMS equals 1, use CT_CHK to verify OP_LEN configuration parameters. If the verification passes, continue to execute the configuration loading operation; otherwise, the configuration circuit indicates a loading error. Step 5: If OP_FA_FIXED is 1, set the read base address FA=FADDR; if OP_AA_FIXED is 1, set the write base address AA=AADDR; repeat steps 2, 3, and 4 until the number of repetitions k equals OP_TIMES, and complete the configuration loading operation.

2. The circuit loading method for operation configuration according to claim 1, characterized in that, In step three, the configuration parameters of FLASH address FA+x are written to ASIC address (AA+F(x)); F(x) means shifting the bits [OP_SEL_BITS+1:2] of x to the left by OP_MOV_BITS, OP_ITEMS+1<=POWER(2, OP_SEL_BITS).

3. The circuit loading method for operation configuration according to claim 2, characterized in that, The configuration parameters, FLASH address space, and ASIC address space are all defined as 4-byte independent units.

4. The circuit loading method for operation configuration according to claim 3, characterized in that, When OP_CODE indicates clear mode, the configuration circuit uses the FADDR value instead of the data read from FLASH to perform the configuration loading operation.

5. The circuit loading method for operation configuration according to claim 1, characterized in that, The configuration file includes multiple configuration files, and the space occupied by a single configuration file is greater than or equal to the file size of the single configuration file, and the space occupied is equal to a power of 2, where n is the smallest integer. A single configuration file includes a configuration header and multiple configuration areas, and the multiple configuration areas are stored sequentially or in parameter grouping order. The configuration header includes a configuration table identifier, ASIC hardware circuit version, configuration table version, configuration table production time, space mask, number of operations, and header check value.

6. The circuit loading method for operation configuration according to claim 5, characterized in that, The configuration circuit first verifies the configuration header, and after the verification is successful, reads the operation control information according to the number of operations.

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