Image processing circuit and image processing method

Abstract

This invention discloses an image processing circuit and an image processing method. The image processing method is applied to an image processing circuit including a first application circuit and a second application circuit, the image processing circuit being coupled to a memory. The method includes: the first application circuit reading a first image from the memory; the first application circuit processing the first image to generate a portion of a second image, and generating progress information corresponding to the portion; the first application circuit storing the portion of the second image into the memory; the first application circuit sending the progress information; the second application circuit receiving the progress information; the second application circuit reading the portion of the second image from the memory according to the progress information; and the second application circuit processing the portion of the second image.

Description

Technical Field

[0001] This application relates to the field of image processing technology, specifically to image processing circuits and image processing methods. Background Technology

[0002] Please see Figure 1 , Figure 1 This is a functional block diagram of an existing electronic device. Electronic device 100 includes application circuit 110, memory 120, and application circuit 130. Application circuit 110 and application circuit 130 are coupled to memory 120.

[0003] Application circuit 110 includes a Direct Memory Access (DMA) circuit (read) 112, a processing circuit 114, and a DMA circuit (write) 116. The DMA circuit (read) 112, controlled by the processing circuit 114, reads image IMG0 from memory 120. The processing circuit 114 processes image IMG0 to generate image IMG1 and controls the DMA circuit (write) 116 to write image IMG1 into memory 120.

[0004] Application circuit 130 includes direct memory access circuit (read) 132, processing circuit 134, and direct memory access circuit (write) 136. Direct memory access circuit (read) 132, controlled by processing circuit 134, reads image IMG1 from memory 120. Processing circuit 134 processes image IMG1 to generate image IMG2 and controls direct memory access circuit (write) 136 to write image IMG2 into memory 120.

[0005] Please see Figure 2 , Figure 2 This is the timing diagram of existing electronic device 100. Please also refer to... Figure 1 and Figure 2 Here, it is assumed that application circuits 110 and 130 share the first memory block MB0 and the second memory block MB1 of memory 120. Tasks TSK0 and TSK1 are tasks of application circuits 110 and 130, respectively, and are generated by the computing unit (not shown in the figure) of electronic device 100. At time point T0, the first task TSK0-0 of application circuit 110 and the first task TSK1-0 of application circuit 130 are generated, and then application circuit 110 begins to process task TSK0-0 (step S215, writing the generated image IMG1 into the first memory block MB0), but at this time application circuit 130 has not yet started to process task TSK1-0.

[0006] Application circuit 110 completes processing of image IMG0 at time T1 (i.e., has generated a complete image IMG1). When task TSK0-0 learns that application circuit 110 has completed processing of image IMG0 (step S220), the computing circuit of electronic device 100 terminates task TSK0-0 and wakes up task TSK1-0 (step S225, time T2). After task TSK1-0 is woken up, task TSK1-0 provides image IMG1 in the first memory block MB0 to application circuit 130, and application circuit 130 begins processing task TSK1-0 (step S230, time T3). It should be noted that task TSK1-0 is generated at time T0, but it is not processed until time T3. This waiting time (approximately equal to the duration of task TSK0-0, i.e., approximately equal to the time it takes for application circuit 110 to process one image) is the hardware gap HWG. Application circuit 130 is in an idle state during the hardware gap HWG, resulting in a waste of system resources.

[0007] Between time points T3 and T4, tasks TSK0-1 and TSK1-0 are essentially in parallel (i.e., application circuit 110 writes the next image IMG1 to the second memory block MB1, and application circuit 130 writes image IMG2 to the first memory block MB0). However, because application circuits 110 and 130 have different processing speeds (assuming application circuit 110's processing speed is greater than application circuit 130's), although task TSK0-2 is ready at time point T4, it cannot start processing immediately (because application circuit 130 is still using the first memory block MB0 at this time). Task TSK0-2 must wait until task TSK1-0 completes (i.e., after the first memory block MB0 is released, approximately at time point T5) before it can begin processing. This waiting time (approximately equal to T5-T4) is the software gap SWG. Application circuit 110 is idle during the software gap SWG, resulting in a waste of system resources.

[0008] The waste of system resources caused by hardware gaps (HWG) and software gaps (SWG) can lead to a decrease in the performance of electronic device 100. Summary of the Invention

[0009] In view of the shortcomings of the prior art, one object of the present invention is to provide an image processing circuit and an image processing method to improve the shortcomings of the prior art.

[0010] An embodiment of the present invention provides an image processing circuit coupled to a memory, including a first application circuit and a second application circuit. The first application circuit includes a first memory access circuit, a first processing circuit, a second memory access circuit, and a notification sending circuit. The first memory access circuit is used to read a first image from the memory. The first processing circuit, coupled to the first memory access circuit, is used to process the first image to generate a portion of a second image and generate progress information corresponding to the portion. The second memory access circuit, coupled to the first processing circuit, is used to store the portion of the second image into the memory. The notification sending circuit, coupled to the first processing circuit, is used to send the progress information. The second application circuit includes a notification receiving circuit, a third memory access circuit, and a second processing circuit. The notification receiving circuit, coupled to the notification sending circuit, is used to receive the progress information. The third memory access circuit, coupled to the notification receiving circuit, is used to read the portion of the second image from the memory according to the progress information. The second processing circuit, coupled to the third memory access circuit, is used to process the portion of the second image.

[0011] Another embodiment of the present invention provides an image processing method applied to an image processing circuit including a first application circuit and a second application circuit, the image processing circuit being coupled to a memory, the method comprising: the first application circuit reading a first image from the memory; the first application circuit processing the first image to generate a portion of a second image, and generating progress information corresponding to the portion; the first application circuit storing the portion of the second image into the memory; the first application circuit sending the progress information; the second application circuit receiving the progress information; the second application circuit reading the portion of the second image from the memory according to the progress information; and the second application circuit processing the portion of the second image.

[0012] The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art, and therefore the present invention can improve the performance of electronic devices compared with the prior art.

[0013] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a functional block diagram of an existing electronic device;

[0015] Figure 2 It is a timing diagram of an existing electronic device;

[0016] Figure 3 This is a functional block diagram of an embodiment of the electronic device of the present invention;

[0017] Figure 4 This is a flowchart of an embodiment of the image processing method of the present invention;

[0018] Figure 5 This is a schematic diagram of the image generated by the application circuit of this invention;

[0019] Figure 6 This is a functional block diagram of an embodiment of the notification sending circuit and notification receiving circuit of the present invention;

[0020] Figure 7 This is a timing diagram of the electronic device of the present invention;

[0021] Figure 8 This is a functional block diagram of another embodiment of the electronic device of the present invention;

[0022] Figure 9 This is a schematic diagram of the image signal processing circuit of the present invention generating an image;

[0023] Figure 10 This is a schematic diagram of another embodiment of the image signal processing circuit of the present invention generating an image.

[0024] Figure label:

[0025] 100, 300, 800: Electronic devices;

[0026] 110, 130, 310, 330: Application circuits;

[0027] 112, 132: Direct Memory Access Circuit (Read);

[0028] 114, 134, 314, 334: Processing circuits;

[0029] 116, 136: Direct Memory Access Circuit (Write);

[0030] 120, 302, 802: Memory;

[0031] IMG0, IMG1, IMG2, IG0-1, IG0-2, IG0-3, IG1-1, IG1-2, IG1-3, IG2-1, IG2-2, IG2-3: Images;

[0032] HWG: Hardware Gauge;

[0033] MB0: First memory block;

[0034] MB1: Second memory block;

[0035] S215, S220, S225, S230, S410, S420, S430, S440, S450, S460, S470, S710, S715, S720, S725, S730, S735, S740, S745, S750: Steps;

[0036] SWG: Software Gaps;

[0037] T0, T1, T2, T3, T4, T5, T6: Time points;

[0038] TSK0, TSK0-0, TSK0-1, TSK0-2, TSK1, TSK1-0, TSK1-1: Task;

[0039] 301, 801: Image processing circuits;

[0040] 311: Notification sending circuit;

[0041] 312, 332: Memory access circuit (read);

[0042] 316, 336: Memory access circuit (write);

[0043] 331: Notification receiving circuit;

[0044] IG0, IG1, IG2: Image groups;

[0045] PI, PI-1, PI-2: Progress information;

[0046] DP: Newly completed portion;

[0047] Tp1, Tp2: Time duration;

[0048] 612: Information recorder;

[0049] 614: Event sending circuit;

[0050] 632: Information Decoder;

[0051] 634: Event receiving circuit;

[0052] TR: Trigger signal;

[0053] 335: Calculation module;

[0054] 810: Image signal processing circuit;

[0055] 830: Lens distortion correction circuit;

[0056] ALG: Correction Algorithm;

[0057] MAP1, MAP2: Correction image maps;

[0058] TH1, TH2, TH1-1, TH1-2, TH1-3, TH1-4: Threshold values;

[0059] A1, A2, A3, A4: Correction areas. Detailed Implementation

[0060] The technical terms used in the following description are based on the common terminology of this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0061] The present invention discloses image processing circuits and image processing methods. Since some components of the image processing circuit of the present invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention. Furthermore, some or all of the processes of the image processing method of the present invention may be in the form of software and / or firmware, and can be executed by the image processing circuit of the present invention or its equivalent device. Without affecting the full disclosure and implementability of the method invention, the following description of the method invention will focus on the steps rather than the hardware.

[0062] Please see Figure 3 , Figure 3 This is a functional block diagram of an embodiment of the electronic device of the present invention. The electronic device 300 includes an image processing circuit 301 and a memory 302. The image processing circuit 301 includes an application circuit 310 and an application circuit 330. The application circuit 310 and the application circuit 330 are coupled to the memory 302.

[0063] Application circuit 310 includes notification sending circuit 311, memory access (e.g., direct memory access) circuit (read) 312, processing circuit 314, and memory access circuit (write) 316.

[0064] The application circuit 330 includes a notification receiving circuit 331, a memory access circuit (read) 332, a processing circuit 334, and a memory access circuit (write) 336.

[0065] Memory 302 stores image groups IG0, IG1, and IG2, each image group comprising multiple images (each image can be a frame). Image group IG0 is generated by the front-end circuitry (not shown) of image processing circuitry 301. In the k-th operation round, application circuitry 310 processes one image IG0-1 from image group IG0 to generate one image IG1-1 from image group IG1, and application circuitry 330 processes the image IG1-1 from image group IG1 to generate one image IG2-1 from image group IG2. Similarly, in the k+1 (k+2)-th operation round, application circuitry 310 processes image IG0-2 (or image IG0-3) to generate image IG1-2 (or image IG1-3), and application circuitry 330 processes image IG1-2 (or image IG1-3) to generate image IG2-2 (or image IG2-3).

[0066] In some embodiments, the application circuit 310 outputs results in units of lines, for example, outputting one line of image IG1-1 each time.

[0067] Please see Figure 4 , Figure 4 This is a flowchart of an embodiment of the image processing method of the present invention. Please refer to the following description as well. Figure 3 and Figure 4 In some embodiments, Figure 4 The process can be executed under the control of the computing unit (e.g., central processing unit or microcontroller, not shown) of the electronic device 300, which controls the application circuits 310 and 330 by configuring the registers of the application circuits 310 and 330. Figure 4 The process includes the following steps.

[0068] Step S410: Control application circuit 310 (more specifically, memory access circuit (read) 312) to read image IG0-1 from memory 302.

[0069] Step S420: The control application circuit 310 (more specifically, the processing circuit 314) processes image IG0-1 to produce a portion of image IG1-1, and generates progress information PI corresponding to said portion of image IG1-1. See also... Figure 5 , Figure 5This is a schematic diagram of the application circuit 310 generating image IG1-1. Image IG1-1 includes N rows of pixels. At time point T0, the application circuit 310 begins processing image IG0-1 (at this time, no row of pixels in image IG1-1 has been generated). At time point T1, the application circuit 310 has generated M1 rows in image IG1-1 (i.e., the newly completed portion DP in image IG1-1 includes the M1 rows of pixels, where M1 is less than N), and the progress information PI-1 generated by the processing circuit 314 at time point T1 includes M1 (i.e., the last row of pixels in the newly completed portion DP) or information equivalent to M1 (e.g., the number of pixels included in the newly completed portion DP). In some embodiments, the processing circuit 314 continuously generates image IG1-1 and synchronously updates the progress information PI.

[0070] Step S430: Control application circuit 310 (more specifically, memory access circuit (write) 316) to store the newly completed portion DP of image IG1-1 into memory 302.

[0071] Step S440: Control application circuit 310 (more specifically, notification sending circuit 311) sends progress information PI to application circuit 330.

[0072] Step S450: Control application circuit 330 (more specifically, notification receiving circuit 331) to receive progress information PI.

[0073] Step S460: The control application circuit 330 (more specifically, the memory access circuit (read) 332) reads the newly completed portion DP of image IG1-1 from memory 302 according to the progress information PI. For example (see...) Figure 5 If the memory access circuit (read) 332 reads M1 rows of pixels (i.e., the newly completed portion DP) from memory 302 at time T1 based on the current progress information PI (i.e., progress information PI-1), then at time T2, the memory access circuit (read) 332 reads M2-M1 rows of pixels from memory 302 based on the current progress information PI (i.e., progress information PI-2, which includes M2) and the current processing progress of application circuit 330 (i.e., row M1, since the memory access circuit (read) 332 has already read row M1 of image IG1-1 at time T1). In other words, the notification receiving circuit 331 can compare the progress information PI with the current processing progress of application circuit 330, and then control the memory access circuit (read) 332 to read the newly completed portion DP of image IG1-1 based on the comparison result.

[0074] Step S470: Control application circuit 330 (more specifically, processing circuit 334) to process the newly completed portion DP of image IG1-1.

[0075] Electronic device 300 repeats execution Figure 4 The process. More specifically, application circuit 310, on the one hand, generates more newly completed portions of the DP in image IG1-1 (e.g., see...). Figure 5 The completed portion of image IG1-1 changes from row M1 at time point T1 to row M2 at time point T2 (M2>M1) and updates the progress information PI (e.g., updates the progress information PI from PI-1 to PI-2) (corresponding to steps S410 to S440); on the other hand, the application circuit 330 obtains more pixels of image IG1-1 based on the progress information PI, and processes the newly completed portion DP of image IG1-1 to generate image IG2-1 (corresponding to steps S450 to S470).

[0076] Please see Figure 6 , Figure 6 This is a functional block diagram of an embodiment of the notification sending circuit 311 and notification receiving circuit 331 of the present invention. The notification sending circuit 311 includes an information recorder 612 and an event sending circuit 614. The notification receiving circuit 331 includes an information decoder 632 and an event receiving circuit 634. The information recorder 612 is coupled or electrically connected to the processing circuit 314, the event sending circuit 614, and the information decoder 632. The information decoder 632 is coupled or electrically connected to the information recorder 612, the event receiving circuit 634, and the memory access circuit (read) 332. The event sending circuit 614 is coupled or electrically connected to the event receiving circuit 634.

[0077] Processing circuit 314 continuously updates progress information PI and provides it to information recorder 612. When a preset condition is met, information recorder 612 controls event sending circuit 614 to transmit trigger signal TR to event receiving circuit 634. In response to the trigger signal TR, event receiving circuit 634 controls information decoder 632 to decode progress information PI, and information decoder 632 controls memory access circuit (read) 332 to read newly completed portion DP of image IG1-1 from memory 302 based on progress information PI and the current processing progress of application circuit 330 (i.e., the number of rows of image IG1-1 processed by processing circuit 334). Because memory access circuit (read) 332 is controlled by information decoder 632, information decoder 632 knows the current progress of application circuit 330. For example, see [link to example]. Figure 5 If the current processing progress of application circuit 330 is line M1, and information decoder 632 knows from progress information PI that the current processing progress of application circuit 310 is line M2, then information decoder 632 controls memory access circuit (read) 332 to read more pixels of image IG1-1 (e.g., newly completed part of DP) based on the difference between the current processing progress of application circuit 310 and application circuit 330 (i.e., M2-M1 line pixels).

[0078] The aforementioned preset conditions can be: (1) when the processing circuit 314 generates a new image IG1-1 with a preset number of rows; or (2) when a predetermined time has elapsed. The following are related to... Figure 5 The above-mentioned preset conditions are explained, wherein it is assumed that the notification sending circuit 311 sends progress information PI-1 and progress information PI-2 at time point T1 and time point T2 respectively, and the notification sending circuit 311 does not send any other progress information PI between time point T0 and time point T1 and between time point T1 and time point T2.

[0079] Regarding the preset condition (1), whenever the processing circuit 314 generates an image IG1-1 with a preset number of rows, it notifies the sending circuit 311 to send progress information PI. That is to say, Figure 5 In this context, M2 = 2 * M1 (i.e., the preset number of rows is M1). At this time, the time length Tp1 may or may not be equal to the time length Tp2.

[0080] Regarding the preset condition (2), the processing circuit 314 generates progress information PI at predetermined intervals. That is to say, Figure 5 The time length Tp1 is equal to the time length Tp2 (i.e., the predetermined time). At this time, M2 may or may not be equal to 2*M1.

[0081] Please continue reading. Figure 5 and Figure 6 In some embodiments, the information decoder 632 only controls the memory access circuit (read) 332 to read more pixels from image IG1-1 for processing by the processing circuit 334 when the difference in current progress (i.e., the number of pixels in rows M2-M1) is greater than a threshold value. The threshold value will be illustrated below.

[0082] In some embodiments, the trigger signal TR can be a hardware interrupt, and the hardware interrupt does not need to be processed by the interrupt management circuit (not shown in the figure) of the image processing circuit 301, so as to speed up the circuit's response speed and reduce the complexity of the interrupt management circuit.

[0083] Please see Figure 7 , Figure 7 This is a timing diagram of the electronic device 300 of the present invention. Please refer to the following description as well. Figure 3 and Figure 7 Here it is assumed that application circuit 310 and application circuit 330 share the first memory block MB0 and the second memory block MB1 (not shown in the figure) of memory 302. Task TSK0 (including multiple subtasks TSK0-0, TSK0-1, TSK0-2, ...) and task TSK1 (including multiple subtasks TSK1-0, TSK1-1, ...) are generated by the computing unit of electronic device 300. Figure 7It includes the following steps.

[0084] Step S710: Application circuit 310 begins processing task TSK0-0 at time point T0. This step corresponds to... Figure 5 The time point T0 (the newly completed part of DP is zero or empty).

[0085] Step S715: Processing circuit 314 begins to generate a portion of image IG1-1 (stored in the first memory block MB0 of memory 302).

[0086] Step S720: Application circuit 310 triggers application circuit 330 at time point T1. More specifically, the aforementioned preset conditions are met at time point T1, therefore the sending circuit 311 is notified to transmit the trigger signal TR and progress information PI to application circuit 330.

[0087] Step S725: Processing circuit 334 begins to generate a portion of image IG2-1 (stored in the second memory block MB1 of memory 302).

[0088] Step S730: Application circuit 310 ends task TSK0-0 at time T3. At this time, the first memory block MB0 stores the complete image IG1-1.

[0089] Step S735: The application circuit 310 starts processing task TSK0-1 at time point T4 (for example, starts processing the next image IG0-2 after image IG0-1).

[0090] Step S740: Application circuit 330 ends task TSK1-0, at which point the second memory block MB1 stores the complete image IG2-1.

[0091] Step S745: Application circuit 310 triggers application circuit 330 at time point T5. More specifically, the aforementioned preset conditions are met at time point T5, therefore the transmitting circuit 311 is notified to transmit the trigger signal TR and progress information PI to application circuit 330.

[0092] Step S750: Application circuit 310 ends task TSK0-1 at time T6. At this time, the second memory block MB1 stores the complete image IG1-2.

[0093] like Figure 7 As shown, compared to the existing electronic device 100, because the application circuit 330 can process the image generated by the application circuit 310 earlier according to the progress information PI, the electronic device 300 of the present invention significantly reduces the hardware gap HWG and software gap SWG (the software gap SWG is essentially reduced to 0), thus improving performance.

[0094] Please note that between time point T1 and time point T3, application circuits 310 and 330 operate essentially simultaneously (processing tasks TSK0-0 and TSK1-0 respectively), and during this period, application circuit 310 continuously sends progress information PI to application circuit 330 (for example, sending progress information PI-2 at time point T2). Please refer to [reference needed] for details. Figure 4 and Figure 5 Explanation.

[0095] In some embodiments, application circuit 310 and application circuit 330 can be a lens distortion correction (LDC) circuit and a scaling circuit, respectively. The lens distortion correction circuit is used to correct image distortion caused by different magnifications in the center and edges of the lens. The scaling circuit only requires a minimum of one row of pixels from image IG1-1 for scaling processing (i.e., the aforementioned threshold value is one row of pixels). In other words, there is at least a one-row-pixel difference between application circuit 310 and application circuit 330, representing a very small hardware gap (HWG).

[0096] In other embodiments, application circuit 310 and application circuit 330 can be an image signal processing (ISP) circuit and a lens distortion correction circuit, respectively, as described below. Figure 8 Further explanation. Figure 4 The process and related instructions apply to Figure 8 Examples of implementations.

[0097] Please see Figure 8 , Figure 8 This is a functional block diagram of another embodiment of the electronic device of the present invention. The electronic device 800 includes an image processing circuit 801 (i.e., a specific embodiment of image processing circuit 301) and a memory 802. The image processing circuit 801 includes an image signal processing circuit 810 (i.e., a specific embodiment of application circuit 310) and a lens distortion correction circuit 830 (i.e., a specific embodiment of application circuit 330). The image signal processing circuit 810 is used to perform preliminary processing (including but not limited to exposure compensation, rotation cropping, white balance, color space conversion, and image compression) on the images captured by the lens (e.g., image group IG0). In addition to image groups IG0, IG1, and IG2, the memory 802 also stores a correction algorithm ALG. The memory access circuit (read) 332 also reads the correction algorithm ALG corresponding to image IG1-1, and then the processing circuit 334 corrects image IG1-1 according to the correction algorithm ALG.

[0098] More specifically, the processing circuit 334 includes a calculation module 335, which calculates the corrected position of a pixel in image IG1-1 based on the correction algorithm ALG. Then, the processing circuit 334 fills the corrected pixel value into the corrected position according to the position information. The operation of the processing circuit 334 in generating the corrected pixel includes (but is not limited to) interpolation and color transition of the original pixel.

[0099] The correction algorithm ALG can be generated by the computing unit (not shown in the figure) of the electronic device 800 based on the parameters of the original image (e.g., image IG0-1), the camera lens of the electronic device 800 (not shown in the figure), and / or the jitter of the electronic device 800 (generated by the gyroscope (not shown in the figure)). Because the original image and the jitter of the electronic device 800 are functions of time, each image has its own correction algorithm ALG.

[0100] Different correction algorithms (ALGs) correspond to different threshold values. For example, please refer to [link to example]. Figure 9 , Figure 9 This is a schematic diagram of the image signal processing circuit 810 generating images IG1-1 and IG1-2. The correction algorithm ALG includes a correction image map MAP1 and a correction image map MAP2. Image IG1-1 corresponds to correction image map MAP1, and image IG1-2 corresponds to correction image map MAP2. Correction image map MAP1 is not equal to correction image map MAP2, and correction image maps MAP1 and MAP2 respectively include threshold values ​​TH1 and TH2 (threshold value TH1 is not equal to threshold value TH2). Please note that... Figure 9 The intervals between time points are for illustrative purposes only and do not reflect actual time durations. Please also refer to [link / reference needed]. Figure 7 and Figure 9 The lens distortion correction circuit 830, based on the correction image map MAP1 (or MAP2), determines that at least the image signal processing circuit 810 needs to complete TH1 (or TH2) row pixels before it can begin correcting image IG1-1 (or IG1-2) (roughly corresponding to...). Figure 7 Time point T1 (or T5)).

[0101] Please see Figure 10 , Figure 10 This is a schematic diagram of another embodiment of the image signal processing circuit 810 of the present invention generating image IG1-1. Figure 10 Corresponding to Figure 8Embodiment. Since the distortion degrees at different coordinates within each frame of an image are different, the correction algorithm ALG usually divides a frame of image into many memory blocks according to the distortion degree. For example, the correction map MAP1 of image IG1-1 divides image IG1-1 into four correction regions (A1 to A4) in the vertical direction, and the four correction regions respectively have threshold values TH1-1, TH1-2, TH1-3, and TH1-4 (i.e., the height of the correction region). The lens distortion correction circuit 830 must obtain all pixels of the correction region A1 (A2, A3, or A4) (i.e., TH1-1 (TH1-2, TH1-3, or TH1-4) rows of pixels) to start correcting the region.

[0102] More specifically, at time point T1, the lens distortion correction circuit 830 learns from the progress information PI-1 and the correction map MAP1 that the newly completed part DP (M1 rows of pixels) is greater than or equal to the threshold value TH1-1. Therefore, the lens distortion correction circuit 830 can start correcting image IG1-1. At time point T2, the lens distortion correction circuit 830 learns from the progress information PI-2 and the correction map MAP1 that the newly completed part DP (M2 - M1 rows of pixels) is not greater than or equal to the threshold value TH1-2 (i.e., M2 - M1 < TH1-2). Therefore, the lens distortion correction circuit 830 cannot correct the correction region A2 of image IG1-1 at time point T2 (for example, notify the receiving circuit 331 that it can temporarily not control the memory access circuit (read) 332 to read the newly completed part DP from the memory 802).

[0103] Although the above embodiments take the image signal processing circuit, the lens distortion correction circuit, and the scaling circuit as examples, this is not a limitation to the present invention. Those skilled in the art of this technology field can appropriately apply the present invention to other types of application circuits according to the disclosure of the present invention.

[0104] Although the embodiments of the present invention are as described above, however, the multiple embodiments are not used to limit the present invention. Those skilled in the art of this technology field can make changes to the technical features of the present invention according to the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. That is to say, the scope of patent protection of the present invention shall be subject to what is defined by the scope of patent application in this specification.

Claims

1. An image processing circuit, characterized in that, Coupled to a memory, including: A first application circuit, comprising: A first memory access circuit is used to read a first image from the memory; A first processing circuit, coupled to the first memory access circuit, is used to process the first image to generate a portion of a second image and generate progress information corresponding to the portion, the progress information indicating that the first processing circuit has completed processing M rows of pixels of the second image; A second memory access circuit, coupled to the first processing circuit, is used to store the portion of the second image into the memory; and A notification sending circuit, coupled to the first processing circuit, is used to send the progress information; and A second application circuit, including: A notification receiving circuit, coupled to the notification sending circuit, is used to receive the progress information; A third memory access circuit, coupled to the notification receiving circuit, is used to read the portion of the second image from the memory according to the progress information; wherein the notification receiving circuit compares the progress information with the current processing progress of the second application circuit, and controls the third memory access circuit to read the portion of the second image according to the comparison result; and A second processing circuit, coupled to the third memory access circuit, is used to process the portion of the second image.

2. The image processing circuit as described in claim 1, characterized in that, When the progress information indicates that the number of rows in the portion is greater than or equal to a threshold value, the notification receiving circuit controls the third memory access circuit to read the portion of the second image from the memory.

3. The image processing circuit as described in claim 2, characterized in that, The first application circuit is an image signal processing circuit, the second application circuit is a lens distortion correction circuit, and the memory also stores a correction algorithm. The correction algorithm divides the second image into a plurality of correction regions, and the threshold value is the row number of one of the plurality of correction regions.

4. The image processing circuit as described in claim 3, characterized in that, The threshold value is a first threshold value. The correction algorithm includes a first correction image and a second correction image. The first correction image includes the first threshold value. The first processing circuit also generates a third image. The third image is not equal to the second image. The first image corresponds to the first correction image. The third image corresponds to the second correction image. The second correction image includes a second threshold value. The second threshold value is not equal to the first threshold value.

5. The image processing circuit as described in claim 2, characterized in that, The first application circuit is a lens distortion correction circuit, the second application circuit is a scaling circuit, and the threshold value is equal to 1.

6. The image processing circuit as described in claim 1, characterized in that, The second image comprises N rows of pixels, where N and M are both positive integers, and M is less than N.

7. The image processing circuit as described in claim 1, characterized in that, Whenever the first processing circuit generates a preset number of rows of the second image, the notification sending circuit sends the progress information once.

8. The image processing circuit as described in claim 1, characterized in that, The notification sending circuit sends the progress information at predetermined intervals.

9. The image processing circuit as described in claim 1, characterized in that, The notification sending circuit includes: An information recorder, coupled to the first processing circuit, is used to receive and transmit the progress information; and An event transmitting circuit, coupled to the information recorder, is used to generate a trigger signal; and The notification receiving circuit includes: An information decoder, coupled to the information recorder, is used to receive the progress information; An event receiving circuit, coupled to the event sending circuit and the information decoder, is used to control the information decoder to decode the progress information in response to the trigger signal.

10. The image processing circuit as described in claim 9, characterized in that, When a predetermined time has elapsed or the progress information indicates that the number of rows in the portion of the second image is greater than or equal to a preset number of rows, the information recorder sends the progress information and controls the event sending circuit to generate the trigger signal.

11. An image processing method, characterized in that, Applied to an image processing circuit including a first application circuit and a second application circuit, the image processing circuit being coupled to a memory, the method includes: The first application circuit reads a first image from the memory; The first application circuit processes the first image to generate a portion of a second image and generates progress information corresponding to the portion, the progress information indicating that the first application circuit has completed processing M rows of pixels of the second image; The first application circuit stores the portion of the second image into the memory; The first application circuit sends the progress information; The second application circuit receives the progress information; The second application circuit reads the portion of the second image from the memory according to the progress information; wherein, the progress information is compared with the current processing progress of the second application circuit, and the reading of the portion of the second image is controlled according to the comparison result; and The second application circuit processes the portion of the second image.

12. The image processing method as described in claim 11, characterized in that, When the progress information indicates that the number of rows in the portion is greater than or equal to a threshold value, the second application circuit reads the portion of the second image from the memory.

13. The image processing method as described in claim 12, characterized in that, The first application circuit is an image signal processing circuit, the second application circuit is a lens distortion correction circuit, and the memory also stores a correction algorithm. The correction algorithm divides the second image into a plurality of correction regions, and the threshold value is the row number of one of the plurality of correction regions.

14. The image processing method as described in claim 13, characterized in that, The threshold value is a first threshold value. The correction algorithm includes a first correction image and a second correction image. The first correction image includes the first threshold value. The first application circuit also generates a third image. The third image is not equal to the second image. The first image corresponds to the first correction image. The third image corresponds to the second correction image. The second correction image includes a second threshold value. The second threshold value is not equal to the first threshold value.

15. The image processing method as described in claim 12, characterized in that, The first application circuit is a lens distortion correction circuit, the second application circuit is a scaling circuit, and the threshold value is equal to 1.

16. The image processing method as described in claim 11, characterized in that, The second image comprises N rows of pixels, where N and M are both positive integers, and M is less than N.

Images