Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate, a plurality of active pillars in the substrate, the plurality of active pillars arranged in an array along a first direction and a second direction, the first direction and the second direction are both directions parallel to a top surface of the substrate, and the first direction intersects the second direction, a plurality of word lines, the plurality of word lines are spaced apart along the first direction, each of the word lines extends along the second direction and continuously covers portions of sidewalls of the plurality of active pillars arranged along the second direction, and any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate. The semiconductor structure can reduce the capacitive coupling effect between the two adjacent word lines, and the process is simple, easy to implement and control.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] However, in semiconductor structures such as dynamic random access memory (DRAM), all word lines are located at the same horizontal level. Due to the narrow spacing between adjacent word lines, the coupling effect between them is strong. When a word line is selected to be turned on, the strong coupling effect can cause adjacent word lines to turn on instantaneously, which may eventually lead to problems such as capacitor leakage or even read / write failures, severely affecting memory performance.

[0004] Therefore, how to reduce the coupling effect between adjacent word lines to improve memory performance is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to reduce the coupling effect between adjacent word lines, thereby improving memory performance and increasing memory yield.

[0006] According to some embodiments, this disclosure provides a semiconductor structure, including: a substrate; a plurality of active pillars located within the substrate, the plurality of active pillars being arranged in an array along a first direction and a second direction, the first direction and the second direction being parallel to the top surface of the substrate, and the first direction intersecting the second direction; a plurality of word lines, the plurality of word lines being arranged at intervals along the first direction, each word line extending along the second direction and continuously covering a portion of the sidewall of the plurality of active pillars arranged along the second direction, and any two adjacent word lines being at least partially staggered in a direction perpendicular to the top surface of the substrate.

[0007] In some embodiments, some of the word lines are first word lines and some of the word lines are second word lines; for the plurality of active pillars arranged along the first direction, the first word line covers a portion of the sidewall of the active pillar of the first parity sequence, and the second word line covers a portion of the sidewall of the active pillar of the second parity sequence.

[0008] In some embodiments, the top surface of the first character line is below the bottom surface of the second character line; or, the top surface of the first character line is above the bottom surface of the second character line, and the top surface of the first character line is below the top surface of the second character line.

[0009] In some embodiments, the top surface of the first character line is located below the bottom surface of the second character line, and there is a preset gap between the top surface of the first character line and the bottom surface of the second character line. In a direction perpendicular to the top surface of the substrate, the width of the preset gap is 1 / 4 to 1 / 2 of the size of the first character line.

[0010] In some embodiments, the active pillars include a source region, a channel region, and a drain region arranged sequentially along a direction perpendicular to the top surface of the substrate, and each word line continuously covers the channel region of the plurality of active pillars arranged along the second direction; the semiconductor structure further includes: a plurality of bit lines located within the substrate, the plurality of bit lines being spaced apart along the second direction, each bit line extending along the first direction and being electrically connected to the source region of the plurality of active pillars arranged along the first direction.

[0011] In some embodiments, the method further includes: an insulating layer covering the sidewall of the source region; a gate dielectric layer covering the sidewall of the channel region and the sidewall of the drain region, wherein the word line is located on the surface of the gate dielectric layer on the channel region; and an isolation layer located between adjacent active pillars and covering the surface of the insulating layer, the surface of the word line, and the surface of the gate dielectric layer on the sidewall of the drain region.

[0012] In some embodiments, the word lines are all of equal size in a direction perpendicular to the top surface of the substrate.

[0013] In some embodiments, some of the word lines are first word lines, some are second word lines, and some are third word lines; for a plurality of active pillars arranged along the first direction, the first word line covers a portion of the sidewall of the active pillar at the 3nth position, the second word line covers a portion of the sidewall of the active pillar at the 3n+1th position, and the third word line covers a portion of the sidewall of the active pillar at the 3n+2th position, where n is an integer greater than or equal to 0.

[0014] According to another embodiment, the disclosure further provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of active pillars in the substrate, the plurality of active pillars being arranged in an array along a first direction and a second direction, the first direction and the second direction being both directions parallel to a top surface of the substrate, and the first direction intersecting the second direction; and forming a plurality of word lines, the plurality of word lines being spaced apart along the first direction, each of the word lines extending along the second direction and continuously covering portions of sidewalls of the active pillars arranged along the second direction, any two adjacent word lines being at least partially staggered in a direction perpendicular to the top surface of the substrate.

[0015] In some embodiments, forming the plurality of active pillars in the substrate comprises: etching the substrate to form a plurality of first trenches, the plurality of first trenches being spaced apart along the second direction, each of the first trenches extending along the first direction; forming a first fill layer filling the plurality of first trenches; and etching the substrate to form a plurality of second trenches, the plurality of second trenches being spaced apart along the first direction, each of the second trenches extending along the second direction.

[0016] In some embodiments, after forming the plurality of active pillars and before forming the plurality of word lines, the method further comprises: forming an insulating layer covering top surfaces and sidewalls of the plurality of active pillars; and forming a plurality of bit lines in the substrate, the plurality of bit lines being spaced apart along the second direction, each of the bit lines extending along the first direction and electrically connected to bottom portions of the active pillars arranged along the first direction.

[0017] In some embodiments, the material of the active pillars is silicon, and the plurality of bit lines are formed by a silicon metallization process.

[0018] In some embodiments, the plurality of word lines include first word lines and second word lines, and for the active pillars arranged along the first direction, the first word lines cover portions of sidewalls of the active pillars of a first parity sequence, and the second word lines cover portions of sidewalls of the active pillars of a second parity sequence.

[0019] In some embodiments, forming the plurality of word lines includes: forming the plurality of word lines by: forming an isolation layer that fills the second trench and covers the surface of the insulating layer; etching a portion of the insulating layer to form a second groove between the active pillar of the second parity sequence and the isolation layer; forming a second word line within the second groove; etching a portion of the insulating layer to form a first groove between the active pillar of the first parity sequence and the isolation layer, the depth of the first groove being different from the depth of the second groove; forming a first word line within the first groove, wherein the second word line is offset from the first word line in a direction perpendicular to the top surface of the substrate.

[0020] In some embodiments, forming a second word line located within the second groove includes: forming an initial second word line that fills the second groove; etching back the initial second word line to form the second word line and a third groove located above the second word line; and forming a second filler layer that fills the third groove.

[0021] In some embodiments, the bottom surface of the first groove is above the bottom surface of the second groove, and the bottom surface of the first groove is below the top surface of the second letter line; or, the bottom surface of the first groove is above the top surface of the second letter line.

[0022] In some embodiments, forming a first character line located within the first groove includes: forming an initial first character line that fills the first groove; etching back the initial first character line to form the first character line and a fourth groove located above the first character line; and forming a third filler layer that fills the fourth groove.

[0023] In some embodiments, forming the plurality of word lines includes: forming an isolation layer that fills the second trench and covers the surface of the insulating layer; etching the insulating layer to form a second groove between the active pillar of the second parity sequence and the isolation layer, and a first groove between the active pillar of the first parity sequence and the isolation layer, wherein the first groove and the second groove have different depths; forming a second word line in the second groove and forming a first word line in the first groove, wherein the second word line and the first word line are staggered in a direction perpendicular to the top surface of the substrate.

[0024] In some embodiments, forming a second groove between the active post and the isolation layer in the second parity sequence, and a first groove between the active post and the isolation layer in the first parity sequence, includes: etching the insulating layer between the active post and the isolation layer in the second parity sequence to form an initial second groove; etching the insulating layer between the active post and the isolation layer in the first parity sequence and the insulating layer at the bottom of the initial second groove to form the first groove and the second groove, respectively.

[0025] In some embodiments, forming a first word line in the first groove and a second word line in the second groove includes: depositing a conductive material layer that fills the first groove and the second groove; etching back the conductive material layer in the second groove; etching back the conductive material layer in the second groove and the first groove again, wherein the conductive material layer remaining in the second groove forms the second word line and the conductive material layer remaining in the first groove forms the first word line.

[0026] The semiconductor structure and its formation method provided in some embodiments of this disclosure control the at least partial offset of any two adjacent word lines in a direction perpendicular to the top surface of the substrate, so that the heights of any two adjacent word lines are different, thereby reducing the facing area between adjacent word lines and thus reducing the capacitive coupling effect between adjacent word lines. Furthermore, this disclosure only requires adjusting the number of etching processes to achieve at least partial offset of any two adjacent word lines, making the process simple, easy to implement, and easy to control. Attached Figure Description

[0027] Appendix Figure 1 This is a top view schematic diagram of the semiconductor structure in a specific embodiment of this disclosure;

[0028] Appendix Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure in a specific embodiment of this disclosure;

[0029] Appendix Figure 3 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;

[0030] Appendix Figure 4 This is a top view schematic diagram of a semiconductor structure formed according to a specific embodiment of the present disclosure;

[0031] Appendix Figure 5A-5N This is a schematic diagram of the main process steps in forming a semiconductor structure according to one embodiment of the specific implementation of this disclosure;

[0032] Appendix Figures 6A-6HThis is a schematic diagram of the main process in forming a semiconductor structure, which is another embodiment of the specific implementation of this disclosure. Detailed Implementation

[0033] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0034] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a top view schematic diagram of the semiconductor structure in a specific embodiment of this disclosure, with attached... Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure in a specific embodiment of this disclosure. Figure 2 yes Figure 1 A schematic cross-sectional view along the a-a' direction. The semiconductor structure described in this specific embodiment can be, but is not limited to, a memory, such as DRAM. Figure 1 and Figure 2 As shown, the semiconductor structure includes: a substrate 20, a plurality of active pillars 12, and a plurality of word lines. The plurality of active pillars 12 are located within the substrate 20 and are arranged in an array along a first direction and a second direction. Both the first direction a-a' and the second direction c-c' are parallel to the top surface 201 of the substrate 20, and the first direction a-a' intersects the second direction c-c'. The plurality of word lines are arranged at intervals along the first direction a-a'. Each word line extends along the second direction c-c' and continuously covers a portion of the sidewalls of the plurality of active pillars 12 arranged along the second direction c-c'. In a direction perpendicular to the top surface 201 of the substrate 20, any two adjacent word lines are at least partially staggered.

[0035] For example, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for explanation. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 includes a top surface 201 and a bottom surface 202 opposite to the top surface. A plurality of active pillars 12 are arranged in an array within the substrate 20 along the first direction a-a' and the second direction c-c', with each active pillar 12 extending in a direction perpendicular to the top surface 201 of the substrate 20. A plurality of word lines are located inside the substrate 20, each word line extending along the second direction c-c' and continuously covering a portion of the sidewalls of the plurality of active pillars 12 arranged along the second direction c-c', with the plurality of word lines spaced apart along the first direction a-a'. The intersection may be perpendicular or oblique; this specific embodiment uses a perpendicular intersection as an example for explanation.

[0036] This specific embodiment controls the arrangement of any two adjacent word lines to be at least partially staggered along a direction perpendicular to the top surface 201 of the substrate 20, so that any two adjacent word lines are at different horizontal heights. This reduces the facing area between any two adjacent word lines, thereby reducing the capacitive coupling effect between any two adjacent word lines. This ensures that when one of the two adjacent word lines is selected to be turned on, the other word line will not be turned on due to the capacitive coupling effect, reducing or even avoiding leakage problems between adjacent memory cells, thereby improving the electrical performance of the semiconductor structure.

[0037] In some embodiments, a portion of the multiple word lines are first word lines 111 and a portion of the word lines are second word lines 112; for a plurality of active pillars 12 arranged along the first direction a-a', the first word line 111 covers a portion of the sidewall of the active pillar 12 of the first parity sequence, and the second word line 112 covers a portion of the sidewall of the active pillar 12 of the second parity sequence.

[0038] For example, the first parity sequence can be an odd sequence, and the second parity sequence can be an even sequence. Correspondingly, the first word line 111 covering a portion of the sidewalls of the active pillars 12 in the first parity sequence, and the second word line 112 covering a portion of the sidewalls of the active pillars 12 in the second parity sequence, means that after sequentially sorting the multiple active pillars 12 arranged along the first direction a-a', the sidewalls of the active pillars 12 located in odd-numbered positions are covered by the first word line 111, and the sidewalls of the active pillars 12 located in even-numbered positions are covered by the second word line 112. In the direction perpendicular to the top surface 201 of the substrate 20, the first word line 111 and the second word line 112 are at least partially offset. Of course, the first parity sequence can also be an even sequence, and the second parity sequence can also be an odd sequence. For example, the projection of the first word line 111 along the direction perpendicular to the top surface 201 of the substrate 20 and the projection of the second word line 112 along the direction perpendicular to the top surface 201 of the substrate 20 can be arranged alternately, which helps to simplify the word line formation process and reduce the manufacturing difficulty of the semiconductor structure.

[0039] In some embodiments, the top surface of the first character line 111 is below the bottom surface of the second character line 112; or, the top surface of the first character line 111 is above the bottom surface of the second character line 112, and the top surface of the first character line 111 is below the top surface of the second character line 112.

[0040] For example, in some embodiments, the top surface of the first character line 111 is located below the bottom surface of the second character line 112, that is, the first character line 111 and the second character line 112 are completely offset in the direction perpendicular to the top surface 201 of the substrate 20, and the first character line 111 and the second character line 112 do not overlap at all in the direction perpendicular to the top surface 201 of the substrate 20, thereby minimizing the capacitive coupling effect between adjacent first character lines 111 and second character lines 112. In other embodiments, the top surface of the first word line 111 is above the bottom surface of the second word line 112, and the top surface of the first word line 111 is below the top surface of the second word line 112. That is, the first word line 111 and the second word line 112 are partially offset in a direction perpendicular to the top surface 201 of the substrate 20, and the first word line 111 and the second word line 112 partially overlap in a direction perpendicular to the top surface 201 of the substrate 20. This reduces the capacitive coupling effect between adjacent first word lines 111 and second word lines 112, and helps to reduce the size of the semiconductor structure.

[0041] In some embodiments, the dimensions of the plurality of word lines are all equal in a direction perpendicular to the top surface 201 of the substrate 20.

[0042] For example, in a direction perpendicular to the top surface 201 of the substrate 20, all the first word lines 111 are of equal size, all the second word lines 112 are of equal size, and the size of any one first word line 111 is equal to the size of any one second word line 112. By controlling that the size of all the word lines is equal, the internal resistance of all the word lines can be controlled to be equal, thereby simplifying the control operation of the semiconductor structure.

[0043] When the first word line 111 and the second word line 112 do not overlap completely in the direction perpendicular to the top surface 201 of the substrate 20, the width of the preset gap between the top surface of the first word line 111 and the bottom surface of the second word line 112 should not be too large, otherwise it will lead to an increase in the size and manufacturing cost of the semiconductor structure. In some embodiments, the top surface of the first word line 111 is located below the bottom surface of the second word line 112, and there is a preset gap between the top surface of the first word line 111 and the bottom surface of the second word line 112. The width of the preset gap in the direction perpendicular to the top surface 201 of the substrate 20 is 1 / 4 to 1 / 2 of the size of the first word line 111. Here, the size of the first word line 111 can be the height of the first word line 111 in the direction perpendicular to the top surface 201 of the substrate 20.

[0044] In some embodiments, the active pillar 12 includes a source region, a channel region, and a drain region arranged sequentially along a direction perpendicular to the top surface 201 of the substrate 20, and each word line continuously covers the channel region of the plurality of active pillars 12 arranged along the second direction c-c'; the semiconductor structure further includes: a plurality of bit lines 10 located within the substrate 20, the plurality of bit lines 10 being arranged at intervals along the second direction c-c', each bit line 10 extending along the first direction a-a' and being electrically connected to the source region of the plurality of active pillars 12 arranged along the first direction a-a'.

[0045] For example, such as Figure 1 and Figure 2 As shown, the substrate 20 includes a plurality of bit lines 10, which are located below the word lines. Each bit line 10 extends along a first direction a-a', and the plurality of bit lines 10 are arranged at intervals along a second direction c-c'. Each bit line 10 is electrically connected to the source region of a plurality of active pillars 12 arranged along the first direction a-a'.

[0046] In some embodiments, the semiconductor structure further includes: an insulating layer 15 covering the sidewall of the source region; a gate dielectric layer 14 covering the sidewall of the channel region and the sidewall of the drain region, wherein the word line is located on the surface of the gate dielectric layer 14 on the channel region; and an isolation layer 13 located between adjacent active pillars 12, and covering the surface of the insulating layer 15, the surface of the word line, and the surface of the gate dielectric layer 14 on the sidewall of the drain region.

[0047] For example, the isolation layer 13 is used to electrically isolate adjacent word lines, such as electrically isolating the first word line 111 and the second word line 112 adjacent along the first direction a-a'. The material of the isolation layer 13 may be, but is not limited to, a nitride material, such as silicon nitride. The insulating layer 15 covers the sidewall of the source region and a portion of the top surface of the bit line 10, and the isolation layer 13 covers the surface of the insulating layer 15 and a portion of the top surface of the bit line 10, electrically isolating the word line and the bit line 10 through the insulating layer 15 and the isolation layer 13. The material of the insulating layer 15 may be, but is not limited to, an oxide material, such as silicon dioxide.

[0048] This specific embodiment uses the example of some of the multiple character lines being first character lines and some being second character lines. In other specific embodiments, some of the multiple character lines are first character lines, some are second character lines, and some are third character lines; for the multiple active pillars 12 arranged along the first direction, the first character line covers part of the sidewall of the active pillar 12 at the 3nth position, the second character line covers part of the sidewall of the active pillar 12 at the 3n+1th position, and the third character line covers part of the sidewall of the active pillar 12 at the 3n+2th position, where n is an integer greater than or equal to 0.

[0049] For example, in other specific embodiments, by setting the first word line, the second word line, and the third word line, and arranging them alternately along the first direction, in the direction perpendicular to the top surface 201 of the substrate 20, any two of the first word line, the second word line, and the third word line are at least partially staggered, that is, in the direction perpendicular to the top surface 201 of the substrate 20, the first word line, the second word line, and the third word line are all at different horizontal heights. By setting the first word line, the second word line, and the third word line at different horizontal heights, the coupling effect between the word lines on adjacent active pillars 12 is reduced, and the integration density of the semiconductor structure is also improved.

[0050] This specific embodiment also provides a method for forming a semiconductor structure, attached... Figure 3 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 4 This is a top view schematic diagram of a semiconductor structure formed according to a specific embodiment of the present disclosure, with attached... Figure 5A-5N This is a schematic diagram of the main process steps in forming a semiconductor structure according to one embodiment of the present disclosure. Figures 6A-6H This is a schematic diagram of the main process in forming a semiconductor structure, which is another embodiment of the specific implementation of this disclosure. Figures 5A-5N ,as well as Figures 6A-6H From respectively Figure 4 The four directions a-a', b-b', c-c', and d-d' in the diagram illustrate the main process cross-sections of the semiconductor structure during its formation, clearly demonstrating the semiconductor structure's formation process. A schematic diagram of the semiconductor structure formed in this specific embodiment can be found in [reference needed]. Figure 1 and Figure 2 The semiconductor structure described in this specific embodiment can be, but is not limited to, a memory, such as DRAM. Figures 3-4 , Figures 5A-5N ,as well as Figures 6A-6HAs shown, the method for forming the semiconductor structure includes the following steps S31 to S33.

[0051] Step S31, provide substrate 20, such as Figure 5A As shown.

[0052] For example, the substrate 20 may be, but is not limited to, a silicon substrate; this specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 includes the top surface 201 and a bottom surface 202 opposite to the top surface.

[0053] Step S32: A plurality of active pillars 12 are formed in the substrate 20. The plurality of active pillars 12 are arranged in an array along a first direction a-a' and a second direction c-c'. Both the first direction a-a' and the second direction c-c' are parallel to the top surface 201 of the substrate 20, and the first direction a-a' and the second direction c-c' intersect.

[0054] In some embodiments, forming the plurality of active pillars 12 within the substrate 20 includes: etching the substrate 20 to form a plurality of first trenches, the plurality of first trenches being spaced apart along the second direction c-c', and each first trench extending along the third direction b-b'; forming a first filling layer 21 that fills the plurality of first trenches, such as... Figure 5B As shown; and etching the substrate 20 to form a plurality of second trenches 23, the plurality of second trenches being arranged at intervals along the first direction a-a', and each second trench extending along the fourth direction d-d', as shown. Figure 5C As shown. Thus, the intersection of the first and second trenches defines multiple active pillars 12, such as... Figure 5C As shown. The third direction b-b' is parallel to the first direction a-a', and the fourth direction d-d' is parallel to the second direction c-c'. Therefore, it can also be said that each of the first grooves extends along the first direction a-a', and each of the second grooves extends along the second direction c-c'.

[0055] For example, SADP (Self-aligned Double Patterning) or SAQP (Self-aligned Quardruple Patterning) processes, combined with dry etching, can be used to etch the substrate 20 along a direction perpendicular to the top surface 201 of the substrate 20 to form the first trenches for isolating adjacent bit lines. The plurality of first trenches are arranged at intervals c-c' along the second direction, and each first trench extends a-a' along the first direction. Subsequently, an insulating material such as an oxide material (e.g., silicon dioxide) is deposited within the first trenches to form the first filling layer 21, such as... Figure 5B As shown. The first filler layer 21 is subsequently used to electrically isolate adjacent bit lines. Next, a patterned first mask layer 22 is formed on the top surface 201 of the substrate 20, and the substrate 20 is etched downwards along the first mask layer 22 to form the second trench 23 for isolating adjacent word lines, as shown. Figure 5C As shown. Since the bit lines formed subsequently are located below the word lines, in order to facilitate sufficient isolation of adjacent bit lines, in one embodiment, the depth of the first trench is greater than the depth of the second trench 23 in the direction perpendicular to the top surface 201 of the substrate 20 (i.e., the bottom surface of the second trench 23 is located below the bottom surface of the first trench).

[0056] In some embodiments, after forming the plurality of active pillars 12 and before forming the plurality of word lines, the method further includes: forming an insulating layer 15 covering the top and side surfaces of the plurality of active pillars 12; forming a plurality of bit lines 10 within the substrate 20, the plurality of bit lines 10 being arranged at intervals along the second direction c-c', each bit line 10 extending along the first direction a-a' and electrically connected to the bottom contact of the plurality of active pillars 12 arranged along the first direction a-a', such as... Figure 5D As shown.

[0057] In some embodiments, the active pillar 12 is made of silicon, and the plurality of bit lines 10 are formed using a silicon metallization process.

[0058] For example, after forming the second trench 23, an insulating layer 15 is deposited covering the top and side surfaces of the active pillar 12. The insulating layer 15 may be made of, but is not limited to, oxide materials (e.g., silicon dioxide). The insulating layer 15 protects the active pillar 12 during the subsequent formation of the bit line 10, preventing damage to the active pillar. Then, the substrate 20 is etched along the second trench 23 to form a bit line groove located below and communicating with the second trench 23. The width of the bit line groove is greater than the width of the second trench 23 along the first direction a-a'. Then, a metal layer made of materials such as titanium, cobalt, or nickel is deposited within the bit line groove, and subsequently, the bit line 10 extending along the first direction a-a' is formed using a silicon metallization process.

[0059] Step S33: Multiple word lines are formed, and the multiple word lines are arranged at intervals along the first direction a-a'. Each word line extends along the second direction c-c' and continuously covers part of the sidewalls of the multiple active pillars 12 arranged along the second direction c-c'. In the direction perpendicular to the top surface 201 of the substrate 20, any two adjacent word lines are at least partially staggered.

[0060] In some embodiments, a portion of the multiple word lines are first word lines 111 and a portion of the word lines are second word lines 112; for a plurality of active pillars 12 arranged along the first direction a-a', the first word line 111 covers a portion of the sidewall of the active pillar 12 of the first parity sequence, and the second word line 112 covers a portion of the sidewall of the active pillar 12 of the second parity sequence.

[0061] For example, the first parity sequence can be an odd sequence, and the second parity sequence can be an even sequence. Correspondingly, the first word line 111 covering a portion of the sidewalls of the active pillars 12 in the first parity sequence, and the second word line 112 covering a portion of the sidewalls of the active pillars 12 in the second parity sequence, means that after sequentially sorting the multiple active pillars 12 arranged along the first direction a-a', the sidewalls of the active pillars 12 located in odd-numbered positions are covered by the first word line 111, and the sidewalls of the active pillars 12 located in even-numbered positions are covered by the second word line 112. In the direction perpendicular to the top surface 201 of the substrate 20, the first word line 111 and the second word line 112 are at least partially offset. Of course, the first parity sequence can also be an even sequence, and the second parity sequence can also be an odd sequence. For example, the projection of the first word line 111 along the direction perpendicular to the top surface 201 of the substrate 20 and the projection of the second word line 112 along the direction perpendicular to the top surface 201 of the substrate 20 can be arranged alternately, which helps to simplify the word line formation process and reduce the manufacturing difficulty of the semiconductor structure.

[0062] In some embodiments, forming the plurality of word lines includes: forming an insulating layer 13 that fills the second trench 23 and covers the surface of the insulating layer 15, such as... Figure 5E As shown; the etched portion of the insulating layer 15 forms a second groove 25 located between the active pillar 12 and the isolation layer 13 in the second parity sequence, as... Figure 5G As shown; a second letter line 112 is formed within the second groove 25, as... Figure 5I As shown; the etched portion of the insulating layer 15 forms a first groove 30 located between the active pillar 12 and the isolation layer 13 in the first parity sequence. The depth of the first groove 30 is different from the depth of the second groove 25, as shown. Figure 5L As shown; a first character line 111 is formed within the first groove 30, and a second character line 112 is offset from the first character line 111 in a direction perpendicular to the top surface 201 of the substrate 20.

[0063] In some embodiments, forming a second letter line 112 located within the second groove 25 includes: forming an initial second letter line 26 that fills the second groove 25, such as... Figure 5H As shown; the initial second word line 26 of the etched portion forms the second word line 112, and a third groove 27 located above the second word line 112, as... Figure 5I As shown; a second filling layer 28 is formed to fill the third groove 27, as... Figure 5J As shown.

[0064] In some embodiments, forming a first character line 111 within the first groove 30 includes: forming an initial first character line filling the first groove 30; retracing the initial first character line to form the first character line 111, and a fourth groove 31 located above the first character line 111, as shown below. Figure 5M As shown; a third filling layer 32 is formed to fill the fourth groove 31 as shown. Figure 5N As shown.

[0065] For example, in some embodiments, insulating materials such as nitrides (e.g., silicon nitride) can be deposited in the second trench 23 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form the isolation layer 13. After chemical mechanical polishing (CMP), the desired result is obtained. Figure 5E The structure is shown. Then, a second mask layer 24 is formed on the top surface 201 of the substrate 20, as shown. Figure 5F As shown. The second mask layer 24 has a first etch window 241 exposing a portion of the insulating layer 15, at least a portion of the isolation layer 13, and the top surface of a plurality of active pillars 12 arranged in the second parity sequence. The material of the second mask layer 24 can be an organic mask material such as carbon. Next, a selective wet etching process is used to etch a portion of the insulating layer 15 downwards along the first etch window 241 to form a second groove 25 located between the active pillars 12 and the isolation layer 13 in the second parity sequence, as shown. Figure 5G As shown. Then, an in-situ oxidation process is used to oxidize the sidewalls of the second groove 25, forming a gate dielectric layer 14 on the sides of the plurality of active pillars 12 arranged according to the second parity sequence. Conductive materials such as TiN are deposited in the second groove 25 using methods such as atomic layer deposition, forming the initial second word line 26 that fills the second groove 25 and covers the sidewalls of the gate dielectric layer 14 and the sidewalls of the isolation layer 13. After a chemical mechanical polishing process, a result is formed as shown. Figure 5H The structure is shown. Then, the initial second word line 26 is etched back to form the second word line 112 and the third groove 27 located above the second word line 112, as shown. Figure 5I As shown. Then, an insulating material such as a nitride (e.g., silicon nitride) is filled into the third groove 27, and after chemical mechanical polishing, it is formed as shown. Figure 5J The second filling layer 28 shown.

[0066] Next, a third mask layer 29 is formed on the top surface of the substrate 20, as shown below. Figure 5KAs shown. The third mask layer 29 has a second etching window 291 exposing a portion of the insulating layer 15, at least a portion of the isolation layer 13, and the top surface of a plurality of active pillars 12 arranged in the first parity sequence. Next, a selective wet etching process is used to etch a portion of the insulating layer 15 downwards along the second etching window 291, forming a first groove 30 located between the active pillars 12 in the first parity sequence and the isolation layer 13, as shown. Figure 5L As shown. Then, an in-situ oxidation process is used to oxidize the sidewalls of the first groove 30, forming a gate dielectric layer 14 on the sides of the plurality of active pillars 12 arranged according to the first parity sequence. Conductive materials such as TiN are deposited in the first groove 30 using methods such as atomic layer deposition, forming an initial first word line that fills the first groove 30 and covers the sidewalls of the gate dielectric layer 14 and the sidewalls of the isolation layer 13. After a chemical mechanical polishing process, the top surface of the initial first word line is made flush with the top surface of the isolation layer 13. Then, the initial first word line is etched back to form the first word line 111 and a fourth groove 31 located above the first word line 111, as shown. Figure 5M As shown. Then, an insulating material such as a nitride (e.g., silicon nitride) is filled into the fourth groove 31, and after chemical mechanical polishing, it is formed as shown. Figure 5N The third filling layer 32 shown.

[0067] In some embodiments, the bottom surface of the first groove 30 is above the bottom surface of the second groove 25, and the bottom surface of the first groove 25 is below the top surface of the second character line 112, such that the bottom surface of the formed first character line 111 is above the bottom surface of the second character line 112, and the bottom surface of the first character line 111 is below the top surface of the second character line 112, that is, the first character line 111 and the second character line 112 only partially overlap. In other embodiments, the bottom surface of the first groove 25 is above the top surface of the second character line 112, such that the bottom surface of the first character line is above the bottom surface of the second character line 112, that is, the first character line 111 and the second character line 112 do not overlap.

[0068] In other embodiments, forming the plurality of word lines includes: forming an isolation layer 23 that fills the second trench 23 and covers the surface of the insulating layer 15; etching the insulating layer 23 to form a second groove 25 located between the active pillar 12 of the second parity sequence and the isolation layer 23, and a first groove 30 between the active pillar 12 of the first parity sequence and the isolation layer 23, wherein the first groove 30 and the second groove 25 have different depths, such as... Figure 6CAs shown; a second character line 112 is formed in the second groove 25, and a first character line 111 is formed in the first groove 30. In a direction perpendicular to the top surface 201 of the substrate 20, the second character line 112 and the first character line 111 are staggered, as shown. Figure 6G As shown.

[0069] In some embodiments, forming a second groove 25 between the active pillar 12 and the isolation layer 23 in the second parity sequence, and a first groove 30 between the active pillar 12 and the isolation layer 23 in the first parity sequence, includes: etching the insulating layer 15 between the active pillar 12 and the isolation layer 23 in the second parity sequence to form an initial second groove 65, such as... Figure 6B As shown; etching is performed on the insulating layer 15 located between the active pillar 12 and the isolation layer 23 in the first parity sequence, and on the insulating layer 15 at the bottom of the initial second groove 65, to form the first groove 30 and the second groove 25, respectively. Figure 6C As shown.

[0070] In some embodiments, forming a first word line 111 in the first groove 30 and a second word line 112 in the second groove 25 includes: depositing a conductive material layer 60 that fills the first groove 30 and the second groove 25; etching back the conductive material layer 60 in the second groove 25; etching back the conductive material layer 60 in the second groove 25 and the first groove 30 again, wherein the conductive material layer 60 remaining in the second groove 25 forms the second word line 112 and the conductive material layer 60 remaining in the first groove 30 forms the first word line 111.

[0071] For example, in other embodiments, insulating materials such as nitrides (e.g., silicon nitride) can be deposited in the second trench 23 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the isolation layer 13. After chemical mechanical polishing (CMP), the top surface of the isolation layer 13 is made flush with the top surface of the active pillar 12. Then, a second mask layer 24 is formed on the top surface 201 of the substrate 20, as shown below. Figure 6AAs shown. The second mask layer 24 has a first etch window 241 exposing a portion of the insulating layer 15, at least a portion of the isolation layer 13, and the top surface of a plurality of active pillars 12 arranged according to the second parity sequence. The material of the second mask layer 24 can be an organic mask material such as carbon. Next, using a selective wet etching process, a portion of the insulating layer 15 is etched downwards along the first etch window 241 to form an initial second groove 65 located between the active pillars 12 and the isolation layer 13 in the second parity sequence, as shown. Figure 6B As shown. Next, the second mask layer 24 is removed, and the insulating layer 15 located between the active pillar 12 and the isolation layer 23 in the first parity sequence is etched using a selective wet etching process. The insulating layer 15 at the bottom of the initial second groove 65 is then etched to form the first groove 30 and the second groove 25, respectively. Figure 6C As shown. Subsequently, the sidewalls of the first groove 30 and the second groove 25 are oxidized using an in-situ oxidation process, forming a gate dielectric layer 14 on the sides of the plurality of active pillars arranged according to the first parity sequence and on the sides of the plurality of active pillars 12 arranged according to the second parity sequence.

[0072] Simultaneously, conductive materials such as TiN are deposited in the first groove 30 and the second groove 25, forming a conductive material layer 60 that fills the first groove 30 and the second groove 25. After chemical mechanical polishing, the top surface of the conductive material layer 60 is made flush with the top surface of the active pillar 12. Figure 6D As shown. Next, a fourth mask layer 62 is formed on the top surface 201 of the substrate 20. The fourth mask layer 62 has a third etch window 621 that exposes a plurality of the active pillars 12 arranged in the second parity sequence, a portion of the conductive material layer 60, and at least a portion of the isolation layer 23, as shown. Figure 6E As shown. The conductive material layer 60 located within the second groove 25 is etched back along the third etching window 621, forming a fifth groove 63 within the second groove 25, as shown. Figure 6F As shown. Then, the conductive material layer 60 within the first groove 30 is etched back, and simultaneously, the conductive material layer 60 at the bottom of the fifth groove 63 is etched, forming the first letter line 111 at the bottom of the first groove 30, the fourth groove 31 above the first letter line 111, the second letter line 112 at the bottom of the second groove 25, and the third groove 27 above the second letter line 112, as shown. Figure 6GAs shown. Subsequently, insulating materials such as nitrides (e.g., silicon nitride) are deposited simultaneously in the fourth groove 31 and the third groove 27, forming a second filling layer 28 in the third groove 27 and a third filling layer 32 in the fourth groove 31.

[0073] The semiconductor structure and its formation method provided in some embodiments of this specific implementation control the arrangement of at least partially offset two adjacent word lines in a direction perpendicular to the top surface of the substrate, thereby reducing the face-to-face area between adjacent word lines and thus reducing the capacitive coupling effect between them. Furthermore, this disclosure only requires adjusting the number of etching processes to achieve at least partial offsetting of any two adjacent word lines, resulting in a simple, easy-to-implement, and controllable process.

[0074] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; Multiple active pillars are located within the substrate. The multiple active pillars are arranged in an array along a first direction and a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects the second direction. Each active pillar includes a source region, a channel region, and a drain region arranged sequentially along a direction perpendicular to the top surface of the substrate. Multiple word lines are arranged at intervals along the first direction. Each word line extends along the second direction and continuously covers a portion of the sidewall of the multiple active pillars arranged along the second direction. In a direction perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered. Each word line continuously covers the channel region of the multiple active pillars arranged along the second direction. Multiple bit lines are located within the substrate and are spaced apart along the second direction. Each bit line extends along the first direction and is electrically connected to the source region of a plurality of active pillars arranged along the first direction. Wherein, the source regions in any two adjacent active pillars in the first direction have different dimensions in the direction perpendicular to the top surface of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, Some of the multiple character lines are first character lines, and some of the character lines are second character lines; For the plurality of active columns arranged along the first direction, the first word line covers a portion of the sidewall of the active column of the first parity sequence, and the second word line covers a portion of the sidewall of the active column of the second parity sequence.

3. The semiconductor structure according to claim 2, characterized in that, The top surface of the first character line is below the bottom surface of the second character line; or... The top surface of the first character line is above the bottom surface of the second character line, and the top surface of the first character line is below the top surface of the second character line.

4. The semiconductor structure according to claim 2, characterized in that, The top surface of the first character line is located below the bottom surface of the second character line. There is a preset gap between the top surface of the first character line and the bottom surface of the second character line. In the direction perpendicular to the top surface of the substrate, the width of the preset gap is 1 / 4 to 1 / 2 of the size of the first character line.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: An insulating layer covers the sidewalls of the source region; A gate dielectric layer covers the sidewalls of the channel region and the sidewalls of the drain region, and the word line is located on the surface of the gate dielectric layer on the channel region; An isolation layer is located between adjacent active pillars and covers the surface of the insulating layer, the surface of the word line, and the surface of the gate dielectric layer of the drain region sidewall.

6. The semiconductor structure according to claim 1, characterized in that, In a direction perpendicular to the top surface of the substrate, all of the word lines are of equal size.

7. The semiconductor structure according to claim 1, characterized in that, Some of the aforementioned character lines are first character lines, some are second character lines, and some are third character lines; For the plurality of active columns arranged along the first direction, the first word line covers part of the sidewall of the active column at position 3n, the second word line covers part of the sidewall of the active column at position 3n+1, and the third word line covers part of the sidewall of the active column at position 3n+2, where n is an integer greater than or equal to 0.

8. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; Multiple active pillars are formed in the substrate, and the multiple active pillars are arranged in an array along a first direction and a second direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction and the second direction intersect. The active pillars include a source region, a channel region and a drain region arranged sequentially along a direction perpendicular to the top surface of the substrate. Multiple bit lines are formed in the substrate, the multiple bit lines are arranged at intervals along the second direction, each bit line extends along the first direction and is electrically connected to the bottom of the multiple active pillars arranged along the first direction. as well as Multiple word lines are formed, and the multiple word lines are arranged at intervals along the first direction. Each word line extends along the second direction and continuously covers part of the sidewall of the multiple active pillars arranged along the second direction. In the direction perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered. Each word line continuously covers the channel region of the multiple active pillars arranged along the second direction. Wherein, the source regions in any two adjacent active pillars in the first direction have different dimensions in the direction perpendicular to the top surface of the substrate.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, Forming the plurality of active pillars within the substrate includes: The substrate is etched to form a plurality of first trenches, the plurality of first trenches being spaced apart along the second direction, and each first trench extending along the first direction; Forming a first filling layer that fills the plurality of first trenches; and The substrate is etched to form a plurality of second trenches, the plurality of second trenches being spaced apart along the first direction, and each second trench extending along the second direction.

10. The method for forming a semiconductor structure according to claim 8, characterized in that, After forming the plurality of active pillars and before forming the plurality of word lines, the process further includes: An insulating layer is formed covering the top and sides of the plurality of active pillars.

11. The method for forming a semiconductor structure according to claim 8, characterized in that, The active pillar is made of silicon, and the multiple bit lines are formed using a silicon metallization process.

12. The method for forming a semiconductor structure according to claim 10, characterized in that, Some of the multiple word lines are first word lines and some of the word lines are second word lines; for the multiple active pillars arranged along the first direction, the first word line covers part of the sidewall of the active pillar of the first parity sequence, and the second word line covers part of the sidewall of the active pillar of the second parity sequence.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The formation of the plurality of character lines includes: An insulating layer is formed that fills the second trench and covers the surface of the insulating layer; The etched portion of the insulating layer forms a second groove located between the active pillar of the second parity sequence and the isolation layer; A second letter line is formed within the second groove; The etched portion of the insulating layer forms a first groove between the active pillar of the first parity sequence and the isolation layer, the depth of the first groove being different from the depth of the second groove; A first character line is formed within the first groove, and a second character line is offset from the first character line in a direction perpendicular to the top surface of the substrate.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, Forming the second letter line located within the second groove includes: Forming an initial second letter line that fills the second groove; The initial second word line is etched back to form the second word line and a third groove located above the second word line; A second filling layer is formed to completely fill the third groove.

15. The method for forming a semiconductor structure according to claim 13, characterized in that, The bottom surface of the first groove is above the bottom surface of the second groove, and the bottom surface of the first groove is below the top surface of the second letter; or, The bottom surface of the first groove is located above the top surface of the second letter line.

16. The method for forming a semiconductor structure according to claim 13, characterized in that, Forming a first letter line located within the first groove includes: Forming an initial first character line that fills the first groove; The initial first word line is etched back to form the first word line and a fourth groove located above the first word line; A third filling layer is formed to fill the fourth groove.

17. The method for forming a semiconductor structure according to claim 12, characterized in that, The formation of the plurality of character lines includes: An insulating layer is formed that fills the second trench and covers the surface of the insulating layer; The insulating layer is etched to form a second groove between the active pillar of the second parity sequence and the isolation layer, and a first groove between the active pillar of the first parity sequence and the isolation layer, wherein the first groove and the second groove have different depths. A second character line is formed in the second groove and a first character line is formed in the first groove. The second character line and the first character line are staggered in a direction perpendicular to the top surface of the substrate.

18. The method for forming a semiconductor structure according to claim 17, characterized in that, Forming a second groove between the active pillar of the second parity sequence and the isolation layer, and a first groove between the active pillar of the first parity sequence and the isolation layer, includes: Etching the insulating layer located between the active pillar and the isolation layer in the second parity sequence forms an initial second groove; The insulating layer located between the active pillar and the isolation layer in the first parity sequence, as well as the insulating layer at the bottom of the initial second groove, are etched to form the first groove and the second groove, respectively.

19. The method for forming a semiconductor structure according to claim 18, characterized in that, Forming a first character line in the first groove and forming a second character line in the second groove includes: A conductive material layer is deposited to fill the first groove and the second groove; The conductive material layer within the second groove is etched back. The conductive material layer in the second groove and the first groove is etched again. The conductive material layer remaining in the second groove forms the second word line, and the conductive material layer remaining in the first groove forms the first word line.

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