Compact delay line for wideband phased array systems and associated circuitry

Abstract

A phased array system includes tunable delay elements having active delay elements and passive delay elements. A second resolution of the passive delay elements is less than a first resolution of the active delay elements, and the resolution corresponds to a delay applied to an input signal and has discrete steps for phases at which the delay elements can operate. For a plurality of groups of tunable delay elements, a calibration process sets all delay elements except an nth active delay element and passive delay elements of a group of delay elements to a first phase and sets the nth active delay element to a second phase. In a second group of delay elements, all active delay elements are set to the first phase and passive delay elements are set to the second phase. Phase differences are detected and adjusted to meet a criterion between the two groups.

Description

Background Technology

[0001] This invention generally relates to communication systems, and more specifically, to communication devices having delay lines and phased array antenna systems.

[0002] Fine resolution is crucial for tunable RF (radio frequency) delay lines in many applications, such as phased array radars with beamguides. Most conventional implementations of RF delay lines use multiple switches to change the values ​​of capacitance and inductance along the line. To improve resolution, the unit size of the switches, capacitors, and inductors should be reduced. However, limitations exist on the minimum achievable size due to parasitic effects and losses.

[0003] Transmission lines with tunable elements can be used, but their size is comparable to the wavelength of the waveform. The size of transmission lines incurs cost compared to discrete transistors or integrated circuits.

[0004] Therefore, broadband performance can be challenging. Summary of the Invention

[0005] This part is exemplary and not restrictive.

[0006] In an exemplary embodiment, an apparatus includes a phased array system. The phased array system includes a set of tunable delay elements, comprising at least one active delay element and at least one passive delay element, wherein the at least one active delay element provides a first resolution, and the at least one passive delay element provides a second resolution. The second resolution is less than the first resolution, and the resolution corresponds to a delay applied to an input signal by a corresponding one of the active or passive delay elements. The first resolution is a first set of discrete lengths for a phase on which the at least one active delay element can operate, and the second resolution is a second set of discrete lengths for a phase on which the at least one passive delay element can operate. The number of discrete lengths in the first set is less than the number of discrete lengths in the second set.

[0007] Another exemplary embodiment is an apparatus including a phased array system and control circuitry. The phased array system includes multiple sets of tunable delay elements, each set including at least one active delay element and at least one passive delay element. At least one active delay element provides a first set of resolutions, and the passive delay element provides a second set of resolutions. The number of elements in the first set is less than the number of elements in the second set. The active delay element includes: a first circuit including a first input stage and a first scaling factor stage, the first input stage outputting to the first scaling factor stage, wherein the first scaling factor stage adjusts a first scaling factor based on inputs to the first scaling factor stage; a second circuit including a second input stage and a second scaling factor stage, the second input stage outputting to the second scaling factor stage, wherein the second scaling factor stage adjusts the first scaling factor based on inputs to the second scaling factor stage; and an adder that adds the outputs from the first and second scaling factor stages and produces an output for the active delay element, wherein the inputs adjusted to the first and second scaling factor stages select a single resolution from the first set. The control circuit is coupled to the phased array system and is configured to select and set the delay for at least one active delay element by using inputs to the first and second scaling factor levels and the delay for at least one passive delay element of a plurality of tunable delay elements.

[0008] In another exemplary embodiment, a method includes performing a calibration process on a phased array system. The phased array system includes multiple sets of tunable delay elements, each set including at least one active delay element and at least one passive delay element. The at least one active delay element provides a first set of resolution, and the passive delay element provides a second set of resolution. The number of elements in the first set is less than the number of elements in the second set. The calibration process includes setting all active delay elements except for the nth active delay element in the first set to a first phase, setting the passive delay elements in that set to a first phase, and setting the nth active delay element in that set to a second phase. The calibration process also includes setting all active delay elements in the second set to a first phase and setting the passive delay elements in that set to a second phase. The calibration process further includes detecting a phase difference between the outputs of the first and second sets of tunable delay elements, and adjusting first and second inputs to first and second scaling factor levels of the nth active delay element until the phase difference meets a criterion. The calibration process includes storing one or more codes indicating the first and second inputs of the nth active delay element as calibration points. Attached Figure Description

[0009] Figure 1 It is a block diagram of the circuit for a broadband timing array with real time delay and the corresponding input and output signals;

[0010] Figure 1A yes Figure 1The delay curve of the circuit. Figure 1B yes Figure 1 Phase diagram of the circuit;

[0011] Figure 2 It shows Figure 1 How can a timing array with a real time delay be approximated by a phased array with a narrowband phase shifter via a narrowband approximation?

[0012] Figure 3A It is a diagram illustrating beam deflection, and Figure 3B This is a diagram illustrating inter-symbol interference caused by non-real time delay effects on phased arrays;

[0013] Figure 4A A block diagram of an all-pass filter using active components is shown. Figure 4B The structure diagram of the all-pass filter is shown;

[0014] Figure 5 A schematic diagram of an exemplary variable delay line using a cascaded all-pass filtering method according to an exemplary embodiment is shown;

[0015] Figure 5A A more detailed example of having a delay element in an exemplary embodiment is shown. Figure 5 An example of a variable delay line;

[0016] Figure 6 This is a table of scaling factors, output current, and phase shift for the all-pass (AP), low-pass (LP), or high-pass (HP) filtering methods in the exemplary embodiments; and

[0017] Figure 7 This is a table of scaling factors, output current, and phase shift for the AP, LP, or HP filtering method in the exemplary embodiment of scaling for variant 1 (a) scaling;

[0018] Figure 8 This is a table of scaling factors, output currents, and phase shifts for the AP, LP, or HP filtering methods in the exemplary embodiment of scaling for variant 2 (ii);

[0019] Figure 9 An exemplary delay line and associated circuitry configured for calibrating broadband real-time delay are shown according to an exemplary embodiment.

[0020] Figure 10A Phase comparison of adjacent channels for hybrid delay calibration is shown according to an exemplary embodiment;

[0021] Figure 10B The diagram illustrates a phase comparison of adjacent channels for hybrid delay calibration performed in the case of a beamforming array, according to an exemplary embodiment.

[0022] Figure 11 This is a flowchart of a calibration process for two delay lines, also known as a phase shifter chain, according to an exemplary embodiment.

[0023] Figure 12 This is an illustration of the use of an exemplary tunable delay line for a phase array application, according to an exemplary embodiment.

[0024] Figure 13 Simulation results for a single active delay element 510 with an inductive load are shown;

[0025] Figure 14A and Figure 14B The simulation results are shown at the standard process (P) and temperature (T) angles, where Figure 14A The amplitude is shown. Figure 14B The phase is shown; and

[0026] Figure 15A and Figure 15B The simulation results of the group delay variation at standard P and T angles are shown, where Figure 15A The amplitude is shown. Figure 15B Phase and group delays are shown. Detailed Implementation

[0027] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this detailed description are exemplary embodiments, provided to enable those skilled in the art to make or use the invention, and not to limit the scope of the invention as defined by the claims.

[0028] As mentioned above, broadband performance can be challenging. Exemplary embodiments address this and other issues, for example, by combining interleaved analog (e.g., active) delay units for coarse phase shifting with T-line-based fine delay lines. This results in lower area and power consumption compared to conventional techniques. Furthermore, multiple interleaved phase shifter stages can lead to process-invariant broadband performance.

[0029] Regarding interleaved analog (e.g., active) delay units, the term "interleaved" refers to the frequency response. That is, if there are cascaded N stages (in the sense that the output of the Nth stage is provided to the input of the (N+1)th stage), and the frequency of the maximum gain of the Nth stage is slightly offset relative to the frequency of the (N+1)th stage, then the combined frequency response of the two stages (in general, the N stages) becomes substantially constant over a wide temperature range.

[0030] Therefore, the interleaving of frequency responses makes the overall (cascaded) frequency response nearly constant over a wide frequency range and provides process invariance. For each process corner, the transconductance g can be adjusted when measuring PVT (process, voltage, temperature). m .

[0031] Before describing exemplary embodiments, it is helpful to provide an overview of the technical field in which the exemplary embodiments pertain. One such area relates to a broadband timing array 100 with real time delays, whose circuitry is... Figure 1 As shown in, Figure 1 In the diagram, there are N time delays 110, shown as τ0, ..., (N-1)τ0, Nτ0. A distance d exists between each corresponding amplifier 115 (among the N amplifiers 115) and an antenna 120 (among the N antennas 120). The input signal 105 is illustrated as having (see reference numeral 130) a time delay of τ0. pulse The resulting signal, in which power is illustrated, is shown. The pulse also results in a power spectrum at a frequency (see reference numeral 140) that is f0 c Centered on the array and having a bandwidth of BW, the output signal 150 from an array of N antennas 120 is shown, where each signal is offset by θ. s Where the offset Δx = d sin(θ) s ).

[0032] like Figure 1A As shown, the introduced delay (τ) is a linear multiple of τ0. Figure 1B This shows that the phase (θ) is a function of θ = -ωτ. Note that... Figure 1A The 3τ0 line corresponds to Figure 1B The bottom phase curve in Figure 1A The τ0 curve in the middle corresponds to Figure 1B The top curve in the middle.

[0033] Achieving the true time delay of a broadband timing array 100 may be a practical challenge. One potential way to achieve similar results is through approximation using a phased array. [Go to...] Figure 2 The figure shows Figure 1 How can a timing array with a real time delay be approximated by a phased array with a narrowband phase shifter via a narrowband approximation?

[0034] like Figure 1B (See reference numeral 210) A wideband timing array 100 is shown in block 260. As indicated by reference numeral 230, a narrowband approximation is performed near the frequency ω0, and this results in the phased array 200 comprising N phase shifters θ0, ..., (N-1)θ0, Nθ0, instead of N time delays 110 (see reference numeral 210). Figure 1, are shown as τ0, ..., (N-1)τ0, Nτ0). Using θ0 = ω0τ0, and with reference numeral 220 indicating that this is a reasonable approximation of the true time delay when centered at θ0.

[0035] While the phased array 200 is an attempt to reasonably approximate a broadband timing array 100 with a real time delay, it has problems. In particular, there is a phenomenon of non-real time delay effects in the phased array. Using phase shifters without real time delay characteristics leads to beam skew (see...). Figure 3A ) and inter-symbol interference (see Figure 3B This limits the radar signal bandwidth. For Figure 3A Regarding beam offset, see Garakoui et al., “Phased-array antenna beamsquinting related to frequency dependency of delay circuits”, 8th European Random Conference, Manchester, UK, 2011, pp. 416-419, which states that “beam skew, in other words, means that the antenna pattern points to θ0+Δθ at frequency f0+Δf, rather than to the pointing direction θ0 at frequency f0.”

[0036] for Figure 3B For information on inter-symbol interference, see Jang et al., “A 1-GHz 16-Element Four-BeamTrue-TimeDelay Digital Beamformer,” in IEEE Journal of Solid-State Circuits, vol.54, no.5, pp.1304-1314, May 2019, doi:10.1109 / JSSC.2019.2894357. Figure 3B It is illustrated there as Figure 3(a), and the reference states as follows: "In Figure 3(a), D1-D4 represent data symbols. Antenna 1 receives D2, while the other antennas receive D1. Since D1 and D2 are independent, D2 is simply a distortion of D1, and the performance of the array degrades after beamforming. This phenomenon is called array ISI because the subsequent symbol (D2) interferes with the current symbol (D1)."

[0037] Several types of phase shifters exist. One type is the narrowband phase shifter. One example is called the RTPS (Reflective Phase Shifter), where the phase can be continuously controlled using a varactor diode at the reflecting end, but the operating bandwidth is limited and the control losses vary relatively greatly. See Arun Natarajan et al., “W-Band Dual-Polarization Phased-Array Transceiver Front-End in SiGe BiCMOS,” IEEE Transactions on Microwave Theory and Techniques, Vol. 63, No. 6, June 2015. Also see Hancoating Zhang et al., “A Microstrip line Reflection-Type Phase Shifter for 60GHz Phased Array,” 2019 IEEE / MTT-S International Microwave Symposium. Another type is the broadband phase shifter, such as an artificial transmission line with discrete switches. See WH Woods, A. Valdes-Garcia, H. Ding and J. Rascoe, "CMOS millimeter wave phase shifter based on tunable transmission lines", Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013, pp. 1-4, doi:10.1109 / CICC.2013.6658442.

[0038] Another technique is to use an all-pass filter with active components. Figure 4A A block diagram of an all-pass filter using active components is shown. Figure 4B The block diagram of the all-pass filter is shown. See Garakoui et al., “Compact Cascadable gm-C All-Pass True Time Delay Cell With Reduced Delay Variation OverFrequency,” IEEE Journal of Solid-State Circuits, Vol. 50, No. 3, March 2015, 693-703. Previous implementations of all-pass filters used cascades of gm-C (transconductance-capacitance) structures. Figure 4ATwo amplifiers, 1 and 2, amplifier block 410, and adder 420 are shown. This structural view shows that the amplifier has a transconductance of -g. m The transconductance amplifier, amplifier block 410 includes capacitor C and a value of 1 / g m The resistance, and the transconductance is -2g m Another transconductance amplifier. These all-pass filters have the following problems:

[0039] 1) They are inherently nonlinear.

[0040] 2) Cascading two active stages leads to more distortion.

[0041] 3) Due to the low Q factor, the use of capacitors is prohibited at mmW (millimeter wave) frequencies.

[0042] 4) They require an additional stage to provide impedance matching.

[0043] 5) No tuning mechanism is provided to adjust the phase shift.

[0044] Another possibility is to use an active transconductor around the T-line (transmission line). See W. Lee and A. Valdes-Garcia, “Tunable Delay Line Using Distributed Inductive / Capacitive Miller Effect”, 2018 IEEE / MTT-S International Microwave Symposium-IMS, Philadelphia, PA, USA, 2018, pp. 1445-1448, doi:10.1109 / MWSYM.2018.8439492.

[0045] An overview of the technical field in which the exemplary embodiments pertain has now been provided, and exemplary embodiments have been described. Contrary to what has already been described, the exemplary embodiments relate to variable delay lines using a cascaded all-pass filtering method.

[0046] Go to Figure 5 and Figure 5A , Figure 5 A schematic diagram of an exemplary variable delay line using a cascaded all-pass filtering method according to an exemplary embodiment is shown, and Figure 5A A more detailed example with a delay element is shown. Figure 5 An example of a variable delay line.

[0047] exist Figure 5 and Figure 5AIn the process, delay line 500 includes a plurality of delay elements 510, 510-1, ..., wherein each of these delay elements 500 is considered to be similar, and a delay element 510 is in Figure 5 It is shown as an overview in, and Figure 5A Additional details are shown in the image. There are also fine delay elements 530, such as T-lines or analog types, which... Figure 5A This is also referred to as a real-time delay element. In these examples, the input 501 of delay line 500 is connected to delay element 510, and the output of delay line 500 is the output of delay element 530. Delay element 510 can be referred to here as a "coarse" delay element because the delay implemented by delay element 510 is generally greater than the delay implemented by "fine" delay element 530. The order of coarse delay element 510 and fine delay element 530 can be changed. It should also be noted that multiple coarse delay elements 510 and a single fine delay element 530 are shown, but this can be changed (e.g., a single coarse delay element 510 can be used, or multiple fine delay elements 530 can be used, or only coarse delay element 510 can be used).

[0048] exist Figure 5 In the diagram, the delay element is indicated by the symbol D to signify that it is a delay element. Meanwhile, in... Figure 5A In this context, it is assumed that the coarse delay element 510 has an adjustable (indicated by the arrow) phase. Such as zero or 45 degrees, or possibly zero, 22.5 and 45 degrees, or zero or 90 degrees, etc.; and it is assumed that the fine delay element 530 has a fine phase of ψ, which can be a very small increment, such as a phase shift from zero to 45 degrees by one-hundredth of a phase.

[0049] Note that delay elements 510 (and 530) can also be considered phase shifters, and the phase is also modified by the delay elements. However, for clarity, this circuit will be referred to primarily as a delay element in this document.

[0050] exist Figure 5 In the overview, coarse delay element 510 is shown as having an input 591 with a voltage of V, which is also the input 501 of the first coarse delay element in delay line 500, and an output 598. The input 591 of coarse delay element 510-1 will be the output 598 of the previous delay element 510. That is, the input of a given delay element 510 comes from the output of the previous delay element 510 in delay line 500.

[0051] Input 591 is divided into two degenerate input (i / p) stages 590, stage 1 590-1, and stage 2 590-2. Each stage is coupled to a corresponding scaling factor stage 595, factor 1 (α) 595-1, and factor 2 (β) 595-1. The scaling factors α and β are referenced via... Figure 5AThe described level 595 is created and manipulated. The outputs 596-1 and 596-2 of the scaling factor 595 are added by the adder 597, the output of which is the output 595 of the delay element 510.

[0052] about Figure 5 (and Figure 5A Please make the following comments.

[0053] [1] Input 591 is provided to two input stages 590-1, 590-1, and input 591 can be single-ended or differential.

[0054] [2] Input stages 1590-1 and 2590-2 provide different discrete phase shifts (various combinations are possible, such as zero and 45 degrees as previously described, or zero, 22.5 degrees and 45 degrees).

[0055] [3] Scaling factors α and β are implemented in current mode (e.g., via current guidance).

[0056] [4] The summation of the two paths 596-1 and 596-2 results in zeros and poles; the summation is performed in current mode.

[0057] [5] The poles and zeros result in an all-pass filter, which in turn provides a delay.

[0058] [6] Output matching can be provided using broadband loads (using passive L / C, inductors / capacitors, components).

[0059] [7] Bypassing this stage (coarse delay element 510) is performed by setting β = 0 (typical examples include stage 1 590-1 using resistive elements and stage 2 590-2 using reactive elements).

[0060] [8] Degradation improves linearity and improves matching between I / P transistors.

[0061] exist Figure 5A In the middle, the delay element 510 includes a transformer (Xfmr) or a balun 520 and two circuits 580 and 585. Figure 5AInput 591 is shown as V+ and V-, that is, an input 591 has a voltage V+ and its inverse V-. Circuit 580 includes circuitry for degrading input (I / P) stage 1 590-1 and scaling factor 1 (α) stage 595-1, the scaling factor 1 (α) stage 595-1 including a set 540 of transistors corresponding to the scaling factor α, the set including transistors 540-1, 540-2, 540-3 and 540-4, and circuit 580 also including degrading I / P stage 1 590-1, which includes transistors 550-1 and 550-2, impedance 570 and current sources 560-1 and 560-2. Circuit 585 includes circuitry for degrading input (i / p) stage 2 590-2 and scaling factor 2 (β) stage 595-2. Scaling factor 1 (β) stage 595-2 includes a set 545 of transistors corresponding to scaling factor β, the set including transistors 545-1, 545-2, 545-3 and 545-4. Degrading i / p stage 2 590-2 includes transistors 555-1 and 555-2, impedance 575 and current sources 565-1 and 565-2.

[0062] The degraded I / P stage 590 can also be called a transconductor because these transconductors convert the input voltage into output current via corresponding {Q1, Q2}. For transistors 550-1 and 550-2, the corresponding {Q1, Q2} are... 1A Q 1B For transistors 555-1 and 555-2, the corresponding {Q} is... 2A Q 2B The scaling factor level 595 can be considered a current-directing device. The structures within these configurations are called differential structures, and these structures provide structural symmetry. For example, the following are different configurations: transistors 540-1, 540-2; transistors 540-3, 540-; transistors 545-1, 545-2; transistors 545-3, 545-4; transistors 550-1, 550-2; and transistors 555-1, 555-2.

[0063] The transistor shown in the diagram is a BJT (Bipolar Junction Transistor). The basic technology should apply to MOS (Metal-Oxide-Semiconductor) transistors or BJTs. For a BJT, the terminals will be base, emitter, and collector. For a MOS, the corresponding terminals will be gate, source, and drain. The base or gate terminal can be considered the control terminal, and the base / emitter or source / drain can be the input / output terminals.

[0064] In this configuration, adder 597 includes connections to signal lines going to and from transformer or balun 520. Output 598 and the corresponding current i are shown. in and i out .

[0065] The scaling factor α represents the fraction of the current (e.g., bias) directed to the load and can be varied by V1-V2 in scaling factor 1 (α) level 595-1. Similarly, the scaling factor β represents the fraction of the current directed to the load and can be varied by V1-V2 in scaling factor 2 (β) level 595-2. Once the circuitry for the coarse delay element is fixed, the voltages V1-V2 in scaling factor 1 (α) level 595-1 and the voltages in scaling factor 2 (α) level 595-2 are determined by how their phases are selected.

[0066] By altering the transconductance g of the real and imaginary parts of the amplifier using bias current and / or degenerate elements m The coarse delay of the coarse delay element 510 can be tuned in discrete steps. Scaling of the transconductance in the real and / or imaginary parts results in a change in delay. Z1 and Z2 are impedances that control the delay, DC (direct current) gain, and input impedance matching; these functions can be independent or interdependent. Degradation can provide higher linearity and input impedance matching compared to not using degradation. For degradation, this can include further adding resistors, capacitors, and / or inductors or other circuitry to adjust the delay of the coarse delay element 510 (e.g., including phase). These degradation elements are not shown.

[0067] Degradation is a well-known technique and has been widely used. Consider degradation as follows: any amplifier (which can be voltage / current to voltage / current, all combinations depending on the type of amplifier being addressed) has an input range on which the amplifier remains linear (i.e., the output is essentially linear with respect to the input). Based on the quiescent current, the output signal has a maximum value, so the same output signal with a larger amplitude will be obtained at an input with a lower gain. This reduced gain is called degradation, and the amplifier operates linearly over a larger input swing than an amplifier without degradation.

[0068] Using Z2 as the inductor keeps the input impedance essentially constant and allows for 50Ω input matching. Therefore, one example is that Z1 is a resistor and Z2 is an inductor, although other configurations are possible. When Z2 is an inductor with a value of L, this results in a frequency domain impedance of Z = jωL.

[0069] For analysis, let's consider an example using Z1 as a resistor with a value of R and Z2 as an inductor, with a large Q factor and inductance L. The following analysis of the input current is then performed:

[0070] Where v in The input voltage is V, and s is the Laplace operator, s = σ + iω, or

[0071]

[0072] Now consider that Z1 and Z2 have equal transconductance: g m1 =g m2 =g m This simplifies the following equation:

[0073]

[0074] For g m R << 1, and

[0075] The Variable Delay Line 500 can be used for all-pass (AP), low-pass (LP), or high-pass (HP) filtering methods. Figure 6 This is a scaling factor table, output current, and phase shift for the AP, LP, or HP filtering method in the exemplary embodiment. The first two (AP) rows can be selected as the implementation case because the gain is constant with frequency, while other options may cause the gain to vary with frequency.

[0076] Another exemplary case is variant 1 (a) scaling, where g m R = 1. In this case, it is... Depends on the product g m R, delay elements may require the use of g m R=1 is used to adjust the scaling factor. Figure 7 This is a table of scaling factors, output currents, and phase shifts for the AP, LP, or HP filtering methods used in an exemplary embodiment of scaling for variant 1 (a). For example... Figure 6 The first two (AP) lines can be selected as the implementation case because of the constant gain with frequency, while the other options can result in a gain variation with frequency.

[0077] Another exemplary case is variant 2 scaling, where g m R = 2. In this case, it is... Depends on the product g m R, delay elements may require the use of g m R=2 is used to adjust the scaling factor. Figure 8 This is a table of scaling factors, output currents, and phase shifts for the AP, LP, or HP filtering methods used in the exemplary embodiment of scaling for variant 2 (a) scaling. Figure 6 and Figure 7 The first two (AP) lines can be selected as the implementation case because the gain is constant with frequency, while the other options can cause the gain to vary with frequency.

[0078] As another example, this involves general scaling, where g m R = N. In this case, it is... The delay is as follows: in addition, It is an "active" transconductance, which can be scaled by modifying N, i.e. It is a scaling factor. Furthermore... The phase is shown.

[0079] Exemplary embodiments for implementing delay lines have been described. Additional details regarding the use of delay lines are now provided.

[0080] Calibrating the delay line can be beneficial. Exemplary theories regarding the calibration of broadband true delay include the following:

[0081] 1) The inductance value remains the same at the P and T (process and temperature) angles.

[0082] 2) The Q factor changes with the P and T angles.

[0083] 3) One example is to excite delay lines relative to multiple frequencies and use, for example, the least mean square (LMS) algorithm to measure the delay.

[0084] 4) The phase difference can be sensed by observing the output from the adjacent delay element.

[0085] 5) The accuracy of the passive delay element 530 can be used as a benchmark.

[0086] 6) A coarse delay element 510 can be calibrated at a time.

[0087] One possible calibration process is as follows:

[0088] 1) Changing the transconductance (g) by changing the bias current m ).

[0089] 2) Using two parts of the DAC, one of which is to provide a constant g m The fixed part.

[0090] 3) Use the second part of the DAC, which is the LMS-based correction part of the DAC.

[0091] 4) Provide multiple frequencies to the hybrid delay unit, one frequency at a time.

[0092] 5) Perform a least mean square (LMS) mathematical fit to complete the delay. The intention of using the LMS algorithm is to determine scaling factors (e.g., coefficients) α and β such that the phase shifter is optimized to operate over a wide frequency range, thereby accurately achieving the delay.

[0093] refer to Figure 9This figure illustrates an exemplary delay line 500-1 implemented in a device 900 (such as a receiver or transmitter) according to an exemplary embodiment, and associated circuitry configured to calibrate broadband true delay. Control circuitry 910 is shown, and in this example includes DACs (digital-to-analog converters) 920, 930, and 940, and one or more memories 950 (including CPC, computer program code 960). Control circuitry 910 may include one or more dedicated or general-purpose processors, or dedicated system processors or other processors, such as microcontrollers or DSPs (digital signal processors). Alternatively or additionally, control circuitry 910 may include other hardware, such as programmable logic devices, application-specific integrated circuits (ASICs), very large-scale integrated circuits (VLSI) circuits, or the like. Control circuitry 910 may be programmable, for example, via computer program code 950 in one or more memories 960. One or more memories 960 may include read-only memory, random access memory, solid-state memory, or any other memory. CPC 950 and / or control circuitry 910 may have program and data storage, such as being programmed to implement the processes described herein and storing data acquired or used herein. Assuming CPC 950 is used, one or more memories 960 and computer program code 950 can be configured to cause device 900 to perform one or more of the operations described herein using control circuitry 910.

[0094] This example features a control circuit 910 comprising three DACs: 920, 930, and 940. This is for ease of reference and clarity, and these DACs can be combined into a single DAC or other corresponding circuits, or further subdivided. DAC 920 is the fixed part of the DAC, providing a constant g. m The DAC 930 is the correction section, which applies a constant g. m The correction section 930 can use stored codes, each code corresponding to a specific output of the D2x (see below). The DAC 940 is dedicated to the fine delay element 530 and also produces an output to adjust the phase of the fine delay element 530.

[0095] The DAC 920 outputs D1, which is a constant g. mThe bias is set, and the DAC 930 outputs D2x, where "x" is A, B, C, ..., and is the corrected DAC signal used for the coefficients of the x-th delay element (and the corrected DAC 930 is adjusted according to calibration). The bias (corresponding to bias 1, bias 2, bias 3, ... for each corresponding coarse delay element 500, 500-1, 500-2, ...) is the sum of D1 and D2x, and the voltages of V1-V2 in scaling factor 1 (α) stage 595-1 and scaling factor 2 (β) stage 595-2 are adjusted. Therefore, a single bias for a delay element 510 can include a constant g. m The bias, and up to four other signals, two for V1 and V2 in scaling factor 1 (α) level 595-1, and two more for V1 and V2 in scaling factor 2 (β) level 595-2. Scaling factor levels 595-1 and 595-2 may also have fewer signals, such as...

[0096] An exemplary procedure for process, voltage, and temperature (P, V, T) calibration is as follows. This is an overview of a possible procedure, and... Figure 11 Another example that includes this process.

[0097] 1) Select the operating frequency (F1).

[0098] 2) Two adjacent delay elements are used for phase shifter chain 1 (PS1) and phase shifter chain 2 (PS2).

[0099] 3) Maintain the specific settings for the coarse 1 510 and coarse 2 510-1 delay elements (min or max at either of the two settings, where min = minimum phase and max = maximum phase).

[0100] 4) Set coarse 3510-2 to the lowest target phase shift (e.g., 0°, zero degrees) and fine delay 530 to a known specific phase shift (e.g., 45°): PS1.

[0101] 5) Set coarse to 3 for a 45° phase shift and set fine to 0°: PS2.

[0102] 6) The phase error difference between PS1 and PS2 is generated by one of the following methods: (a) signal subtraction; (b) multiplication to make the vector product zero (e.g., a mixer-based method); or (c) null detection is performed in the beam direction pattern.

[0103] 7) Perform the above steps at multiple frequencies F2, F3, ...

[0104] 8) Minimize error by setting D2C to use the LMS algorithm.

[0105] 9) Repeat the above steps for coarse delay units 1 and coarse delay units 2 respectively.

[0106] 10) Obtain the settings for D2A and D2B.

[0107] 11) If further accuracy is required, digital algorithms can compensate for residual errors after calibration.

[0108] An example of using phase error difference (see above (6)) is to use a phase comparator. Figure 10A Phase comparison of adjacent channels for hybrid delay calibration according to an exemplary embodiment is illustrated. Two phase shifter chains PS1 1000-1 and PS2 1000-2 are shown, and they are shown coupled to phase comparator 1010 via corresponding outputs 1040-1 and 1040-2. Each of the phase shifter chains PS1 1000-1 and PS2 1000-2 is a form of delay line 500 as previously described. Phase shifter chain PS1 1000-1 includes an active broadband time delay section 1020-1, which includes a plurality of coarse delay elements 510, and a passive broadband real time delay section 1030-1, which includes fine delay elements 530. Phase shift channel PS2 1000-2 includes an active broadband time delay section 1020-2, which includes a plurality of coarse delay elements 510, and a passive broadband real time delay section 1030-3, which includes fine delay elements 530.

[0109] The phase comparator 1010 can be implemented in a variety of ways. For example, this can be implemented using a baseband implementation, such as using a phase detector or measuring the zeros of a beamformer. Alternatively, this can be implemented using an RF implementation, such as using a mixer as a phase detector or using a subtractor method.

[0110] Go to Figure 10B This figure illustrates, according to an exemplary embodiment, the phase comparison of adjacent channels for hybrid delay calibration performed in the case of a beamforming array. There are multiple (K) phase shifter channels 1000-1, 1000-2, ..., 1000-k for the beamforming array. Each phase shifter channel 1000 includes multiple (N) active stages 1020 and one passive stage 1030. The figure shows how phase shifter channel 1000-1 is tested, since the N active stages 1020 of phase shifter channels 1000-2, ..., 1000-k are set to zero degrees, and their passive stages 1030 are set to 45 degrees. Meanwhile, the "n" in the nth coarse delay element in phase shifter channel 1000-1 and the corresponding arrow indicate a delay element set to various coarse values ​​(such as 45 degrees).

[0111] Regarding the calibration of broadband real-time latency, the following observations were made:

[0112] 1) Based on BEOL (back-end process), the inductors and capacitors remain the same at the PVT angle.

[0113] 2) The Q factor changes with the PVT angle, but does not affect the phase.

[0114] 3) Delay calibration of the active phase shifter needs to be performed over a wide frequency range.

[0115] The inventors have determined that using the accuracy of a passive tunable delay as a benchmark to calibrate active components is one way to calibrate delay lines.

[0116] Figure 11 This is a flowchart, according to an exemplary embodiment, for calibrating two delay lines, also known as a phase shifter chain. Figure 11 This provides a more detailed description of the content that has already been briefly described above. Figure 11 The illustration also includes the operation of an exemplary method according to an exemplary embodiment, the execution result of computer program instructions implemented on a computer-readable storage medium, functions executed by logic implemented in hardware, and / or interconnection means for performing functions. Assuming... Figure 11 The operation is controlled by control circuit 910. Note that control circuit 910 may follow some or all of the procedures provided by the user for this process (e.g., in computer program code 950). DACs 920 and 930 are controlled by control circuit 910.

[0117] Figure 11 The process begins at block 1105, and in block 1110, control circuit 910 configures DAC 920 to set a constant g. m Bias. In block 1115, control circuit 910 selects a set of N frequencies: {F1, F2, F3, ..., F...} N In block 1120, control circuit 910 sets the mid code for DAC correction of DAC 930. The mid code is the middle code in a range where the correction can be varied, where the code corresponds to the correction for scaling factor level 595, factor 1 (α) 595-1, and factor 2 (β) 595-1, for example, an example with correction terms given by V1-V2, or ΔV. Typically, one way to achieve this is V1 = V0 + ΔV and V2 = V0 - ΔV, where V0 is the bias voltage, which supports static operation. Therefore, block 1120 (and also see block 1130) can involve setting one or more of ΔV for scaling factor level 595, factor 1 (α) 595-1, and factor 2 (β) 595-1, which can be set independently or both can be related to a single voltage difference. There is an applied total bias, which is a constant g. m The sum of the bias and the bias corresponding to the mid code (or multiple biases).

[0118] The process proceeds to block 1121, where blocks 1130 and 1125 are executed. In block 1130, for phase shifter chain PS1 (delay line 500), the coarse delay elements 510 indicated as active elements (“active”) are set to [1:n-1, n+1:N] for zero degree (0°). In other words, there are N delay elements 510, and all delay elements except the Nth are set to zero degree. For PS1, the active [n] is set to 45°. The fine delay elements 530 indicated as passive elements (“passive”) are set to the zero degree (0°) setting. In block 1125, for phase shifter chain PS2 (another delay line 500), the coarse delay elements 510 indicated as active elements (“active”) are all set to [1:N] zero degree (0°). In other words, there are N delay elements 510, and all delay elements are set to zero degree. For PS2, the fine delay element 530, which is indicated as a passive element (“passive”), is set to a 45-degree (45°) setting.

[0119] In block 1135, the phase difference (PD) is detected. Block 1140 determines whether the PD is zero. If the PD is non-zero, then block 1180 = no, and the process proceeds to block 1185, where the DAC code for PS1 used by the nth active [n] delay element 510 is adjusted, and the process returns to block 1120. Note that this can be an increase or decrease in the code, and at the next execution of block 1185, a decision can be made regarding whether to continue in the current direction (increase or decrease) or change direction. For example, if an increase was previously performed and this resulted in a higher PD, a decrease can be performed in block 1185.

[0120] If PD is zero (e.g., or within some variation of zero), then block 1145 is yes, and the process proceeds to block 1150, where it is determined whether all active segments (i.e., coarse delay element 510) have been completed. If no, then block 1174 is no, and the process proceeds to block 1175, where n = n + 1, and the process returns to block 1130. If all active segments have been completed, then block 1155 is yes, and in block 1170, it is determined that all frequencies have been completed. If no, then block 1172 is no, and in 1190, the next frequency is selected by combining the frequency set in block 1115. Note that for the LMS analysis in module 1165, the DAC correction code is stored by frequency for use by the LMS algorithm.

[0121] If all frequencies have been completed, then block 1160 = yes, and the LMS algorithm is run and the DAC is completed (block 1165), which means that g for DAC 920... m The bias and the code for the correction of each coarse delay element in the DAC 930 are known and stored. The process ends at block 1167.

[0122] Figure 11 It includes two delay elements, but this can be extended to full-phase arrays with more than two delay elements. Differential calibration is repeated for adjacent elements to cover all elements in the phased array.

[0123] in addition, Figure 11 These are examples of zero and 45 degrees for active delay elements, but the same process can be performed if the active delay element has more phases (e.g., also 90 degrees) or different phases (e.g., 0, 22.5, and 45 degrees), for example, as long as the passive delay element supports these phases.

[0124] Figure 12 This is an illustration of the use of an exemplary tunable delay line for a phased array application according to an exemplary embodiment. Device 900-1 is a receiver and includes 16 elements 1220-0 to 1220-15, each accepting a 60 GHz input and having an LNA (Low Noise Amplifier), followed by corresponding delay lines 500-0 to 500-15, and a VGA (Variable Gain Amplifier). Digital beamforms 1050-0 to 1050-15 feed the corresponding delay lines 500-0 to 500-15 and the VGA. These signals are input to a passive / active combiner block 1230, which includes 16 passive combiners 1235 in a first stage, four passive combiners 1240 in a second stage, two active combiners, and a single passive combiner that finally outputs to a receiver core 1210.

[0125] Receiver core 1210 includes a digital I / O (input / output) register array and beam control 1260 for at least controlling receiver core 1210. A multiplier is present, which accepts x3 (three times) from a synthesizer, which also outputs to a divider (÷2), which outputs from 16.66 GHz to 18.52 GHz, and its output goes to an IQ phase rotator. The multiplier output goes to a frequency adjuster, providing frequency adjustment from 8.33 GHz to 9.26 GHz, and then to an amplifier. The amplifier output goes to an AM detector, another multiplier, a frequency adjuster, an amplifier, another frequency adjuster, and another amplifier to produce an I output. The amplifier output also goes to an FM discriminator, another multiplier, a frequency adjuster, an amplifier, another frequency adjuster, and another amplifier to produce a Q output.

[0126] The device 900-1 may also include a control circuit 1210 for controlling the operation of the device. This will include the control circuit 910 and control each of the 16 elements 1220-0 to 1220-15, as well as other elements in the device.

[0127] Go to Figure 13This figure shows the simulation results for a single active delay element 510 with an inductive load. Four curves are shown: curves 1310 and 1320 represent amplitude in decibels (dB), see the right vertical axis of V (dB); curves 1330 and 1340 correspond to 1310 and 1320 respectively, and show phase in degrees, see the left vertical axis of V (degrees). The horizontal axis represents the frequency (GHz) from 24.0 to 30.0 GHz. Point 1310-1 is 1.694 dB, point 1310-2 is 1.378 dB. Point 1320-1 is 1.506 dB, point 1320-2 is 1.558 dB. Point 1330-1 is -10.39189 degrees, point 1330-2 is -47.75134 degrees. Point 1340-1 is -47.35073 degrees, and point 1330-2 is -94.09481 degrees.

[0128] It can be seen that the amplitude difference across the frequency band is <200mdB, and there is a linear phase variation of ~10 degrees across the frequency band. If two active delay elements 510 are used, for this example, each element can provide a 45-degree offset; therefore, {0, 45, 90} degrees can be obtained from the two delay elements. A passive fine delay line is added for the 45-degree interpolation. This can reduce the size of the passive phase shifter by a factor of four per channel.

[0129] Figure 13 This can also be used to illustrate the following. One aspect of the exemplary embodiment is to implement specific phase-to-frequency characteristics in the active coarse variable delay element 510. One idea is to create a phase-frequency slope that causes the active delay element to behave like a real time delay over a wide frequency range, similar to the passive delay element already described. The active delay occupies a much smaller area, thus providing overall benefits.

[0130] More detailed information about the phase slope with respect to frequency: the real time delay has a specific phase slope with respect to frequency, such as... Figure 1B As shown. The physical delay corresponds to the real time delay, where at low frequencies, there exists a delay corresponding to a given phase shift (θ1 = 2πf). low / delay), but at higher frequencies, the delay remains the same, but the phase shift increases (θ2=2πf). high / delay>θ1, for f low >f high Typically, active phase shifters do not possess this characteristic. Instead, they typically provide something similar to... Figure 1A The characteristics shown. For example... Figure 3A and Figure 3B as well as Figure 4A and Figure 4B As shown in the comparative examples, it has Figure 1B The phase distribution ratio in has Figure 1A The phase distribution in [the context] is more preferred. Therefore, although [it is as follows] Figure 13 The active circuit shown here, the exemplary circuit here, can have similar Figure 1B The characteristics, namely, Figure 13 This shows a similar phase versus frequency. Figure 1B The characteristics change.

[0131] It can test the process, voltage and temperature (P, V, T or PVT) changes and corresponding angles of equipment such as 900. Figure 14A and Figure 14B The simulation results are shown at the standard process (P) and temperature (T) angles, where Figure 14A The amplitude is shown. Figure 14B The phase is shown. Figure 15A and Figure 15B The simulation results of the group delay variation at standard P and T angles are shown, where Figure 15A The amplitude is shown. Figure 15B Phase and group delays are shown.

[0132] Therefore, there are several options for measuring the angle, including those described below in the available terminology. The designation S_HV_LT indicates a "slow" process angle (first letter, S) with high voltage (second term, HV) and low temperature (third term, LT). The terms S / F / N represent slow / fast / nominal value. The terms HV / NV / LV represent high voltage, nominal voltage, and low voltage. The terms HT / NT / LT represent high temperature, nominal temperature, and low temperature; these are essentially used to observe the robustness of a design relative to process, voltage, and transistor temperature variations. The temperature is the junction temperature, not the ambient temperature. Figure 14A , Figure 14B , Figure 15A , Figure 15B The following naming conventions are shown and explained using the previous naming conventions: F_HV_LT; N_NV_RT; N_NV_NT; N_NV_HT; and S_LV_HT.

[0133] for Figure 14A and Figure 14B Multiple interleaved segments (e.g., delay element 510) can be cascaded to achieve a substantially constant phase difference across the two phase settings. The bias current can also be P,T tracking type to compensate for variations.

[0134] for Figure 15A and Figure 15B These provide the phase derivative of the phase with respect to the frequency curves shown earlier. This is only for a single stage and variations can be reduced by cascading methods.

[0135] The exemplary embodiment can be considered as implementing a hybrid delay approach, such as between a vector modulation-based implementation and a true time delay implementation using microwave technology. This contrasts with conventional techniques.

[0136] One conventional technique is a vector modulation-based implementation, which can be considered to have a relatively narrow bandwidth. The resolution can be DAC-based or otherwise digitally controlled, with input matching operating for a 50Ω input impedance. This area can be relatively compact, and the inputs are quadrature phase. This structure / construction is active and provides gain. For a true time delay implementation using microwave technology, another conventional technique is used, where the bandwidth can be relatively wide, and the resolution can be DAC-based or digitally controlled. For this purpose, the input matching has low impedance, preferably to reduce losses, and the area is relatively large (e.g., due to the transmission line). The input can be single-phase or differential phase, and the structure / construction is typically passive, thus providing loss.

[0137] Conversely, the hybrid delay approach presented herein combines the advantages of both. For example, exemplary embodiments can be applied to wide bandwidths, and wide bandwidth or real-time delay is advantageous for phased array applications. Resolution can be DAC-based, and digital control is provided. Digital control is preferred for easy reconfiguration / calibration. Exemplary embodiments can provide input matching, such as a 50Ω input impedance. In some applications, a 50Ω input impedance is preferred for seamless interface and placement within the architecture. For exemplary embodiments, the area can be compact, and for a given area, the use of transistors, etc., provides higher density compared to, for example, the use of transmission lines. For some implementations, having a compact area is preferred to reduce losses and increase the number of array elements. The input of exemplary embodiments can be single-phase or differential-phase, and single-ended / differential is preferred in some signal distribution applications, and can be switched between each other, for example, using a balun. The architecture of exemplary embodiments can be hybrid, such as providing gain, as signal gain may be required in some implementations to maintain low power.

[0138] Without limiting the scope, interpretation, or application of the following claims in any way, the technical effects and advantages of one or more of the exemplary embodiments disclosed herein include one or more of the following:

[0139] 1) The proposed delay line can reduce the area of ​​a broadband phased array system.

[0140] 2) The proposed delay line can provide power gain (unlike passive delay lines).

[0141] 3) The proposed delay line can provide 50Ω input impedance matching.

[0142] 4) Exemplary embodiments can be used as single-ended or differential. For example, exemplary embodiments can be configured for both single-ended and differential signal paths.

[0143] 5) An exemplary embodiment can be used to provide a continuous delay (by using Z2 as a tunable transmission line or by changing α and β in small steps).

[0144] 6) An exemplary embodiment can be performed by g m ~1 / R tracks changes in P and T.

[0145] 7) The order (coarse, fine) of the delay units can be changed to provide more functionality.

[0146] 8) Exemplary embodiments may be used in place of distortion cancellers, mirror suppression mixers, or clock delays.

[0147] 9) The technology of this invention can be used to implement RF (radio frequency) beamforming, LO (local oscillator) beamforming, or IF (intermediate frequency) beamforming, resulting in a wide range of flexibility. More specifically, in the Cartesian method of multiplying two waveforms IF and LO, we obtain two terms LO+IF and LO-IF. Beamforming essentially means providing different phase shifts to different elements in the array, and this can be done in both LO and IF, and since RF is a linear sum and difference of LO and IF terms, a phase shift in either of them results in the same phase shift in the RF domain.

[0148] If necessary, the different functions discussed herein can be performed in different orders and / or simultaneously with each other. Furthermore, if necessary, one or more of the aforementioned functions can be optional or can be combined.

[0149] Although various aspects of the invention are set forth in the independent claims, other aspects of the invention include other combinations of features from the described embodiments and / or dependent claims with features of the independent claims, and not only the combinations expressly set forth in the claims.

[0150] It should also be noted that while exemplary embodiments of the invention have been described above, these descriptions should not be considered limiting. Rather, various changes and modifications may be made without departing from the scope of the invention as defined in the appended claims.

[0151] In a preferred embodiment of the present invention, an apparatus is now provided, comprising: a phased array system including: multiple sets of tunable delay elements, the multiple sets of tunable delay elements including at least one active delay element and at least one passive delay element, wherein the at least one active delay element provides a first set of resolutions, and the passive delay element provides a second set of resolutions, the number of the first set being less than the number of the second set, wherein the active delay element includes: a first circuit including a first input stage and a first scaling factor stage, the first input stage outputting to the first scaling factor stage, wherein the first scaling factor stage adjusts a first scaling factor based on the input to the first scaling factor stage; a second circuit including a second input stage and A second scaling factor stage, a second input stage output to a second scaling factor stage, wherein the second scaling factor stage adjusts the first scaling factor based on the input to the second scaling factor stage; and an adder that sums the outputs from the first and second scaling factor stages and produces an output for an active delay element, wherein the inputs adjusted to the first and second scaling factor stages select a single one of a first set of resolutions; and control circuitry coupled to the phased array system and configured to select and set the delay for at least one active delay element and the delay for at least one passive delay element using at least the inputs to the first and second scaling factor stages. Preferably, the first input stage includes an impedance Z1; the second input stage includes an impedance Z2; Z1 and Z2 are impedances that control one or more of the delay, DC gain, or input impedance of the active delay element. Preferably, the first and second scaling factor stages are configured to perform current guiding toward a respective one of impedances Z1 or Z2 by adjusting a corresponding first voltage of the first and second scaling factor stages, and wherein the active delay element is configured, based on the operation of impedances Z1 and Z2 and the current guiding, to enable phase-to-frequency characteristics in the active delay element in response to a second voltage being applied to the first and second input stages, the second voltage corresponding to the signal to be delayed. Preferably, impedance Z1 is a resistor and impedance Z2 is an inductor. Preferably, the first scaling factor stage includes a current guiding device configured to guide the amount of output current toward impedance Z1 in response to the first and second voltages input to the first scaling factor stage; and the second scaling factor stage includes a current guiding device configured to guide the amount of output current toward impedance Z2 in response to the first and second voltages input to the second scaling factor stage.Preferably, at least one active delay element includes a plurality of active delay elements for multiple sets of tunable delay elements, and the control circuit is configured to perform a calibration process for at least two sets of tunable delay elements in the plurality of sets of tunable delay elements. The calibration process includes: the control circuit setting all active delay elements in a first set of the set except for the nth active delay element to a first phase, setting the passive delay elements in the set to a first phase, and setting the nth active delay element in the set to a second phase; the control circuit setting all active delay elements in a second set of the set to a first phase, and setting the passive delay elements in the set to a second phase; the control circuit detecting a phase difference between the outputs of the first set of tunable delay elements and the second set of tunable delay elements, and adjusting to the first and second inputs of the first and second scaling factor levels of the nth active delay element until the phase difference meets a criterion; and the control circuit storing one or more codes indicating the first and second inputs of the nth active delay element as calibration points. Preferably, there are N active delay elements in the first group of adjustable delay elements, and the calibration process further includes: the control circuit includes performing the following operations for each of the N active delay elements in the first group of adjustable delay elements: setting all active delay elements in the first group except for the Nth active delay element to a first phase, and setting the Nth active delay element in the group to a second phase; detecting the phase difference between the outputs of the first group of adjustable delay elements and the second group of adjustable delay elements; adjusting the first input and the second input; and storing, wherein a calibration point is stored for each of the N active delay elements in the first group of adjustable delay elements. Preferably, adjusting the first and second inputs to the first and second scaling factor levels of the nth active delay element until the phase difference meets the criteria includes: the control circuit setting a constant bias for the first and second inputs; the control circuit setting a code corresponding to the amount of bias added to or subtracted from the constant bias, wherein the total bias of the first and second inputs is a constant bias added to the bias corresponding to the code, and wherein the calibration point includes the code. Preferably, the code corresponds to the voltage change ΔV, the first input is voltage V1, the second input is voltage V2, V1 = V0 + ΔV and V2 = V0 - ΔV, where V0 is the bias voltage that supports static operation.Preferably, the first and second scaling factor levels have corresponding scaling factors α and β, and wherein the calibration process further includes: performing a calibration process for each of the N active delay elements in the first set of tunable delay elements for a plurality of different frequencies, thereby generating a calibration point for each of the N active delay elements at a plurality of different frequencies; and performing a least mean square (LMS) algorithm using at least the calibration points of each of the N active delay elements at a plurality of different frequencies to determine scaling factors α and β, such that the corresponding active delay elements are optimized to operate within the selected frequency range, thereby accurately achieving the delay of the active delay elements.

Claims

1. An apparatus comprising: Phased array system, including: A set of tunable delay elements, including at least one active delay element and at least one passive delay element, wherein the at least one active delay element provides a first resolution and the at least one passive delay element provides a second resolution. Wherein, the second resolution is smaller than the first resolution, and the first resolution corresponds to the delay applied to the input signal by the at least one active delay element, and the second resolution corresponds to the delay applied to the input signal by the at least one passive delay element. Wherein, the first resolution is a first set of discrete steps for the phase on which the at least one active delay element can operate, the second resolution is a second set of discrete steps for the phase on which the at least one passive delay element can operate, and the number of discrete steps in the first set is less than the number of discrete steps in the second set.

2. The apparatus according to claim 1, wherein, For the at least one active delay element, the delay is programmed by adjusting the current within the at least one active delay element.

3. The apparatus according to claim 1, wherein, The at least one active delay element provides at least two different delays as the first set of discrete step lengths.

4. The apparatus of claim 1, wherein the at least one active delay element comprises a plurality of delay elements, the active delay element comprising: A first circuit includes a first input stage and a first scaling factor stage, wherein the first input stage outputs to the first scaling factor stage; The second circuit includes a second input stage and a second scaling factor stage, wherein the output of the second input stage is to the second scaling factor stage; The adder adds the outputs from the first scaling factor level and the second scaling factor level, and produces the output for the active delay element.

5. The apparatus according to claim 4, wherein: The first input stage includes an impedance Z1; The second input stage includes impedance Z2; Z1 and Z2 are impedances that control one or more of the delay, DC gain, or input impedance of the active delay element.

6. The apparatus according to claim 5, wherein, The first scaling factor stage and the second scaling factor stage are configured to perform current guidance toward a corresponding one of the impedances Z1 or Z2 via adjustment of a corresponding first voltage of the first scaling factor stage and the second scaling factor stage, and wherein the operation of the active delay element based on the impedances Z1 and Z2 and the current guidance is configured to enable the phase-to-frequency characteristics in the active delay element in response to a second voltage being applied to the first input stage and the second input stage, the second voltage corresponding to the signal to be delayed.

7. The apparatus of claim 5, wherein impedance Z1 is a resistor and impedance Z2 is an inductor.

8. The apparatus according to claim 5, wherein: The first input stage includes two differentially configured transistors. The first transistor of the first input stage has a control terminal coupled to an input voltage, a first input / output terminal coupled to the first scaling factor stage, and a second input / output terminal coupled to a first current source. The second transistor of the first input stage has an inverting control terminal coupled to the input voltage, a first input / output terminal coupled to the first scaling factor stage, and a second input / output terminal coupled to a second current source. The impedance Z1 is coupled between the second input / output terminal of the first transistor and the second input / output terminal of the second transistor in the first input stage. The second input stage includes two transistors. The first transistor of the second input stage has a control terminal coupled to the input voltage, a first input / output terminal coupled to the second scaling factor stage, and a second input / output terminal coupled to a third current source. The second transistor of the second input stage has an inverting control terminal coupled to the input voltage, a first input / output terminal coupled to the second scaling factor stage, and a second input / output terminal coupled to a fourth current source. Impedance Z2 is coupled between the second input / output terminal of the first transistor and the second input / output terminal of the second transistor in the second input stage.

9. The apparatus according to claim 5, wherein: The first scaling factor stage includes a current guiding device configured to respond to a first voltage and a second voltage input to the first scaling factor stage by guiding an output current toward the impedance Z1. as well as The second scaling factor stage includes a current guiding device configured to respond to a first voltage and a second voltage input to the second scaling factor stage by guiding an output current toward the impedance Z2.

10. The apparatus according to claim 9, wherein: The current guiding device in the first scaling factor level includes two sets of differential structures, each set including two transistors, wherein each set includes: A first transistor has a control terminal coupled to the first voltage and a first input / output terminal coupled to a transformer or a balun; The second transistor has a control terminal coupled to the second voltage and a first input / output terminal coupled to the power supply voltage; In the first scaling factor level, the second input / output terminals of the first transistor and the second input / output terminals of the second transistor in each differential structure of the current guiding device are coupled together; The second input / output terminal of the first group of the two differential structures of the current guiding device in the first scaling factor stage is coupled to the first input of the first input stage; and The second input / output terminals of the second group of the two differential structures of the current guiding device in the first scaling factor stage are coupled to the second input of the first input stage; and The current guiding device in the second scaling factor level includes two sets of differential structures, each set including two transistors, wherein each set includes: A first transistor has a control terminal coupled to the first voltage and a first input / output terminal coupled to a transformer or a balun; The second transistor has a control terminal coupled to the second voltage and a first input / output terminal coupled to the power supply voltage; In the second scaling factor level, the second input / output terminals of the first transistor and the second input / output terminals of the second transistor in each differential structure of the current guiding device are coupled together; The second input / output terminals of the first of the two differential structures of the current guiding device in the second scaling factor stage are coupled to the first input of the second input stage; and The second input / output terminal of the second group of the two differential structures of the current guiding device in the second scaling factor stage is coupled to the second input of the second input stage.

11. A method for calibrating a phased array system, comprising: A calibration process is performed on a phased array system comprising multiple sets of tunable delay elements, each set including at least one active delay element and at least one passive delay element. The at least one active delay element provides a first set of resolutions, and the at least one passive delay element provides a second set of resolutions. The first set of resolutions is a first set of discrete step lengths for a phase on which the at least one active delay element can operate, and the second set of resolutions is a second set of discrete step lengths for a phase on which the at least one passive delay element can operate. The number of discrete step lengths in the first set is less than the number of discrete step lengths in the second set. The active delay element includes: A first circuit includes a first input stage and a first scaling factor stage, wherein the first input stage outputs to the first scaling factor stage; The second circuit includes a second input stage and a second scaling factor stage, wherein the output of the second input stage is to the second scaling factor stage; And the calibration process described therein includes: In the first group of tunable delay elements, all active delay elements except the nth active delay element are set as the first phase, passive delay elements in the first group of tunable delay elements are set as the first phase, and the nth active delay element in the first group of tunable delay elements is set as the second phase. All active delay elements in the second group of tunable delay elements are set as the first phase, and the passive delay elements in the second group of tunable delay elements are set as the second phase. Detect the phase difference between the outputs of the first group of tunable delay elements and the second group of tunable delay elements, and adjust the first and second inputs of the first and second scaling factor stages of the nth active delay element until the phase difference is zero; and Store one or more codes indicating the first and second inputs of the nth active delay element as calibration points.

12. The method according to claim 11, wherein, There are N active delay elements in the first group of tunable delay elements, where n ≤ N, and the calibration process further includes: For each of the N active delay elements in the first group of tunable delay elements, perform the following operations: set all active delay elements in the first group except for the nth active delay element to a first phase and set the nth active delay element in the first group to a second phase; detect the phase difference between the outputs of the first group of tunable delay elements and the second group of tunable delay elements; adjust the first input and the second input and store the results. Specifically, for each of the N active delay elements in the first group of tunable delay elements, a calibration point is stored.

13. The method according to claim 12, wherein, Adjusting the first and second inputs of the first scaling factor stage and the second scaling factor stage of the nth active delay element until the phase difference is zero includes: Set constant biases for the first input and the second input; and Set a code corresponding to the amount of bias added to or subtracted from the constant bias, wherein the total bias of the first input and the second input is the constant bias added to the bias corresponding to the code, wherein the calibration point includes the code.

14. The method according to claim 13, wherein, The code corresponds to a voltage change ΔV, where the first input is voltage V1 and the second input is voltage V2. V0 is the bias voltage that supports static operation.

15. The method according to claim 14, wherein, The first scaling factor level and the second scaling factor level have corresponding scaling factors α and β, and the calibration process further includes: For multiple different frequencies, the calibration process is performed for each of the N active delay elements in the first group of tunable delay elements, thereby generating calibration points for each of the N active delay elements at the multiple different frequencies; and The least mean square (LMS) algorithm is performed using calibration points at least for each of the N active delay elements at the plurality of different frequencies to determine the scaling factors α and β, such that the corresponding active delay element is optimized to operate within the selected frequency range, thereby accurately achieving the delay of the active delay element.

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