Pixel driving circuit, driving method thereof, and display device

Abstract

This application proposes a pixel drive circuit, a driving method, and a display device. The pixel drive circuit includes a first pixel group and a second pixel group arranged alternately along a column direction, each connected to a shared data line. By arranging the first and second pixel groups, a novel dual-gate pixel architecture is constructed. This novel dual-gate pixel architecture allows two sub-pixels of the same color to be connected simultaneously on the same data line when driving two rows simultaneously, making it applicable to DLG drive scenarios.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a pixel driving circuit, a driving method thereof, and a display device. Background Art

[0002] In the LCD display industry, DRD (Double Rate Driving) design is increasingly being used because it can save the number of Chip On Film (COF) and reduce costs. For example, with a dual-gate pixel architecture, every two columns of sub-pixels share one data line, and each row of pixels has two gates. Compared with a single-gate pixel architecture, the number of data lines and COFs is halved, while the number of gates and GOA levels is doubled. However, Figure 1 In the dual gate pixel architecture shown, when driving two scan lines at the same time, the same data line either connects two sub-pixels of different colors at the same time, or no sub-pixel is connected. In fact, when driving, the same data line can only output pixel data of the same color, and cannot output pixel data of two different colors at the same time. In other words, Figure 1 The dual gate pixel architecture shown cannot be applied to the DLG (double refresh technology) driving scenario. Summary of the Invention

[0003] The main purpose of the embodiments of this application is to provide a pixel driving circuit, a driving method thereof, and a display device. This invention aims to provide a novel dual-gate pixel architecture that allows two sub-pixels of the same color to be connected simultaneously on the same data line when driving two rows simultaneously, and is applicable to DLG driving scenarios.

[0004] To achieve the above-mentioned object, a first aspect of an embodiment of the present application provides a pixel driving circuit, comprising a first pixel group and a second pixel group alternately arranged along a column direction, wherein the first pixel group and the second pixel group are both connected to the same shared data line;

[0005] The first pixel group includes a first row array and a second row array adjacent to each other in the column direction, the first row array includes a first sub-pixel and a second sub-pixel alternately arranged in the row direction, the second row array includes a third sub-pixel and a fourth sub-pixel alternately arranged in the row direction, the first sub-pixel is connected to the nth row scan line, the second sub-pixel is connected to the n+1th row scan line, the third sub-pixel is connected to the n+3th row scan line, and the fourth sub-pixel is connected to the n+2th row scan line;

[0006] The second pixel group includes a third row array and a fourth row array adjacent to each other in the column direction, the third row array includes a fifth sub-pixel and a sixth sub-pixel alternately arranged in the row direction, the fourth row array includes a seventh sub-pixel and an eighth sub-pixel alternately arranged in the row direction, the fifth sub-pixel is connected to the (n+5)th scan line, the sixth sub-pixel is connected to the (n+4)th scan line, the seventh sub-pixel is connected to the (n+6)th scan line, and the eighth sub-pixel is connected to the (n+7)th scan line, where n is a natural number greater than or equal to 1;

[0007] The first sub-pixel, the third sub-pixel, the fifth sub-pixel, and the seventh sub-pixel are sequentially arranged along a column direction to form a first column array, and the second sub-pixel, the fourth sub-pixel, the sixth sub-pixel, and the eighth sub-pixel are sequentially arranged along a column direction to form a second column array. The shared data line is arranged to intersect with each of the scan lines. The shared data line passes through a position between the first column array and the second column array and is connected to each sub-pixel in the first column array and the second column array.

[0008] The sub-pixels in the same column array have the same color.

[0009] In one embodiment of the present application, the first row array includes a plurality of the first sub-pixels and a plurality of the second sub-pixels arranged alternately, the second row array includes a plurality of the third sub-pixels and a plurality of the fourth sub-pixels arranged alternately, the third row array includes a plurality of the fifth sub-pixels and a plurality of the sixth sub-pixels arranged alternately, the fourth row array includes a plurality of the seventh sub-pixels and a plurality of the eighth sub-pixels arranged alternately, and the pixel driving circuit correspondingly forms a plurality of the first column arrays and a plurality of the second column arrays arranged alternately along the row direction, and the pixel driving circuit is provided with a plurality of the shared data lines arranged at intervals in the row direction, and the shared data lines pass through the position between the corresponding first column array and the second column array.

[0010] In one embodiment of the present application, any two adjacent sub-pixels in each row array have different colors.

[0011] In one embodiment of the present application, the pixel driving circuit is configured to drive with a first preset cycle, and the preset cycle is to sequentially and simultaneously drive the n+1th scan line, the n+2th scan line, the n+3th scan line and the nth scan line, the n+4th scan line and the n+7th scan line, and the n+6th scan line and the n+5th scan line.

[0012] A second aspect of the embodiments of the present application provides a driving method for driving the pixel driving circuit described in any embodiment of the present application, the driving method comprising:

[0013] providing scan pulses to the scan lines according to a first preset period, wherein the first preset period sequentially and simultaneously drives the scan line (n+1) and the scan line (n+2), the scan line (n+3) and the scan line (n), the scan line (n+4) and the scan line (n+7), and the scan line (n+6) and the scan line (n+5);

[0014] determining a pixel voltage applied to each of the sub-pixels through the shared data line according to a connection relationship between each of the sub-pixels and the scan line and the shared data line;

[0015] The pixel voltage is applied to the shared data line in synchronization with the scan pulse to drive each of the sub-pixels.

[0016] In one embodiment of the present application, after determining the first preset period, the method includes:

[0017] Generate a corresponding driving timing signal according to the driving sequence determined by the first preset period;

[0018] A scan pulse is provided to the scan line according to the driving timing signal.

[0019] A third aspect of the embodiments of the present application provides a driving method for driving the pixel driving circuit described in any embodiment of the present application, the driving method comprising:

[0020] providing scan pulses to the scan lines according to a second preset period, wherein the second preset period sequentially drives the (n+1)th scan line, the (n+2)th scan line, the (n+3)th scan line, the (n)th scan line, the (n+4)th scan line, the (n+7)th scan line, the (n+6)th scan line, and the (n+5)th scan line;

[0021] determining a pixel voltage applied to each of the sub-pixels through the shared data line according to a connection relationship between each of the sub-pixels and the scan line and the shared data line;

[0022] determining the polarity of the pixel voltage applied to each of the sub-pixels according to two-row polarity inversion settings;

[0023] A pixel voltage with a polarity is applied to the shared data line in synchronization with the scan pulse to drive each of the sub-pixels.

[0024] In one embodiment of the present application, driving each of the sub-pixels includes driving the first pixel group, and driving the first pixel group includes performing the following steps in sequence:

[0025] providing a scan pulse to the (n+1)th scan line, and applying a second pixel voltage having a first polarity to the second sub-pixel through the shared data line;

[0026] providing a scan pulse to the (n+2)th scan line, and applying a fourth pixel voltage having the first polarity to the fourth sub-pixel through the shared data line;

[0027] providing a scan pulse to the (n+3)th scan line, and applying a third pixel voltage having a second polarity to the third sub-pixel through the shared data line, wherein the first polarity and the second polarity are opposite polarities;

[0028] A scan pulse is provided to the n-th scan line, and a first pixel voltage having the second polarity is applied to the first sub-pixel through the shared data line.

[0029] In one embodiment of the present application, driving each of the sub-pixels includes driving the second pixel group, and driving the second pixel group includes performing the following steps in sequence:

[0030] providing a scan pulse to the (n+4)th scan line, and applying a sixth pixel voltage having a second polarity to the sixth sub-pixel through the shared data line;

[0031] providing a scan pulse to the (n+7)th scan line, and applying an eighth pixel voltage having the second polarity to the eighth sub-pixel through the shared data line;

[0032] providing a scan pulse to the (n+6)th scan line, and applying a seventh pixel voltage having a first polarity to the seventh sub-pixel through the shared data line, wherein the second polarity is opposite to the first polarity;

[0033] A scan pulse is provided to the (n+5)th scan line, and a fifth pixel voltage having the first polarity is applied to the fifth sub-pixel through the shared data line.

[0034] A fourth aspect of the embodiments of the present application provides a display device, including:

[0035] A display panel, the display panel comprising the pixel driving circuit described in any embodiment of the present application;

[0036] A timing control module is connected to the display panel and is used to execute the driving method described in any embodiment of the present application to drive the pixel driving circuit.

[0037] In the technical solution provided in the embodiments of the present application, the pixel driving circuit includes a first pixel group and a second pixel group arranged alternately along the column direction, each connected to the same shared data line. This arrangement of the first and second pixel groups creates a novel dual-gate pixel architecture. This novel dual-gate pixel architecture allows two sub-pixels of the same color to be connected simultaneously on the same data line when driving two rows simultaneously, making it suitable for DLG drive scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is the dual gate pixel architecture diagram proposed in the related technology;

[0039] Figure 2 is a structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0040] Figure 3 is another structural schematic diagram of the pixel driving circuit provided in an embodiment of the present application;

[0041] Figure 4 is a flowchart of the driving method provided in an embodiment of the present application;

[0042] Figure 5 This is an example timing diagram corresponding to driving according to the first preset cycle provided in an embodiment of the present application;

[0043] Figure 6 is a flowchart of steps performed after determining the first preset period provided by an embodiment of the present application;

[0044] Figure 7 is another flow chart of the driving method provided in an embodiment of the present application;

[0045] Figure 8 This is an example timing diagram corresponding to driving according to the second preset cycle provided in an embodiment of the present application;

[0046] Figure 9 is a schematic structural diagram of a pixel driving circuit with polarity shown in an embodiment of the present application;

[0047] Figure 10 is a flowchart of the steps of driving the first pixel group provided in an embodiment of the present application;

[0048] Figure 11 This is a flowchart of the steps for driving the first pixel group provided in an embodiment of the present application.

[0049] The following are the descriptions of the reference numerals:

[0050] First pixel group 1; second pixel group 2; shared data line 3; first row array 11; second row array 12; first sub-pixel 111; second sub-pixel 112; third sub-pixel 121; fourth sub-pixel 122; third row array 21; fourth row array 22; fifth sub-pixel 211; sixth sub-pixel 212; seventh sub-pixel 221; eighth sub-pixel 222; first column array 41; second column array 42. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0052] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and so on, in the specification, claims, and drawings, are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0054] Liquid Crystal Displays (LCDs) have numerous advantages, including thin body, power saving, and zero radiation, and have been widely used. In the development of large-size and high-refresh-rate display panels, dual-gate technology has attracted attention. The principle of DLG technology is that the panel's GDL circuit simultaneously opens two rows of scan lines, and both rows are input with the same scan signal. In this mode, the amount of data displayed vertically is reduced by half, and the refresh rate can be doubled without changing the original hardware and chip computing power.

[0055] In recent years, the cost pressure of panels has increased significantly due to the shortage of driver chips (ICs) and the rise in raw material prices in the semiconductor industry. Many end-user customers are urging to reduce costs by reducing the number of source driver chips (ICs). Due to the high cost of source drivers, the gate side can adopt GOA (gate on array, array substrate row drive) circuit design, which does not require the use of additional driver chips. Therefore, the dual gate technology goal can be achieved by reducing the number of data lines and source integrated circuits (source ICs) and doubling the number of gate lines. However, as Figure 1 In the dualgate pixel architecture shown, when driving two scan lines at the same time, the same data line either connects two sub-pixels of different colors at the same time, or no sub-pixels are connected. In fact, when driving, the same data line can only output pixel data of the same color, and cannot output pixel data of two different colors at the same time. In other words, Figure 1 The dual gate pixel architecture shown cannot be applied to the DLG (double refresh technology) driving scenario.

[0056] Based on this, the embodiment of the present application proposes a pixel driving circuit to construct a new dual gate pixel architecture. Figure 1 The dual gate pixel architecture shown in the figure has the following characteristics: when driving two rows simultaneously, two sub-pixels of the same color can be connected to the same data line at the same time, which can be applied to DLG driving scenarios.

[0057] Reference Figure 2 , Figure 2 Schematic diagram of the structure of the pixel driving circuit provided by the embodiment of the present application. Figure 2 As shown, the pixel driving circuit includes a first pixel group 1 and a second pixel group 2 alternately arranged along the column direction, and the first pixel group 1 and the second pixel group 2 are both connected to the same shared data line 3.

[0058] The first pixel group 1 includes a first row array 11 and a second row array 12, which are adjacent to each other in the column direction. The first row array 11 includes first sub-pixels 111 and second sub-pixels 112, which are alternately arranged in the row direction. The second row array 12 includes third sub-pixels 121 and fourth sub-pixels 122, which are alternately arranged in the row direction. The first sub-pixel 111 is connected to the nth scan line, the second sub-pixel 112 is connected to the n+1th scan line, the third sub-pixel 121 is connected to the n+3th scan line, and the fourth sub-pixel 122 is connected to the n+2th scan line.

[0059] The second pixel group 2 includes a third row array 21 and a fourth row array 22, which are adjacent to each other in the column direction. The third row array 21 includes a fifth sub-pixel 211 and a sixth sub-pixel 212, which are alternately arranged in the row direction. The fourth row array 22 includes a seventh sub-pixel 221 and an eighth sub-pixel 222, which are alternately arranged in the row direction. The fifth sub-pixel 211 is connected to the (n+5)th scan line, the sixth sub-pixel 212 is connected to the (n+4)th scan line, the seventh sub-pixel 221 is connected to the (n+6)th scan line, and the eighth sub-pixel 222 is connected to the (n+7)th scan line, where n is a natural number greater than or equal to 1.

[0060] The first sub-pixel 111, the third sub-pixel 121, the fifth sub-pixel 211, and the seventh sub-pixel 221 are arranged in sequence along the column direction to form a first column array 41. The second sub-pixel 112, the fourth sub-pixel 122, the sixth sub-pixel 212, and the eighth sub-pixel 222 are arranged in sequence along the column direction to form a second column array 42. The shared data line 3 is arranged to cross each scan line. The shared data line 3 passes through the position between the first column array 41 and the second column array 42 and is connected to each sub-pixel on the first column array 41 and the second column array 42.

[0061] The sub-pixels in the same column array have the same color.

[0062] In the present application, refer to Figure 2When the (n+1)th and (n+2)th scan lines are driven simultaneously, the second subpixel 112 and the fourth subpixel 122 connected to the shared data line 3 are connected. Since the second subpixel 112 and the fourth subpixel 122 belong to the same column array, and the subpixels in the same column array have the same color, the second subpixel 112 and the fourth subpixel 122 belong to the same color pixel. Therefore, when the (n+1)th and (n+2)th scan lines are driven simultaneously, pixel data of the same color can be input to the second subpixel 112 and the fourth subpixel 122 simultaneously via the shared data line 3. Similarly, when the (n+3)th and (n)th scan lines are driven simultaneously, the first subpixel 111 and the third subpixel 121 connected to the shared data line 3 are connected. Since the first subpixel 111 and the third subpixel 121 belong to the same column array, and the subpixels in the same column array have the same color, the first subpixel 111 and the third subpixel 121 belong to the same color pixel. Therefore, when the n+3th and nth scan lines are driven simultaneously, pixel data of the same color can be simultaneously input to the first subpixel 111 and the third subpixel 121 via the shared data line 3. When the n+4th and n+7th scan lines are driven simultaneously, the fifth subpixel 211 and the seventh subpixel 221 connected to the shared data line 3 are connected. Since the fifth subpixel 211 and the seventh subpixel 221 belong to the same column array, and the subpixels in the same column array have the same color, the fifth subpixel 211 and the seventh subpixel 221 belong to the same color pixel. Therefore, when the n+4th and n+7th scan lines are driven simultaneously, pixel data of the same color can be simultaneously input to the fifth subpixel 211 and the seventh subpixel 221 via the shared data line 3. When the n+6th and n+5th scan lines are driven simultaneously, the sixth sub-pixel 212 and the eighth sub-pixel 222 connected to the shared data line 3 are connected. Since the sixth sub-pixel 212 and the eighth sub-pixel 222 belong to the same column array, and the sub-pixels in the same column array have the same color, the sixth sub-pixel 212 and the eighth sub-pixel 222 belong to the same color pixel. Therefore, when the n+6th and n+5th scan lines are driven simultaneously, the pixel data of the same color can be input to the sixth sub-pixel 212 and the eighth sub-pixel 222 at the same time through the shared data line 3. It can be seen that based on Figure 1 The new dual gate pixel architecture shown has the ability to simultaneously drive two rows, allowing two sub-pixels of the same color to be connected to the same data line at the same time, making it applicable to DLG driving scenarios.

[0063] In one embodiment of the present application, referring to Figure 2The first row array 11 includes a plurality of first sub-pixels 111 and a plurality of second sub-pixels 112 arranged alternately. The second row array 12 includes a plurality of third sub-pixels 121 and a plurality of fourth sub-pixels 122 arranged alternately. The third row array 21 includes a plurality of fifth sub-pixels 211 and a plurality of sixth sub-pixels 212 arranged alternately. The fourth row array 22 includes a plurality of seventh sub-pixels 221 and a plurality of eighth sub-pixels 222 arranged alternately. The pixel driving circuit accordingly forms a plurality of first column arrays 41 and a plurality of second column arrays 42 arranged alternately along the row direction. The pixel driving circuit is provided with a plurality of shared data lines 3 arranged alternately along the row direction. The shared data lines 3 pass through the positions between the corresponding first column arrays 41 and second column arrays 42.

[0064] In the embodiment of the present application, in the pixel driving circuit, a plurality of first pixel groups 1 are arranged at intervals in the row direction of the row where the first pixel group 1 is located, and a plurality of second pixel groups 2 are arranged at intervals in the row direction of the row where the second pixel group 2 is located. The first pixel groups 1 and the second pixel groups 2 are arranged alternately in the column direction. Similarly, Figure 2 As shown, the new dualgate pixel architecture composed of the pixel driving circuit has the possibility of simultaneously driving two rows, and two sub-pixels of the same color can be connected to the same data line at the same time, so it can be applied to the DLG driving scenario.

[0065] In one embodiment of the present application, any two adjacent sub-pixels in each row array have different colors. Figure 3 , Figure 3 is another structural diagram of the pixel driving circuit provided in an embodiment of the present application. Figure 3 As shown, in the row array, the colors of the sub-pixels are arranged alternately in the order of red, green, and blue. Thus, all sub-pixels in the first column array are red, all sub-pixels in the second column array are green, and all sub-pixels in the third column array are blue.

[0066] It should be noted that the embodiments of this application Figure 3 The present invention only illustrates one color arrangement sequence of the sub-pixels in the row array, namely, alternating red, green, and blue. The present embodiment does not impose any specific restrictions on the color arrangement sequence of the sub-pixels in the row array, as long as any two adjacent sub-pixels have different colors. For example, the color arrangement sequence of the sub-pixels in the row array can also be red, blue, green, or blue, green, red, or blue, red, green, or green, red, blue, or green, blue, red.

[0067] In one embodiment of the present application, the pixel driving circuit is configured to drive with a first preset cycle, and the preset cycle is to simultaneously drive the n+1th row scan line and the n+2th row scan line, the n+3th row scan line and the nth row scan line, the n+4th row scan line and the n+7th row scan line, and the n+6th row scan line and the n+5th row scan line.

[0068] In an embodiment of the present application, the pixel driving circuit is driven with a first preset cycle, that is, when the n+1th row scan line and the n+2th row scan line are driven simultaneously, each shared data line 3 is connected to two sub-pixels of the same color at the same time. Then, the n+3th row scan line and the nth row scan line are driven simultaneously, and each shared data line 3 is still connected to two sub-pixels of the same color at the same time. Then, the n+4th row scan line and the n+7th row scan line are driven simultaneously, and each shared data line 3 is still connected to two sub-pixels of the same color at the same time. Then, the n+6th row scan line and the n+5th row scan line are driven simultaneously, and each shared data line 3 is still connected to two sub-pixels of the same color at the same time. That is, the pixel driving circuit is cyclically driven according to the first preset cycle, so that the shared data line 3 is simultaneously connected to two sub-pixels of the same color during each row driving, thereby realizing DLG driving.

[0069] In one embodiment of the present application, referring to Figure 4 , Figure 4 This is a flowchart of a driving method provided by an embodiment of the present application, which is used for a pixel driving circuit provided by any embodiment of the present application. The method includes but is not limited to steps S410 to S430.

[0070] Step S410, providing scan pulses to the scan lines according to a first preset cycle, wherein the first preset cycle is to sequentially and simultaneously drive the n+1th scan line and the n+2th scan line, the n+3th scan line and the nth scan line, the n+4th scan line and the n+7th scan line, and the n+6th scan line and the n+5th scan line.

[0071] In the embodiment of the present application, the scan line driving module provides a scan pulse to the scan line according to a first preset period. Figure 5 , Figure 5 This is a timing diagram corresponding to the first preset cycle driving provided by the embodiment of the present application. After the scan line driving module receives the first driving signal, the scan line driving module simultaneously sends a signal to the n+1th row of scan lines. Figure 5 The driving voltage waveform signal (i.e., the scanning pulse) corresponding to G1 shown in FIG and the driving voltage waveform signal sent to the n+2th row scanning line Figure 5 The driving voltage waveform signal corresponding to G2 is shown in FIG. Among them, the driving voltage waveform signal corresponding to G1 is the same as the driving voltage waveform signal corresponding to G2. After the scanning line driving module receives the second driving signal, the scanning line driving module simultaneously sends a signal to the n+3th row scanning line. Figure 5The driving voltage waveform signal corresponding to G3 shown in FIG and sent to the n-th row scan line Figure 5 The driving voltage waveform signal corresponding to G4 is shown in FIG. Among them, the driving voltage waveform signal corresponding to G3 is the same as the driving voltage waveform signal corresponding to G4. After the scanning line driving module receives the third driving signal, the scanning line driving module simultaneously sends a signal to the n+4th row scanning line. Figure 5 The driving voltage waveform signal corresponding to G5 shown in FIG and sent to the n+7th row scanning line Figure 5 The driving voltage waveform signal corresponding to G6 is shown in FIG. Among them, the driving voltage waveform signal corresponding to G5 is the same as the driving voltage waveform signal corresponding to G6. After the scanning line driving module receives the fourth driving signal, the scanning line driving module simultaneously sends a signal to the n+6th row scanning line. Figure 5 The driving voltage waveform signal corresponding to G7 shown in FIG and sent to the n+5th row scanning line Figure 5 The driving voltage waveform signal corresponding to G8 is shown in FIG. The driving voltage waveform signal corresponding to G7 is the same as the driving voltage waveform signal corresponding to G8.

[0072] Step S420 : determining the pixel voltage applied to each sub-pixel through the shared data line according to the connection relationship between each sub-pixel and the scan line and the shared data line.

[0073] In the embodiment of the present application, the timing control module reorganizes the pixel voltage data provided by the SOC (system on chip) based on the connection relationship between each sub-pixel and the scan line and the shared data line in the pixel driving circuit to determine the pixel voltage that needs to be applied to each sub-pixel through the shared data line when driven according to the first preset cycle. Referring to Table 1, Table 1 is an example table of pixel voltage data corresponding to the output of each shared data line when driven according to the first preset cycle. As shown in Table 1, when n is equal to 1, Figure 2The pixel driving circuit shown drives according to a first preset cycle, i.e., simultaneously driving the second and third scan lines, then simultaneously driving the fourth and first scan lines, then simultaneously driving the fifth and eighth scan lines, and finally simultaneously driving the seventh and sixth scan lines. Specifically, when driving the second and third scan lines, for the shared data line S1, the pixel voltage data corresponding to the first green (G) sub-pixel in the first row needs to be output, which is recorded as G11, and the pixel voltage data corresponding to the first green (G) sub-pixel in the second row needs to be output, which is recorded as G21, where G11 = G21. For the shared data line S2, the pixel voltage data corresponding to the second red (R) sub-pixel in the first row needs to be output, which is recorded as R12, and the pixel voltage data corresponding to the second red (R) sub-pixel in the second row needs to be output, which is recorded as R22, where R12 = R22. For shared data line S3, the pixel voltage data corresponding to the second blue (B) subpixel in row 1 is output as B12, and the pixel voltage data corresponding to the second blue (B) subpixel in row 2 is output as B22, where B12 = B22. When driving scan lines 4 and 1, for shared data line S1, the pixel voltage data corresponding to the first red (R) subpixel in row 2 is output as R21, and the pixel voltage data corresponding to the first red (R) subpixel in row 1 is output as R11, where R21 = R11. For shared data line S2, the pixel voltage data corresponding to the first blue (B) subpixel in row 2 is output as B21, and the pixel voltage data corresponding to the first blue (B) subpixel in row 1 is output as B11, where B21 = B11. For shared data line S3, the pixel voltage data corresponding to the second green (G) sub-pixel in row 2 is output, denoted as G22, and the pixel voltage data corresponding to the second green (G) sub-pixel in row 1 is output, denoted as G12, where G22 = G12. Simultaneously driving scan lines 5 and 8, and scan lines 7 and 6, corresponds to the shared data shown in Table 1, and corresponding pixel voltage data is output.

[0074] Table 1 Example of pixel voltage data outputted by each shared data line when driven according to the first preset cycle

[0075] S1 S2 S3 When driving the second scan line G11 R12 B12 When driving the third scan line G21 R22 B22 When driving the 4th scan line R21 B21 G22 When driving the first scan line R11 B11 G12 When driving the 5th scan line G31 R32 B32 When driving the 8th scan line G41 R42 B42 When driving the 7th scan line R41 B41 G42 When driving the 6th scan line R31 B31 G32

[0076] As shown in Table 1, in the embodiment of the present application, when the pixel driving circuit drives two rows simultaneously according to the first preset period, each shared data line outputs a corresponding pixel voltage of the same color. In other words, the pixel driving voltage provided in the embodiment of the present application can achieve the DLG function by driving according to the first preset period.

[0077] In step S430 , a pixel voltage is applied to the shared data line in synchronization with the scan pulse to drive each sub-pixel.

[0078] In the embodiment of the present application, after determining the pixel voltage to be applied to each sub-pixel via each shared data line, the corresponding pixel voltage is applied to the corresponding shared data line in synchronization with the scan pulse to drive each sub-pixel. For example, when driving the second and third rows of scan lines simultaneously, while the scan line driver module simultaneously and separately transmits the same scan pulse to the second and third rows of scan lines, the timing control module outputs pixel voltage data for G11 and G21 via the shared data line S1, pixel voltage data for R12 and R22 via the shared data line S2, and pixel voltage data for B12 and B22 via the shared data line S3.

[0079] In the embodiment of the present application, the pixel driving circuit provided in any embodiment of the present application is driven according to the first preset period to realize the DLG function.

[0080] In one embodiment of the present application, referring to Figure 6 , Figure 6 It is a flowchart of steps performed after determining the first preset period provided by an embodiment of the present application, including but not limited to steps S610 to S620.

[0081] Step S610, generating a corresponding driving timing signal according to the driving sequence determined in the first preset period;

[0082] Step S620 , providing a scan pulse to the scan line according to the driving timing signal.

[0083] In the embodiment of the present application, a first preset driving cycle is first determined based on the DLG driving requirements. The timing control module then generates corresponding driving timing signals based on the driving sequence determined in the first preset cycle and transmits them to the scan line driver module. The scan line driver module then provides corresponding scan pulses to the scan lines based on the driving timing signals.

[0084] It should be noted that in the embodiments of the present application, to meet the timing requirements corresponding to the drive sequence, the timing control module can use a multi-input multi-output shifter / level converter (lever shift), and each clock signal CK can be independently controlled and generated by the timing control module (TCON). This can also be achieved by changing the connection method corresponding to the shared data line in the plane.

[0085] In one embodiment of the present application, referring to Figure 7 , Figure 7This is another flow chart of a driving method provided in an embodiment of the present application, which is used to drive a pixel driving circuit provided in any embodiment of the present application. The method includes but is not limited to steps S710 to S740.

[0086] Step S710, providing scan pulses to the scan lines according to a second preset cycle, wherein the second preset cycle is to drive the n+1th scan line, the n+2th scan line, the n+3th scan line, the nth scan line, the n+4th scan line, the n+7th scan line, the n+6th scan line and the n+5th scan line row by row in sequence.

[0087] In the embodiment of the present application, the scan line driving module provides a scan pulse to the scan line according to the second preset period. Figure 8 , Figure 8 This is a timing diagram corresponding to the second preset period driving provided by the embodiment of the present application. After the scan line driving module receives the first driving signal, the scan line driving module sends a signal to the n+1th row of scan lines. Figure 8 The driving voltage waveform signal (i.e., scanning pulse) corresponding to G1 is shown in FIG. After the scanning line driving module receives the second driving signal, the scanning line driving module sends a signal to the n+2th row scanning line. Figure 8 After receiving the third driving signal, the scanning line driving module sends a driving voltage waveform signal to the n+3th row scanning line. Figure 8 The driving voltage waveform signal corresponding to G3 is shown in FIG. After the scanning line driving module receives the first driving signal, the scanning line driving module sends a signal to the nth row scanning line. Figure 8 The driving voltage waveform signal corresponding to G4 is shown in FIG. After the scanning line driving module receives the fifth driving signal, the scanning line driving module sends a signal to the n+4th row scanning line. Figure 8 The driving voltage waveform signal corresponding to G5 is shown in FIG. After the scanning line driving module receives the sixth driving signal, the scanning line driving module sends a signal to the n+7th row scanning line. Figure 8 After receiving the seventh driving signal, the scanning line driving module sends a driving voltage waveform signal to the n+6th row scanning line. Figure 8 The driving voltage waveform signal corresponding to G7 is shown in FIG. After the scanning line driving module receives the eighth driving signal, the scanning line driving module sends a signal to the n+5th row scanning line. Figure 8 The driving voltage waveform signal corresponding to G8 is shown in FIG. Among them, the driving voltage waveform signals corresponding to G1, G2, G3, G4, G5, G6, G7 and G8 are different.

[0088] Step S720 , determining the pixel voltage applied to each sub-pixel through the shared data line according to the data to be displayed and the connection relationship between each sub-pixel and the scan line and the shared data line.

[0089] In the embodiment of the present application, the timing control module reorganizes the pixel voltage data provided by the SOC (system on chip) based on the connection relationship between each sub-pixel and the scan line and the shared data line in the pixel driving circuit to determine the pixel voltage that needs to be applied to each sub-pixel through the shared data line when driving according to the second preset cycle. Referring to Table 2, Table 2 is an example table of pixel voltage data corresponding to the output of each shared data line when driving according to the second preset cycle. As shown in Table 2, when n is equal to 1, for Figure 2 The pixel driving circuit shown is driven according to a second preset cycle, that is, driving the second scan line, the third scan line, the fourth scan line, the first scan line, the fifth scan line, the eighth scan line, the seventh scan line, and the sixth scan line row by row. Specifically, when driving the second scan line, for the shared data line S1, it needs to output the pixel voltage data corresponding to the first green (G) sub-pixel in the first row, which is recorded as G11. For the shared data line S2, it needs to output the pixel voltage data corresponding to the second red (R) sub-pixel in the first row, which is recorded as R12. For the shared data line S3, it needs to output the pixel voltage data corresponding to the second blue (B) sub-pixel in the first row, which is recorded as B12. When driving the third scan line, for the shared data line S1, it needs to output the pixel voltage data corresponding to the first green (G) sub-pixel in the second row, which is recorded as G21. For the shared data line S2, the pixel voltage data corresponding to the second red (R) sub-pixel in the second row needs to be output, recorded as R22. For the shared data line S3, the pixel voltage data corresponding to the second blue (B) sub-pixel in the second row needs to be output, recorded as B22. When driving the 4th row of scan lines, for the shared data line S1, the pixel voltage data corresponding to the first red (R) sub-pixel in the second row needs to be output, recorded as R21. For the shared data line S2, the pixel voltage data corresponding to the first blue (B) sub-pixel in the second row needs to be output, recorded as B21. For the shared data line S3, the pixel voltage data corresponding to the second green (G) sub-pixel in the second row needs to be output, recorded as G22. When driving the 1st row of scan lines, for the shared data line S1, the pixel voltage data corresponding to the first red (R) sub-pixel in the first row needs to be output, recorded as R11. For shared data line S2, the pixel voltage data corresponding to the first blue (B) sub-pixel in row 1 needs to be output, denoted as B11. For shared data line S1, the pixel voltage data corresponding to the second green (G) sub-pixel in row 1 needs to be output, denoted as G12. Simultaneously, the 5th, 8th, 7th, and 6th scan lines are driven, and each of the shared data shown in Table 2 has corresponding pixel voltage data to be output.

[0090] Table 2 Example of pixel voltage data outputted by each shared data line when driven according to the second preset cycle

[0091] S1 S2 S3 When driving the second scan line G11 R12 B12 When driving the third scan line G21 R22 B22 When driving the 4th scan line R21 B21 G22 When driving the first scan line R11 B11 G12 When driving the 5th scan line G31 R32 B32 When driving the 8th scan line G41 R42 B42 When driving the 7th scan line R41 B41 G42 When driving the 6th scan line R31 B31 G32

[0092] As shown in Table 2, in the embodiment of the present application, when the pixel driving circuit is driven according to the second preset period, each shared data line outputs a corresponding different pixel voltage.

[0093] In step S730 , the polarity of the pixel voltage applied to each sub-pixel is determined according to the polarity inversion setting of the two rows.

[0094] In the embodiment of the present application, while driving the pixel driving circuit according to the second preset cycle, a 2-line inversion polarity setting is also used to determine the polarity of the pixel voltage applied to each sub-pixel. Figure 9 , Figure 9 : is a schematic diagram of the structure of the pixel driving circuit with polarity shown in the embodiment of the present application. Figure 9 As shown, the first column array is arranged in a "++--++--" cyclic pattern with two rows reversed vertically. The second column array has the exact opposite polarity to the first, forming "--++--++". The third column array has two rows reversed vertically, forming a "--++--++" cyclic pattern. The fourth column array has the exact opposite polarity to the third, forming "++--++--".

[0095] In step S740 , a pixel voltage with a polarity is applied to the shared data line in synchronization with the scan pulse to drive each sub-pixel.

[0096] In the embodiment of the present application, a pixel voltage with polarity is applied to the shared data line synchronously with the scan pulse to drive each sub-pixel, thereby utilizing the inherent defect of insufficient charging when switching between positive and negative polarities to achieve the EVA effect.

[0097] Specifically, taking shared data line S1 as an example, combined with Table 2, the data output by S1 is G11(-), G21(-), R21(+), R11(+), G31(+), G41(+), R41(-), and R31(-). That is, the output polarity of shared data line S1 follows a "--++++--" cycle. From G11 to G21, it's negative polarity to negative polarity, and the G11 voltage can actively control dimming. However, when switching from G21 to R21, due to the polarity reversal, R21 is undercharged, which just meets the EVA (wide viewing angle) requirement (R21 is dimmed). Similarly, as long as there is a polarity switch, there will be undercharging, which just meets the EVA requirement.

[0098] In the embodiments of this application, the principle of EVA (Extended Viewing Angle) is to present different grayscale brightness levels on adjacent sub-pixels, for example, controlling odd-numbered sub-pixels to be brighter and even-numbered sub-pixels to be darker, and so on. The pixel driving circuit proposed in any embodiment of this application is driven according to a second predetermined period and employs a two-row inversion setting. This eliminates the need for active voltage adjustment and instead utilizes the inherent defect of insufficient charging during positive and negative polarity switching to achieve the EVA effect.

[0099] In one embodiment of the present application, referring to Figure 10 , Figure 10 This is a flowchart of the steps for driving the first pixel group provided in an embodiment of the present application, including but not limited to steps S1010 to S1040.

[0100] Step S1010 , providing a scan pulse to the (n+1)th scan line, and applying a second pixel voltage having a first polarity to the second sub-pixel through the shared data line;

[0101] Step S1020, providing a scan pulse to the (n+2)th scan line, and applying a fourth pixel voltage having a first polarity to the fourth sub-pixel through the shared data line;

[0102] Step S1030, providing a scan pulse to the (n+3)th scan line, and applying a third pixel voltage having a second polarity to the third sub-pixel through the shared data line, wherein the first polarity and the second polarity are opposite polarities;

[0103] Step S1040 , providing a scan pulse to the n-th scan line, and applying a first pixel voltage with a second polarity to the first sub-pixel through the shared data line.

[0104] In an embodiment of the present application, driving each subpixel includes driving a first pixel group. The first pixel group includes a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel. Driving the pixel driving circuit according to a second preset cycle includes sequentially driving the n+1th scan line, the n+2th scan line, the n+3th scan line, and the nth scan line. Thus, when driving the n+1th scan line, a scan pulse is provided to the n+1th scan line, and a second pixel voltage having a first polarity is applied to the second subpixel via a shared data line. When driving the n+2th scan line, a scan pulse is provided to the n+2th scan line, and a fourth pixel voltage having a first polarity is applied to the fourth subpixel via the shared data line. When driving the n+3th scan line, a scan pulse is provided to the n+3th scan line, and a third pixel voltage having a second polarity is applied to the third subpixel via the shared data line. When driving the nth scan line, a scan pulse is provided to the nth scan line, and a first pixel voltage having a second polarity is applied to the first subpixel via the shared data line. The first polarity and the second polarity are opposite polarities. For example, when the first polarity is positive, the second polarity is negative. And when the first polarity is negative, the second polarity is negative.

[0105] In the embodiment of the present application, by setting two rows of polarity inversion, it is ensured that the polarities of the first and second sub-pixels distributed on both sides of the shared data line are opposite, and the polarities of the third and fourth sub-pixels distributed on both sides of the shared data line are opposite. However, the polarities of the first and third sub-pixels distributed in the same column array and adjacent to each other are the same, and the polarities of the second and fourth sub-pixels distributed in the same column array and adjacent to each other are the same. This ensures uniform pixel polarity distribution.

[0106] In one embodiment of the present application, referring to Figure 11 , Figure 11 This is a flowchart of the steps for driving the first pixel group provided in an embodiment of the present application, including but not limited to steps S1110 to S1140.

[0107] Step S1110 , providing a scan pulse to the (n+4)th scan line, and applying a sixth pixel voltage having a second polarity to the sixth sub-pixel through the shared data line;

[0108] Step S1120 , providing a scan pulse to the (n+7)th scan line, and applying an eighth pixel voltage having a second polarity to the eighth sub-pixel through the shared data line;

[0109] Step S1130 , providing a scan pulse to the (n+6)th scan line, and applying a seventh pixel voltage having a first polarity to the seventh sub-pixel through the shared data line, wherein the second polarity is opposite to the first polarity;

[0110] In step S1140 , a scan pulse is provided to the (n+5)th scan line, and a fifth pixel voltage having a first polarity is applied to the fifth sub-pixel through the shared data line.

[0111] In an embodiment of the present application, driving each subpixel includes driving a second pixel group. The second pixel group includes a fifth subpixel, a sixth subpixel, a seventh subpixel, and an eighth subpixel. When driving the pixel driving circuit according to a second preset cycle, the process includes sequentially driving the n+4th scan line, the n+7th scan line, the n+6th scan line, and the n+5th scan line. Thus, when driving the n+4th scan line, a scan pulse is provided to the n+4th scan line, and a sixth pixel voltage having a second polarity is applied to the sixth subpixel via the shared data line. When driving the n+7th scan line, a scan pulse is provided to the n+7th scan line, and an eighth pixel voltage having a second polarity is applied to the eighth subpixel via the shared data line. When driving the n+6th scan line, a scan pulse is provided to the n+6th scan line, and a seventh pixel voltage having a first polarity is applied to the seventh subpixel via the shared data line. When driving the n+5th scan line, a scan pulse is provided to the n+5th scan line, and a fifth pixel voltage having a first polarity is applied to the fifth subpixel via the shared data line. The first polarity and the second polarity are opposite polarities. For example, when the first polarity is positive, the second polarity is negative. Conversely, when the first polarity is negative, the second polarity is negative.

[0112] In the embodiment of the present application, by setting two rows of polarity inversion, the fifth and sixth sub-pixels distributed on either side of a shared data line have opposite polarities, as do the seventh and eighth sub-pixels distributed on either side of the shared data line. However, the fifth and seventh sub-pixels distributed in the same column array and adjacent to each other have the same polarity, as do the sixth and eighth sub-pixels distributed in the same column array and adjacent to each other. This ensures uniform pixel polarity distribution.

[0113] The present application also provides a display device, including:

[0114] A display panel, the display panel comprising the pixel driving circuit provided by any embodiment of the present application;

[0115] The timing control module is connected to the display panel and is used to execute the driving method provided in any embodiment of the present application to drive the pixel driving circuit.

[0116] Since the display device provided in the embodiment of the present application includes a display panel and a timing control module, and the display panel includes the pixel driving circuit provided in any embodiment of the present application, the timing control module can execute the driving method provided in any embodiment of the present application, so that the display device of the present application can be applied to GLD driving scenarios and EVA driving scenarios.

[0117] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0118] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0119] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0120] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0121] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0122] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0123] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0124] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0126] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0127] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A pixel driving circuit, characterized in that: comprising a first pixel group and a second pixel group alternately arranged along a column direction, wherein the first pixel group and the second pixel group are both connected to the same shared data line; The first pixel group includes a first row array and a second row array adjacent to each other in the column direction, the first row array includes a first sub-pixel and a second sub-pixel alternately arranged in the row direction, the second row array includes a third sub-pixel and a fourth sub-pixel alternately arranged in the row direction, the first sub-pixel is connected to the nth row scan line, the second sub-pixel is connected to the n+1th row scan line, the third sub-pixel is connected to the n+3th row scan line, and the fourth sub-pixel is connected to the n+2th row scan line; The second pixel group includes a third row array and a fourth row array adjacent to each other in the column direction, the third row array includes a fifth sub-pixel and a sixth sub-pixel alternately arranged in the row direction, the fourth row array includes a seventh sub-pixel and an eighth sub-pixel alternately arranged in the row direction, the fifth sub-pixel is connected to the (n+5)th scan line, the sixth sub-pixel is connected to the (n+4)th scan line, the seventh sub-pixel is connected to the (n+6)th scan line, and the eighth sub-pixel is connected to the (n+7)th scan line, where n is a natural number greater than or equal to 1; The first sub-pixel, the third sub-pixel, the fifth sub-pixel, and the seventh sub-pixel are sequentially arranged along a column direction to form a first column array, and the second sub-pixel, the fourth sub-pixel, the sixth sub-pixel, and the eighth sub-pixel are sequentially arranged along a column direction to form a second column array. The shared data line is arranged to intersect with each of the scan lines. The shared data line passes through a position between the first column array and the second column array and is connected to each sub-pixel in the first column array and the second column array. The sub-pixels in the same column array have the same color; The first row array includes a plurality of the first sub-pixels and a plurality of the second sub-pixels arranged alternately, the second row array includes a plurality of the third sub-pixels and a plurality of the fourth sub-pixels arranged alternately, the third row array includes a plurality of the fifth sub-pixels and a plurality of the sixth sub-pixels arranged alternately, and the fourth row array includes a plurality of the seventh sub-pixels and a plurality of the eighth sub-pixels arranged alternately, the pixel driving circuit correspondingly forms a plurality of the first column arrays and a plurality of the second column arrays arranged alternately along the row direction, and the pixel driving circuit is provided with a plurality of the shared data lines arranged alternately along the row direction, the shared data lines passing through positions between the corresponding first column arrays and the second column arrays; Any two adjacent sub-pixels in each row array have different colors; The pixel driving circuit is configured to drive with a first preset cycle, and the preset cycle is to sequentially and simultaneously drive the n+1th scan line and the n+2th scan line, the n+3th scan line and the nth scan line, the n+4th scan line and the n+7th scan line, and the n+6th scan line and the n+5th scan line.

2. A driving method for driving the pixel driving circuit according to claim 1, characterized in that: The driving method includes: providing scan pulses to the scan lines according to a first preset period, wherein the first preset period sequentially and simultaneously drives the scan line (n+1) and the scan line (n+2), the scan line (n+3) and the scan line (n), the scan line (n+4) and the scan line (n+7), and the scan line (n+6) and the scan line (n+5); determining a pixel voltage applied to each of the sub-pixels through the shared data line according to a connection relationship between each of the sub-pixels and the scan line and the shared data line; The pixel voltage is applied to the shared data line in synchronization with the scan pulse to drive each of the sub-pixels.

3. The method according to claim 2, characterized in that After determining the first preset period, the method includes: Generate a corresponding driving timing signal according to the driving sequence determined by the first preset period; A scan pulse is provided to the scan line according to the driving timing signal.

4. A driving method for driving the pixel driving circuit according to claim 1, characterized in that: The driving method includes: providing scan pulses to the scan lines according to a second preset period, wherein the second preset period sequentially drives the (n+1)th scan line, the (n+2)th scan line, the (n+3)th scan line, the (n)th scan line, the (n+4)th scan line, the (n+7)th scan line, the (n+6)th scan line, and the (n+5)th scan line; determining a pixel voltage applied to each of the sub-pixels through the shared data line according to a connection relationship between each of the sub-pixels and the scan line and the shared data line; determining the polarity of the pixel voltage applied to each of the sub-pixels according to two-row polarity inversion settings; A pixel voltage with a polarity is applied to the shared data line in synchronization with the scan pulse to drive each of the sub-pixels.

5. The method according to claim 4, characterized in that Driving each of the sub-pixels includes driving the first pixel group, and driving the first pixel group includes performing the following steps in sequence: providing a scan pulse to the (n+1)th scan line, and applying a second pixel voltage having a first polarity to the second sub-pixel through the shared data line; providing a scan pulse to the (n+2)th scan line, and applying a fourth pixel voltage having the first polarity to the fourth sub-pixel through the shared data line; providing a scan pulse to the (n+3)th scan line, and applying a third pixel voltage having a second polarity to the third sub-pixel through the shared data line, wherein the first polarity and the second polarity are opposite polarities; A scan pulse is provided to the n-th scan line, and a first pixel voltage having the second polarity is applied to the first sub-pixel through the shared data line.

6. The method according to claim 5, characterized in that Driving each of the sub-pixels includes driving the second pixel group, and driving the second pixel group includes performing the following steps in sequence: providing a scan pulse to the (n+4)th scan line, and applying a sixth pixel voltage having a second polarity to the sixth sub-pixel through the shared data line; providing a scan pulse to the (n+7)th scan line, and applying an eighth pixel voltage having the second polarity to the eighth sub-pixel through the shared data line; providing a scan pulse to the (n+6)th scan line, and applying a seventh pixel voltage having a first polarity to the seventh sub-pixel through the shared data line, wherein the second polarity is opposite to the first polarity; A scan pulse is provided to the (n+5)th scan line, and a fifth pixel voltage having the first polarity is applied to the fifth sub-pixel through the shared data line.

7. A display device, characterized in that: include: A display panel, the display panel comprising the pixel driving circuit according to claim 1; A timing control module is connected to the display panel and is used to execute the driving method according to any one of claims 2 to 6 to drive the pixel driving circuit.

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