A FPGA upgrading method applied to 250kVA energy router
By using a communication architecture of host computer + DSP + FPGA and EMIF interface, combined with dual compression mirror design and power-on self-verification scheme, the problem of needing to open the cover for FPGA upgrades is solved, realizing convenient upgrades and stable operation of the equipment.
CN117193814BActive Publication Date: 2026-07-24STATE GRID FUJIAN ELECTRIC POWER CO LTD +1
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STATE GRID FUJIAN ELECTRIC POWER CO LTD
- Filing Date
- 2023-07-12
- Publication Date
- 2026-07-24
AI Technical Summary
Technical Problem
Existing FPGA upgrade methods require opening the cover, which affects the maintainability of the equipment, and the equipment cannot operate normally if the program is damaged.
Method used
The communication architecture adopts a host computer + DSP + FPGA, and the FPGA upgrade process is simplified through the EMIF interface. The dual compression image design and power-on self-verification scheme are used to ensure the stability and reliability of the program.
Benefits of technology
It enables convenient FPGA program upgrades without opening the cover, ensuring that the device can still operate normally when the program is damaged, thus improving the maintainability and reliability of the device.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN117193814B_ABST
Abstract
The application provides an FPGA upgrading method applied to a 250kVA energy router, and the upgrading method realizes the upgrading process of the FPGA to be convenient through a communication architecture of a host computer + DSP + FPGA, and steps are as follows: step S1, FPGA upgrading data packets of the router are imported into the host computer; step S2, the host computer issues an upgrading instruction and the upgrading data packets to the router DSP for temporary storage; step S3, the DSP issues the upgrading instruction to the FPGA to upgrade the FPGA function; and step S4, after the FPGA receives the upgrading instruction and the upgrading data packets issued by the DSP through an EMIF interface, the FPGA starts to operate a flash device of the FPGA to complete the upgrading operation; the application is an FPGA upgrading scheme applied to a DSP + FPGA control architecture, the FPGA program updating can be more convenient without increasing additional hardware resources, the device does not need to be opened, and after a program image is damaged, another image can be automatically loaded to continue to keep the device to work normally.
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