An exception processing method, an exception processing device, a terminal, and a storage medium

Abstract

The application discloses an abnormality processing method, an abnormality processing device, a terminal and a storage medium, and is applied to the terminal. The terminal comprises a main controller, a main relay for controlling the power supply of the main controller, a backup controller with the same function as the main controller, a main storage chip and a backup storage chip. The method comprises the following steps: in the case that the terminal is powered on and fails to write data to the main storage chip through the main controller, generating a first control signal through the backup controller and sending the first control signal to the main relay, wherein the first control signal is used for resetting the main controller; responding to the first control signal through the main relay to reset the main controller; judging whether the main controller can write data to the main storage chip, if not, switching the main storage chip to the backup storage chip through the backup controller, and accessing the backup storage chip through the main controller to read or write data.

Description

Technical Field

[0001] This application relates to the field of communications, and in particular to an anomaly handling method, an anomaly handling device, a terminal, and a storage medium. Background Technology

[0002] With the increasing demand for Internet of Things (IoT) terminals, IoT technology has experienced unprecedented development, giving rise to a series of IoT terminal products. Due to their extremely wide range of applications, such as smart wearables, smart metering, smart home appliances, connected vehicles, security monitoring, and military applications, IoT terminals face stringent requirements for stability and security. However, during long-term use, the applications and / or storage chips of IoT terminals inevitably encounter various problems as operating time increases. In the most severe cases, this can even lead to system crashes, causing work stoppages and the loss of important data. Summary of the Invention

[0003] This application provides an exception handling method, an exception handling device, a terminal, and a storage medium.

[0004] The technical solution of this application is implemented as follows:

[0005] This application provides an exception handling method applied to a terminal, the terminal including a main controller, a main relay for controlling the power supply of the main controller, a backup controller having the same function as the main controller, a main storage chip, and a backup storage chip, the method including:

[0006] If the terminal is powered on and writing data to the main storage chip through the main controller fails, the backup controller generates a first control signal and sends the first control signal to the main relay, wherein the first control signal is used to reset the main controller;

[0007] The main controller is reset by responding to the first control signal via the main relay; it is determined whether the main controller can write data to the main memory chip. If not, the main memory chip is switched to the backup memory chip via the backup controller, and the backup memory chip is accessed by the main controller to read or write data.

[0008] This application provides an anomaly handling device, the device comprising: a main controller, a main relay for controlling the power supply of the main controller, a backup controller having the same function as the main controller, a main storage chip, and a backup storage chip, wherein...

[0009] The backup controller is configured to generate a first control signal and send the first control signal to the main relay when the abnormal handling device is powered on and the main controller fails to write data to the main memory chip, wherein the first control signal is used to reset the main controller;

[0010] The main relay is used to respond to the first control signal to reset the main controller;

[0011] The backup controller is also used to determine whether the main controller can write data to the main storage chip. If not, the backup controller switches the main storage chip to the backup storage chip and accesses the backup storage chip to read or write data.

[0012] This application provides a terminal, the terminal comprising:

[0013] Memory, used to store executable instructions;

[0014] A processor is configured to execute executable instructions stored in the memory to implement the exception handling method described above.

[0015] This application provides a storage medium that stores one or more programs, which can be executed by one or more processors to implement the exception handling method described above.

[0016] This application provides an anomaly handling method, an anomaly handling device, a terminal, and a storage medium. When the terminal is powered on and writing data to the main storage chip via the main controller fails, a backup controller generates a first control signal and sends it to a main relay. The first control signal is used to reset the main controller. The main relay responds to the first control signal to reset the main controller. It is then determined whether the main controller can write data to the main storage chip. If not, the backup controller switches the main storage chip to the backup storage chip, and the main controller accesses the backup storage chip to read or write data. This application employs a multi-mode redundancy design for the storage chip. Even if one storage chip completely fails, the backup controller and main relay switch the main storage chip to the backup storage chip, and the main controller accesses the backup storage chip to read or write data. This achieves self-processing and self-recovery of storage chip failures, improving the reliability and stability of the terminal. Attached Figure Description

[0017] Figure 1 A flowchart illustrating an optional exception handling method provided in an embodiment of this application;

[0018] Figure 2A flowchart illustrating an optional exception handling method provided in an embodiment of this application;

[0019] Figure 3 A structural block diagram of the hardware circuit of the terminal provided in the embodiments of this application;

[0020] Figure 4 A flowchart illustrating an optional exception handling method provided in an embodiment of this application;

[0021] Figure 5 A schematic diagram of an optional Flash redundancy design hardware circuit provided for an embodiment of this application;

[0022] Figure 6 A schematic diagram of a switching circuit for different data transmission paths in an optional GPS module provided in an embodiment of this application;

[0023] Figure 7 This is a schematic diagram of an optional terminal provided in an embodiment of this application. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0025] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] See Figure 1 , Figure 1This is a schematic diagram of an implementation flow of the exception handling method provided in this application embodiment. The exception handling method is applied to a terminal, which includes a main controller, a main relay for controlling the power supply of the main controller, a backup controller with the same function as the main controller, a main storage chip, and a backup storage chip. The exception handling method includes the following steps:

[0028] Step 101: If the terminal is powered on and the main controller fails to write data to the main storage chip, the backup controller generates a first control signal and sends the first control signal to the main relay.

[0029] The first control signal is used to reset the main controller.

[0030] In this embodiment of the application, the process of powering on the terminal can be understood as follows: after the terminal is connected to an external power source and the terminal power button is turned on, i.e., the terminal is powered on, an electrical signal is emitted, indicating that the power supply is starting normally and working stably. At this time, the terminal is powered on.

[0031] In this embodiment, the terminal includes at least two controllers, at least two relays for controlling the power supply of the controllers, and at least two memory chips. The controllers control various components within the terminal, and the relays are automatic switches that use a small current to control a large current, providing isolation protection and automatic switching. It should be noted that the functions and roles of the at least two controllers are identical, and the functions and roles of the at least two relays are also identical. Here, we will use two controllers and two relays, with one controller being the main controller and the other a backup controller; the relay controlling the power supply of the main controller is the main relay, and the relay controlling the power supply of the backup controller is the backup relay.

[0032] In this embodiment, the memory chip can be a flash memory chip, which is a non-volatile storage medium that retains its on-chip information even after the external power supply is turned off. The flash memory chip includes, but is not limited to, NOR flash and NAND flash. NOR flash can store a small amount of code, and the program can run directly within the flash chip without needing to read the code into the system RAM; additionally, NOR flash has high data transfer efficiency and fast read speed. NAND flash can provide extremely high cell density, achieving high storage density, and also has fast write and erase speeds; furthermore, as a non-volatile storage medium, NAND flash uses semiconductors as the memory carrier, making it more resistant to temperature changes, mechanical vibrations, and shocks than traditional storage devices, resulting in higher reliability and easier implementation of high-speed, low-power storage systems.

[0033] In this embodiment, the failure of the terminal to write data to the storage chip via the controller may be due to the following situations: 1. The controller fails when the application in the terminal freezes, crashes, or enters an infinite loop; 2. The controller malfunctions; 3. The storage chip in the terminal has bad blocks or is faulty. Therefore, the failure of the main controller to write data to the main storage chip may be due to the main controller failing when the application freezes, crashes, or enters an infinite loop, or the main controller malfunctions, or the main storage chip has bad blocks or is faulty.

[0034] In practical applications, terminals can include, but are not limited to, mobile terminals such as smartphones, tablets, laptops, smart TVs, personal digital assistants (PDAs), cameras, and wearable devices, as well as fixed terminals such as desktop computers.

[0035] Step 102: Reset the main controller by responding to the first control signal through the main relay.

[0036] In this embodiment, when the terminal is powered on and writing data to the main storage chip through the main controller fails, and it is uncertain whether the fault lies with the main controller or the main storage chip, a first control signal for resetting the main controller is first generated by the backup controller and sent to the main relay. Furthermore, the terminal responds to the first control signal through the main relay, thereby controlling the power supply of the main controller to be turned off and on, thereby resetting the main controller. This allows it to determine whether the main controller can write data to the main storage chip after the main controller is reset.

[0037] Step 103: Determine whether the main controller can write data to the main storage chip. If not, switch the main storage chip to the backup storage chip through the backup controller, and access the backup storage chip through the main controller to read or write data.

[0038] In this embodiment, after resetting the main controller, the terminal further determines whether the main controller can write data to the main storage chip. If the main controller still fails to write data to the main storage chip, and it is determined that the main storage chip has bad blocks or has failed, the backup controller is activated to switch the main storage chip to the backup storage chip. The main controller then accesses the backup storage chip to read or write data. This avoids the problem of the system failing when the storage chip fails, achieving a redundant design for the storage chip. In the event of a complete failure of one storage chip, fault self-processing and self-recovery are performed, resulting in high reliability, security, and stability. If the main controller can write data to the main storage chip, it is determined that the main controller has automatically recovered from the fault after being reset, and therefore, it can continue to access the backup storage chip to read or write data. Thus, by resetting the controller, fault self-processing and self-recovery are achieved.

[0039] This application provides an anomaly handling method. When the terminal powers on and fails to write data to the main storage chip via the main controller, a first control signal is generated by a backup controller and sent to the main relay. This first control signal is used to reset the main controller. The main relay responds to the first control signal to reset the main controller. It is then determined whether the main controller can write data to the main storage chip. If not, the backup controller switches the main storage chip to the backup storage chip, and the main controller accesses the backup storage chip to read or write data. This application employs a multi-mode redundancy design for the storage chip. Even if one storage chip completely fails, the backup controller and main relay switch the main storage chip to the backup storage chip, and the main controller accesses the backup storage chip to read or write data. This achieves self-handling and self-recovery of storage chip failures, improving the reliability and stability of the terminal.

[0040] See Figure 2 , Figure 2 This is a schematic diagram of an implementation flow of the exception handling method provided in this application embodiment. This exception handling method is applied to a terminal. (Refer to...) Figure 3 As shown, Figure 3This is a structural block diagram of the hardware circuit of a terminal provided in an embodiment of this application. The terminal includes an external power supply, a main controller, a main relay for controlling the power supply of the main controller, a backup controller with the same function as the main controller, a main storage chip and a backup storage chip, a main power module providing power to the main controller (located between the main relay and the main controller), a backup power module providing power to the backup controller, a backup relay for controlling the power supply of the backup controller (located between the backup relay and the backup controller), and a first switch module. The input terminals of the first switch module are connected to the main controller and the backup controller, respectively, and the output terminals of the first switch module are connected to the main storage chip and the backup storage chip, respectively. The fault handling method includes the following steps:

[0041] Step 201: If the terminal is powered on and the main controller fails to write data to the main storage chip, the backup controller generates a first control signal and sends the first control signal to the main relay.

[0042] The first control signal is used to reset the main controller.

[0043] In this embodiment of the application, regarding the process before the backup controller generates the first control signal in step 201 when the terminal is powered on and writing data to the main memory chip fails through the main controller, the process is combined with... Figure 4 To provide further explanation,

[0044] Step 301: With both the main controller and the backup controller powered on, the backup controller performs a heartbeat detection on the main controller and obtains the detection result.

[0045] In this embodiment, heartbeat detection is used to determine whether the controller has malfunctioned.

[0046] In this embodiment, after both the main controller and the backup controller are powered on, both the main relay and the backup relay are in the normally open state. The main controller and the backup controller communicate with each other through a full-duplex communication bus such as a Serial Peripheral Interface (SPI). The main controller and the backup controller perform heartbeat detection and synchronize key data with each other, including heartbeat detection and key data synchronization of the main controller by the backup controller, and heartbeat detection and key data synchronization of the backup controller by the main controller.

[0047] In this embodiment of the application, the detection result can indicate that the data value of the online dictionary established by the backup controller and the main controller meets the threshold condition, that is, it indicates that the main controller has not failed. The detection result can also indicate that the data value of the online dictionary established by the backup controller does not meet the threshold condition, that is, it indicates that the main controller has failed.

[0048] In this embodiment of the application, the process of step 301, in which the backup controller performs heartbeat detection on the main controller and obtains the detection result when both the main controller and the backup controller are powered on and started, can be described as follows.

[0049] When the backup controller receives a heartbeat packet periodically sent by the master controller via the full-duplex communication bus, it updates the data value in the online dictionary established by the master controller to the preset data value and obtains the detection result.

[0050] If the backup controller does not receive a heartbeat packet within the second time period, it automatically increments the data value of the online dictionary until the incremented data value is greater than the data threshold, and then obtains the detection result.

[0051] Among them, the threshold conditions include data values ​​less than or equal to the data threshold, and heartbeat packets carrying key data of the terminal.

[0052] In this embodiment of the application, the data values ​​of the online dictionary established by the backup controller are used to determine the status of the main controller, where the status of the main controller includes fault status and normal status.

[0053] In this embodiment, the key data includes, but is not limited to, the terminal location, system time, the status of the main controller, and the value of at least one register. The key data carried in the heartbeat packet is designed to enable the terminal's system to recover quickly and facilitate normal system startup and loading.

[0054] In this embodiment, the key data is used by the backup controller to obtain the terminal's controller when the main controller fails, thereby quickly restoring the system in the terminal.

[0055] In one feasible application scenario, the main controller communicates with the backup controller via the SPI bus and periodically sends heartbeat packets to the backup controller. The backup controller establishes an online dictionary, updating its data value to 0 each time it receives a heartbeat packet from the main controller. Further, it is determined that the data value in the online dictionary established by the backup controller meets a threshold condition, confirming that the main controller is not faulty. If no heartbeat packet is received within a specified time, the data value in the dictionary will automatically accumulate. After a period of time, if the accumulated data value exceeds the data threshold, a fault is confirmed in the main controller. In this case, the backup controller outputs a first control signal to reset the main controller. If the main controller still shows a fault, the backup controller inherits the control authority of the main controller and outputs a third control signal to put the main relay in a normally closed state, thereby controlling the main power module to power off, and consequently, the main controller to power off. Here, the third control signal is used to switch the main relay from a normally open state to a normally closed state, thus achieving self-handling and self-recovery of controller faults.

[0056] In one implementation scenario, the instruction format of the heartbeat packet can be as shown in Table 1.

[0057]

[0058] Table 1

[0059] In some practical scenarios, for example, the frame header is 1 byte in size and is defined as 0xFF; the function code is 1 byte in size; if the function code is defined as 0x01, it indicates that this heartbeat packet is used to read data; if the function code is defined as 0x02, it indicates that this heartbeat packet is used to write data; the instruction length is 2 bytes in size, used to store the instruction format for updating the heartbeat packet; the data type is 2 bytes in size, here, the data type of all data can be arranged and defined according to the 0x format; the critical data is 2 bytes in size, and the critical data includes the terminal location, system time, device status, and the value of at least one register; the frame tail is 1 byte in size and is defined as 0xFE. For example, during terminal operation, if 0x01 is read, it indicates that the following 2 bytes are terminal location information.

[0060] In some embodiments, since both the main and backup controllers have separate power supply modules—that is, the main power supply module supplies power to the main controller and the backup power supply module supplies power to the backup controller—when both the main and backup controllers are powered on and started, they will mutually detect the voltage and / or current of each other's power supply modules. If the voltage and / or current data is abnormal, the system will immediately control the relay of the other controller to switch from the normally open state to the normally closed state, thereby disconnecting the power supply to the other controller's power supply module. This ensures that the system will not affect the other controller due to short circuits or burnout of components. The specific implementation process is as follows:

[0061] When both the main controller and the backup controller power on via the main power module, and the backup relay is in the normally open state, the main controller detects the first current and first voltage values ​​of the backup power module. If the first current value is greater than a first current threshold and / or the first voltage value is greater than a first voltage threshold, the main controller controls the backup relay to switch from the normally open state to the normally closed state to disconnect the backup power module. When both the main controller and the backup controller power on via the main power module, and the main relay is in the normally open state, the backup controller detects the second current and second voltage values ​​of the main power module. If the second current value is greater than a second current threshold and / or the second voltage value is greater than a second voltage threshold, the backup controller controls the main relay to switch from the normally open state to the normally closed state to disconnect the main power module. Thus, if a short circuit and / or burnout occurs in the power supply module of one controller, controlling the corresponding relay to be in the normally closed state ensures that the system in the terminal will not affect the other controller due to a short circuit and / or burnout.

[0062] Step 302: If the detection result indicates that the data value of the online dictionary established by the backup controller meets the threshold condition, continue to write data to the main storage chip through the main controller.

[0063] Step 303: If the detection result indicates that the data value in the backup controller does not meet the threshold condition, and the data value in the main controller still does not meet the threshold condition after resetting the main controller through the backup controller, then write data to the main memory chip through the backup controller.

[0064] In this embodiment, when both the main controller and the backup controller are powered on, the backup controller performs a heartbeat detection on the main controller. After obtaining the detection result, if the result indicates that the data values ​​in the online dictionary established by the backup controller for the main controller meet the threshold condition (i.e., the main controller is not faulty), data continues to be written to the main memory chip through the main controller. If the detection result indicates that the data values ​​in the online dictionary established by the backup controller do not meet the threshold condition (i.e., the main controller is faulty), and after resetting the main controller through the backup controller, if the data values ​​in the main controller still do not meet the threshold condition, the backup controller will inherit the control authority of the main controller. Data is written to the main storage chip by the backup controller; at the same time, the backup controller outputs a third control signal to control the main relay to be in a normally closed state, thereby controlling the main power module to shut down, and then controlling the main controller to shut down. Here, the third control signal is used to control the main relay to switch from a normally open state to a normally closed state. Thus, in this embodiment, the controller is hot-backed up, and heartbeat detection is performed between the main and backup controllers. In the event of a complete failure of the main controller, the backup controller will take over the control authority, perform fault self-handling and switching, and ensure that the terminal is not affected. At the same time, during the switching process between the main controller and the backup controller, the backup controller will also use heartbeat packets to enable the system to recover quickly.

[0065] Step 202: When the main controller is powered on and started through the main power module, the backup controller is powered on and started through the backup power module, and the main relay is in the normally open state, the main relay responds to the first control signal to control the main relay to switch from the normally open state to the normally closed state to disconnect the main power module.

[0066] In this embodiment of the application, the process of the controller starting up through the power module can be understood as follows: when the controller issues the first control command, it is determined that the controller has completed the power-on startup through the power module.

[0067] Step 203: When the main relay has been in the normally closed state for a certain period of time, the main relay is switched from the normally closed state to the normally open state by the backup controller to turn on the main power module and reset the main controller.

[0068] In this embodiment, the main controller powers on via the main power module, and the backup controller powers on via the backup power module. Both the main and backup relays are normally open. In this state, the main controller gains control of the system in the terminal, while the backup controller is in standby mode, also known as hot backup mode. Further, if the main controller fails to write data to the main storage chip, the backup controller determines that the main controller is not faulty through heartbeat detection. At this time, the backup controller generates a first control signal and sends it to the main relay. The main relay responds to the first control signal, switching from the normally open state to the normally closed state to disconnect the main power module. When the main relay remains in the normally closed state for a certain duration, the backup controller controls the main relay to switch from the normally closed state to the normally open state to turn on the main power module. This achieves a reset operation for the main controller.

[0069] Step 204: Determine whether the main controller can write data to the main memory chip. If not, output a second control signal through the backup controller.

[0070] The second control signal is used to switch the memory chip.

[0071] Step 205: Switch the main storage chip to the backup storage chip by responding to the second control signal through the first switch module.

[0072] In this embodiment, the first switching module consists of four single-pole triple-throw (SP3T) switches. The first switching module is used to respond to a second control signal, thereby enabling the switching of the memory chip.

[0073] In a feasible application scenario, taking a memory chip with three Flash modules as an example, since the main controller Flash module adopts a redundant design, refer to... Figure 5 As shown, Figure 5The diagram shows a hardware circuit schematic for a Flash redundancy design. The Flash uses SPI NAND Flash and has three signal interfaces: Chip Select (CS), Clock (CLK), and Input / Output (IO) interfaces, namely IO0, IO1, IO2, and IO3. When the master controller has control, if the primary Flash fails, the backup controller will use the master relay and the first switching module to switch the Flash. Specifically, the backup controller generates a second control signal and sends it to the first switching module. The first switching module responds to the second control signal, enabling autonomous switching between different Flash chips, thus achieving self-handling and self-recovery from faults. Here, the second control signal is represented by C1 and C2, where C1 is low (0) and high (1), C2 is low (0) and high (1). The functions of the first switching module are shown in Table 2.

[0074] C1 C2 Flash1 Flash2 Flash3 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1

[0075] Table 2

[0076] In Table 3 above, when C1 is 0 and C2 is 0, Flash1, Flash2, and Flash3 are all unusable (represented by 0); when C1 is 0 and C2 is 1, Flash2 can be used (represented by 1), while Flash1 and Flash3 are unusable (represented by 0); when C1 is 1 and C2 is 0, Flash1 can be used (represented by 1), while Flash2 and Flash3 are unusable (represented by 0); when C1 is 1 and C2 is 1, Flash3 can be used (represented by 1), while Flash1 and Flash3 are unusable (represented by 0). Thus, this embodiment employs a triple-modal redundancy design for Flash memory. In the event of a complete failure of one Flash memory chip, the primary storage chip can be switched to the backup storage chip via the backup controller and the first switching module. The primary controller can then access the backup storage chip to read or write data, thereby achieving self-processing and self-recovery of storage chip failures and improving the reliability and stability of the terminal.

[0077] Of course, the above function table is only one example. The functions of the second control signal and the first switch module can also be represented in other ways, as long as the autonomous switching between different memory chips can be guaranteed.

[0078] Step 206: Reset the main controller again through the backup controller so that the terminal can obtain key data from the backup controller and load it into the backup storage chip during operation, and access the backup storage chip through the main controller to read or write data.

[0079] In this embodiment, after the terminal resets the main controller via the backup controller, it determines whether the main controller can write data to the main storage chip. If the main controller fails to write data to the main storage chip, the backup controller outputs a second control signal for switching the storage chip. Then, the first switching module responds to the second control signal, thereby switching the main storage chip to the backup storage chip. During the switching, the backup controller resets the main controller again, enabling the terminal to obtain key data from the backup controller and load it into the backup storage chip during operation, and access the backup storage chip through the main controller to read or write data.

[0080] In other embodiments of this application, reference continues to be made to... Figure 3 As shown, the terminal also includes a 4G or 5G module and a GPS module. To reduce design costs and space, the 4G or 5G antenna in the terminal is multiplexed using a combiner, as shown in the reference. Figure 3 and Figure 6 As shown, Figure 6 The diagram shows a circuit diagram of the switching between different data transmission paths in the GPS module. The GPS module uses a second switch module for multiplexing. The second switch module is a two-way single-pole double-throw switch. The backup controller generates a fourth control signal and outputs the fourth control signal to the second switch module. The second switch module responds to the fourth control signal to realize the switching between different data transmission paths in the GPS module. Here, the fourth control signal is represented by K1 and K2 to realize the autonomous switching between different data transmission paths. K1 is represented by 0 when it is low and 1 when it is high. K2 is represented by 0 when it is low and 1 when it is high. TX1 and RX1 are the transmit signal path and receive signal path in the first data transmission path, and TX2 and RX2 are the transmit signal path and receive signal path in the second data transmission path. The function of the second switch module is shown in Table 3.

[0081] K1 K2 TX1, RX1 TX2, RX2 0 0 1 0 0 1 0 1 1 X 0 0

[0082] Table 3

[0083] In Table 3 above, when K1 is 0 and K2 is 0, both the transmit signal path TX1 and the receive signal path RX1 in the first transmission data path are usable (represented by 1), while both the transmit signal path TX2 and the receive signal path RX2 in the second transmission data path are unusable (represented by 0). When K1 is 0 and K2 is 1, both the transmit signal path TX1 and the receive signal path RX1 in the first transmission data path are unusable (represented by 0), while both the transmit signal path TX2 and the receive signal path RX2 in the second transmission data path are usable (represented by 1). When K1 is 1 and K2 is X (where X can be 0 or 1), both the transmit signal path TX1 and the receive signal path RX1 in the first transmission data path, as well as the transmit signal path TX2 and the receive signal path RX2 in the second transmission data path, are unusable (represented by 0). Thus, in this embodiment, a combiner is used to multiplex the 4G / 5G module, and a second switch module is used to multiplex the GPS module, reducing design cost and space.

[0084] Of course, the above function table is only one example. The functions of the fourth control signal and the second switch module can also be represented in other ways, as long as the switching and use of the data transmission path can be realized.

[0085] It should be noted that the descriptions of the same steps and contents as in other embodiments in this embodiment can be found in the descriptions in other embodiments, and will not be repeated here.

[0086] Based on the foregoing embodiments, this application provides an exception handling device that can be used to implement... Figures 1-2 , Figure 4 One corresponding exception handling method is provided. The exception handling device includes a main controller, a main relay for controlling the power supply of the main controller, a backup controller with the same function as the main controller, a main storage chip, and a backup storage chip, wherein...

[0087] A backup controller is used to generate a first control signal and send the first control signal to the main relay when the abnormal handling device is powered on and the main controller fails to write data to the main memory chip. The first control signal is used to reset the main controller.

[0088] The main relay is used to respond to the first control signal to reset the main controller;

[0089] The backup controller is also used to determine whether the main controller can write data to the main storage chip. If not, the backup controller switches the main storage chip to the backup storage chip and accesses the backup storage chip through the main controller to read or write data.

[0090] Based on the foregoing embodiments, this application provides a terminal that can be used to implement... Figures 1-2 , Figure 4 For a corresponding exception handling method, please refer to [link / reference]. Figure 7 As shown, the terminal 7 includes a memory 701 and a processor 702, wherein the processor 702 is used to execute an exception handling program stored in the memory 701, and the terminal 7 uses the processor 702 to implement the following steps:

[0091] If the terminal is powered on and the main controller fails to write data to the main storage chip, the backup controller generates a first control signal and sends the first control signal to the main relay. The first control signal is used to reset the main controller.

[0092] The main controller is reset by responding to the first control signal via the main relay;

[0093] Determine whether the main controller can write data to the main storage chip. If not, switch the main storage chip to the backup storage chip through the backup controller, and access the backup storage chip through the main controller to read or write data.

[0094] In other embodiments of this application, the processor 702 is used to execute an exception handler stored in the memory 701 to perform the following steps:

[0095] When the main controller is powered on and started via the main power module, the backup controller is powered on and started via the backup power module, and the main relay is in the normally open state, the main relay responds to the first control signal to switch the main relay from the normally open state to the normally closed state to disconnect the main power module; when the main relay is in the normally closed state for a certain period of time, the main relay is switched from the normally closed state to the normally open state by the controller to turn on the main power module and reset the main controller.

[0096] In other embodiments of this application, the processor 702 is used to execute an exception handler stored in the memory 701 to perform the following steps:

[0097] The backup controller outputs a second control signal, which is used to switch the memory chip; the first switch module responds to the second control signal to switch the main memory chip to the backup memory chip.

[0098] In other embodiments of this application, the processor 702 is used to execute an exception handler stored in the memory 701 to perform the following steps:

[0099] When both the main controller and the backup controller are powered on, the backup controller performs a heartbeat detection on the main controller and obtains the detection result. If the detection result indicates that the data value in the online dictionary established by the backup controller meets the threshold condition, data continues to be written to the main memory chip through the main controller. If the detection result indicates that the data value in the backup controller does not meet the threshold condition, and the data value in the backup controller still does not meet the threshold condition after resetting the main controller through the backup controller, data is written to the main memory chip through the backup controller.

[0100] In other embodiments of this application, the processor 702 is used to execute an exception handler stored in the memory 701 to perform the following steps:

[0101] When the backup controller receives a heartbeat packet periodically sent by the master controller via the full-duplex communication bus, it updates the data value in the online dictionary established by the master controller to a preset data value, and obtains the detection result. The threshold conditions include that the data value is less than or equal to the data threshold and the heartbeat packet carries key data of the terminal. If the backup controller does not receive a heartbeat packet within a second time period, it automatically increments the data value in the online dictionary until the incremented data value is greater than the data threshold, and obtains the detection result.

[0102] In other embodiments of this application, key data includes: the terminal location of the terminal, system time, the state of the main controller, and the value of at least one register.

[0103] In other embodiments of this application, the processor 702 is used to execute an exception handler stored in the memory 701 to perform the following steps:

[0104] When the main controller and the backup controller are powered on and started via the main power module, and the backup relay is in the normally open state, the main controller detects the first current value and the first voltage value of the backup power module. If the first current value is greater than the first current threshold and / or the first voltage value is greater than the first voltage threshold, the main controller controls the backup relay to switch from the normally open state to the normally closed state to disconnect the backup power module. Alternatively, when the main controller and the backup controller are powered on and started via the main power module, and the main relay is in the normally open state, the backup controller detects the second current value and the second voltage value of the main power module. If the second current value is greater than the second current threshold and / or the second voltage value is greater than the second voltage threshold, the backup controller controls the main relay to switch from the normally open state to the normally closed state to disconnect the main power module.

[0105] This application provides a storage medium storing one or more programs that can be executed by one or more processors. When the terminal powers on and the main controller fails to write data to the main storage chip, a backup controller generates a first control signal and sends it to a main relay. This first control signal is used to reset the main controller. The main relay responds to the first control signal to reset the main controller. It then determines whether the main controller can write data to the main storage chip. If not, the backup controller switches the main storage chip to the backup storage chip, and the main controller accesses the backup storage chip to read or write data. This application employs a multi-mode redundancy design for the storage chip. Even if one storage chip completely fails, the backup controller and main relay switch the main storage chip to the backup storage chip, and the main controller accesses the backup storage chip to read or write data. This achieves self-handling and self-recovery of storage chip failures, improving the reliability and stability of the terminal.

[0106] It should be noted that the aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; it can also be various terminals that include one or any combination of the above-mentioned memory, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0107] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0108] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0109] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing module, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0110] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0111] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0112] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0113] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An exception handling method, characterized in that, The method is applied to a terminal, the terminal including a main controller, a main relay for controlling the power supply of the main controller, a backup controller having the same function as the main controller, a main storage chip, and a backup storage chip, the method including: If the terminal is powered on and writing data to the main storage chip through the main controller fails, the backup controller generates a first control signal and sends the first control signal to the main relay, wherein the first control signal is used to reset the main controller; The main controller is reset by responding to the first control signal via the main relay. Determine whether the main controller can write data to the main storage chip. If not, switch the main storage chip to the backup storage chip through the backup controller, and access the backup storage chip through the main controller to read or write data. The method further includes: When both the main controller and the backup controller are powered on and started, the backup controller performs heartbeat detection on the main controller and obtains the detection result. If the detection result indicates that the data value of the online dictionary established by the backup controller meets the threshold condition, the main controller continues to write data to the main storage chip; If the detection result indicates that the data value in the backup controller does not meet the threshold condition, and the data value in the backup controller still does not meet the threshold condition after resetting the main controller through the backup controller, then data is written to the main memory chip through the backup controller.

2. The anomaly handling method according to claim 1, characterized in that, The terminal further includes: a main power module that provides power to the main controller, the main power module being located between the main relay and the main controller; and a backup power module that provides power to the backup controller. The step of resetting the main controller by responding to the first control signal via the main relay includes: When the main controller is powered on and started by the main power module, the backup controller is powered on and started by the backup power module, and the main relay is in the normally open state, the main relay responds to the first control signal to control the main relay to switch from the normally open state to the normally closed state, so as to disconnect the main power module. If the main relay remains in the normally closed state for a first duration, the controller switches the main relay from the normally closed state to the normally open state to turn on the main power module and reset the main controller.

3. The anomaly handling method according to claim 1, characterized in that, The terminal includes a first switch module, the input terminals of which are respectively connected to the main controller and the backup controller, and the output terminals of which are respectively connected to the main memory chip and the backup memory chip. Switching from the main memory chip to the backup memory chip via the backup controller includes: The backup controller outputs a second control signal, which is used to switch the memory chip. The first switch module responds to the second control signal to switch the main storage chip to the backup storage chip.

4. The anomaly handling method according to claim 1, characterized in that, The step of performing heartbeat detection on the main controller through the backup controller and obtaining the detection result includes: When the backup controller receives a heartbeat packet periodically sent by the main controller through the full-duplex communication bus, it updates the data value in the online dictionary established by the backup controller for the main controller to a preset data value to obtain the detection result. The threshold condition includes the data value being less than or equal to a data threshold, and the heartbeat packet carrying key data of the terminal. If the backup controller does not receive the heartbeat packet within a second time period, it automatically increments the data value of the online dictionary until the incremented data value is greater than the data threshold, thereby obtaining the detection result.

5. The anomaly handling method according to claim 4, characterized in that, The key data includes: the terminal's location, system time, the status of the main controller, and the value of at least one register.

6. The anomaly handling method according to any one of claims 1 to 5, characterized in that, After switching the primary storage chip to the backup storage chip via the backup controller, the method further includes: The main controller is reset again by the backup controller so that the terminal can obtain the key data from the backup controller and load it into the backup storage chip during operation.

7. The anomaly handling method according to any one of claims 1 to 5, characterized in that, The terminal further includes: a backup relay for controlling the power supply of the backup controller, the backup power module being located between the backup relay and the backup controller, and the method further includes: When the main controller is powered on and started via the main power module, the backup controller is powered on and started via the backup power module, and the backup relay is in the normally open state, the main controller detects the first current value and the first voltage value of the backup power module. If the first current value is greater than a first current threshold, and / or the first voltage value is greater than a first voltage threshold, the main controller controls the backup relay to switch from the normally open state to the normally closed state to disconnect the backup power module; and / or, When the main controller is powered on and started by the main power module, the backup controller is powered on and started by the backup power module, and the main relay is in the normally open state, the backup controller detects the second current value and the second voltage value of the main power module. If the second current value is greater than the second current threshold and / or the second voltage value is greater than the second voltage threshold, the backup controller controls the main relay to switch from the normally open state to the normally closed state to disconnect the main power module.

8. A terminal, characterized in that, The terminal includes: Memory, used to store executable instructions; A processor, when executing executable instructions stored in the memory, implements the exception handling method according to any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium stores one or more programs, which can be executed by one or more processors to implement the exception handling method as described in any one of claims 1 to 7.

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