An antifuse array structure and method of operation thereof and memory

Abstract

The embodiments of the present disclosure disclose a structure of anti-fuse array and an operating method thereof and a memory, wherein the structure of anti-fuse array comprises an anti-fuse array region and a selection circuit region; the anti-fuse array region comprises a plurality of anti-fuse cells, and the selection circuit region comprises a plurality of selection transistors; and the selection circuit region is located on at least one side of the anti-fuse array region.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an antifuse array structure, its operation method, and a memory. Background Technology

[0002] One-time programmable devices based on anti-fuse technology are widely used in DRAM, NAND flash memory, and other similar devices. An anti-fuse device is a semiconductor device consisting of two conductive layers and a dielectric layer between them. When unprogrammed, the conductive layers are separated by the dielectric layer, and the antifuse is open-circuited. During programming (with an applied high voltage), the dielectric layer is broken down by the high electric field, forming an electrical connection between the two conductive layers, and the antifuse is short-circuited (melted). This melting process is physically one-time, permanent, and irreversible. The on and off states of the antifuse can represent logic "0" and logic "1," respectively. However, current antifuse array structures composed of multiple antifuse devices suffer from problems such as large chip area occupation and poor uniformity, hindering chip miniaturization.

[0003] Therefore, optimizing the antifuse array structure is a technical problem that urgently needs to be solved at this stage. Summary of the Invention

[0004] In view of this, the present disclosure provides an antifuse array structure, its operation method, and a memory.

[0005] According to a first aspect of the present disclosure, an antifuse array structure is provided, comprising: an antifuse array region and a selection circuit region; the antifuse array region includes a plurality of antifuse units, and the selection circuit region includes a plurality of selection transistors; wherein the selection circuit region is located on at least one side of the antifuse array region.

[0006] In some embodiments, the plurality of antifuse units are arranged as a plurality of antifuse unit rows and a plurality of antifuse unit columns; wherein, one of the selection transistors is electrically connected to a column of antifuse units, and the selection transistor is used to select the antifuse unit electrically connected to it from the antifuse unit array for programming operation.

[0007] In some embodiments, the antifuse array region includes: a plurality of first active regions, the plurality of first active regions being arranged in parallel to each other and extending along a first direction; a plurality of antifuse unit gate lines, the plurality of antifuse unit gate lines being arranged in parallel to each other and extending along a second direction, the plurality of first active regions and the plurality of antifuse unit gate lines intersecting each other to define a plurality of antifuse units arranged in the array.

[0008] In some embodiments, the selection circuit region is located on one side of the antifuse array region in the first direction.

[0009] In some embodiments, the selection circuit region includes: a plurality of second active regions located on the same side of the antifuse array region in the first direction, the plurality of second active regions being arranged along the second direction; and a selection transistor gate line extending along the second direction, the selection transistor gate line covering a portion of each of the second active regions.

[0010] In some embodiments, the width of the second active region along the second direction is the same as the width of the first active region along the second direction.

[0011] In some embodiments, the selection circuit area includes a first selection circuit area and a second selection circuit area; the first selection circuit area is located on one side of the antifuse array area in the first direction, and the second selection circuit area is located on the other side of the antifuse array area in the first direction.

[0012] In some embodiments, the antifuse array region includes multiple rows of antifuse units, wherein the selection transistors electrically connected to the even-numbered rows of antifuse units are located on one side of the antifuse array region in the first direction; and the selection transistors electrically connected to the odd-numbered rows of antifuse units are located on the other side of the antifuse array region in the first direction.

[0013] In some embodiments, the selection circuit region includes: a plurality of second active regions arranged on both sides of the antifuse array region in the first direction, the plurality of second active regions on each side being arranged along the second direction; a first selection transistor gate line extending along the second direction and covering a portion of each of the second active regions located on one side of the antifuse array region in the first direction; a second selection transistor gate line extending along the second direction and covering a portion of each of the second active regions located on the other side of the antifuse array region in the first direction; and a connector electrically connecting the first selection transistor gate line and the second selection transistor gate line.

[0014] In some embodiments, the width of the second active region along the second direction is greater than or equal to twice the width of the first active region along the second direction.

[0015] In some embodiments, the system further includes: a plurality of bit lines located above the first active region, the plurality of bit lines being arranged in parallel to each other and extending along a first direction, each bit line being electrically connected to the first and second poles of a plurality of antifuse units, and each bit line being electrically connected to a bit line signal input terminal through a selection transistor.

[0016] In some embodiments, the device further includes: a plurality of first contact plugs located on the first active region, wherein the first and second terminals of the antifuse unit are electrically connected to the bit line through the first contact plugs; and a plurality of second contact plugs located on the second active region, wherein the first terminal of the selection transistor is electrically connected to the bit line through the second contact plugs, and the second terminal of the selection transistor is electrically connected to the bit line signal input terminal through the second contact plugs.

[0017] According to a second aspect of the present disclosure, an operation method for an antifuse array structure is provided, comprising: providing an antifuse array structure as described in any of the above embodiments; and performing a programming operation or a reading operation on the antifuse array structure.

[0018] In some embodiments, the programming operation includes: selecting an antifuse cell to be programmed; applying a first voltage to the gate line of the antifuse cell to be programmed; leaving other antifuse cell gate lines floating; applying a second voltage to the gate line of the selection transistor; applying a third voltage to the bit line signal input terminal electrically connected to the antifuse cell to be programmed; and leaving other bit line signal input terminals floating; wherein the first voltage is greater than the third voltage, and the difference between the first voltage and the third voltage is sufficient to break down the gate dielectric layer of the antifuse cell, and the second voltage is the turn-on voltage of the selection transistor.

[0019] In some embodiments, the read operation includes: applying a fourth voltage to the gate line of the selected transistor;

[0020] Select the antifuse cell to be read, apply a fifth voltage to the bit line signal input terminal electrically connected to the antifuse cell to be read, and leave other bit line signal input terminals floating; apply a sixth voltage to the gate line of the antifuse cell to be read, and leave other antifuse cell gate lines floating or apply a seventh voltage; wherein,

[0021] The fifth voltage is greater than the sixth voltage, the fifth voltage is equal to the seventh voltage, and the fourth voltage is the turn-on voltage of the selection transistor.

[0022] According to a third aspect of the present disclosure, a memory is provided, including an antifuse memory array circuit as described in any of the above embodiments.

[0023] In this embodiment, by placing the selection circuit region, which includes multiple selection transistors, around the antifuse array region, the length and width of the antifuse array are significantly reduced, resulting in a substantial decrease in the area of ​​the antifuse array. Based on this structure, the layout of the antifuse cell gate lines and active regions can be more uniform, contributing to improved uniformity of the antifuse array. Simultaneously, most of the selection transistor gate line control signals can be eliminated, requiring only one set of selection transistor gate line control signals. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the layout of an antifuse array structure provided in an embodiment of the present disclosure;

[0026] Figure 2 This is a schematic diagram of an antifuse array structure provided in an embodiment of the present disclosure;

[0027] Figure 3 This is a schematic diagram of the layout of another antifuse array structure provided in an embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram of another antifuse array structure provided in an embodiment of the present disclosure;

[0029] Figure 5 This is a flowchart illustrating an operation method for an antifuse array structure provided in an embodiment of this disclosure.

[0030] Explanation of reference numerals in the attached figures:

[0031] 10-Antifuse array region; 11-Antifuse unit; 12-First active region; 13-Antifuse unit gate line; 14-First contact plug; 15-Third contact plug; 16-First metal layer;

[0032] 20 - Selection circuit area; 201 - First selection circuit area; 202 - Second selection circuit area; 21 - Selection transistor; 22 - Second active area; 23 - Selection transistor gate line; 231 - First selection transistor gate line; 232 - Second selection transistor gate line; 24 - Second contact plug; 25 - Fourth contact plug; 26 - Second metal layer; 27 - Connector;

[0033] 31-bit line; 32-bit line signal input terminal. Detailed Implementation

[0034] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0036] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0041] Typically, each antifuse device includes an antifuse cell and a select transistor electrically connected to it. The gate voltage of the select transistor serves as a control signal to program the antifuse cell. However, in an antifuse array structure comprising multiple antifuse devices, each select transistor electrically connected to the antifuse cell occupies a limited area of ​​the chip. Furthermore, the select transistors located within the antifuse array structure affect the overall layout of the antifuse cells, which limits the development of chip miniaturization and high integration.

[0042] Based on this, the present disclosure provides an antifuse array structure. Figure 1 This is a schematic diagram of the layout of the antifuse array structure provided in the embodiments of this disclosure; Figure 2 This is a schematic diagram of the antifuse array structure provided in an embodiment of this disclosure.

[0043] See appendix Figure 1 and attached Figure 2 An antifuse array structure includes an antifuse array region 10 and a selection circuit region 20; the antifuse array region 10 includes a plurality of antifuse units 11, and the selection circuit region 20 includes a plurality of selection transistors 21; wherein the selection circuit region 20 is located on at least one side of the antifuse array region 10.

[0044] The antifuse array structure provided in this disclosure places the select transistors on the periphery of the antifuse array region, thereby greatly reducing the length and width of the antifuse array and significantly reducing its area. Based on this structure, the layout of the antifuse cell gate lines and active regions can be more uniform, contributing to improved uniformity of the antifuse array. Simultaneously, most of the select transistor gate line control signals can be eliminated, requiring only one set of select transistor gate line control signals.

[0045] In the embodiments of this disclosure, the antifuse unit may have a transistor structure, the transistor including a gate and two doped regions located on both sides of the gate, the two doped regions being a first electrode and a second electrode, respectively, wherein the first electrode can be the source and the second electrode can be the drain; or, the first electrode can be the drain and the second electrode can be the source. In actual operation, adjacent antifuse transistors can share the same doped region (as the first electrode or the second electrode) to improve space utilization, allowing the bit line to be electrically connected to the first and second electrodes of multiple antifuse units simultaneously. This allows the antifuse unit to be programmed from both sides simultaneously, improving programming efficiency. In actual operation, the antifuse unit may include a metal-oxide-semiconductor transistor (MOS), such as a P-type metal-oxide-semiconductor transistor (PMOS) or an N-type metal-oxide-semiconductor transistor (NMOS). It should be noted that the embodiments of this disclosure include, but are not limited to, these. The antifuse unit may also have a capacitor structure, the capacitor structure including a gate and a doped region located on one side of the gate. The following description uses an antifuse unit with a transistor structure as an example, but does not constitute a limitation on the embodiments of this disclosure.

[0046] In some embodiments, see Appendix Figure 2 Multiple antifuse cells 11 are arranged in multiple rows and columns; one select transistor 21 is electrically connected to one column of antifuse cells 11, and the select transistor 21 is used to select the antifuse cell 11 electrically connected to it from the antifuse cell array for programming operation. Here, the row extension direction and column extension direction of the antifuse cell array can be perpendicular to each other.

[0047] In some embodiments, see Appendix Figure 2 The antifuse array region includes: a plurality of first active regions 12, which are arranged in parallel to each other and extend along a first direction; a plurality of antifuse unit gate lines 13, which are arranged in parallel to each other and extend along a second direction, and the plurality of first active regions 12 and the plurality of antifuse unit gate lines 13 intersect each other to define a plurality of antifuse units 11 arranged in the array.

[0048] In practice, the first active region is disposed on a substrate, which can be silicon, silicon-germanium, germanium, or other suitable semiconductors. The first active region can be formed into an N-type doped region by doping with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and can be formed into a P-type doped region by doping with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. In practice, the first active region can include source / drain doped regions. The material of the antifuse cell gate line includes, but is not limited to, polysilicon, titanium nitride, tungsten, or combinations thereof. In practice, the first direction is the column extension direction of the antifuse cell array, and the second direction is the row extension direction of the antifuse cell array. The first direction can be perpendicular to the second direction, which can further improve the integration density of the structure.

[0049] In some embodiments, see Appendix Figure 1 and attached Figure 2 The selection circuit area 20 is located on one side of the antifuse array area 10 in the first direction. This results in a simple overall layout, a small antifuse array structure, simple manufacturing process, fewer interconnects, and high integration.

[0050] In some embodiments, see Appendix Figure 2 The selection circuit region 20 includes: a plurality of second active regions 22, located on the same side of the antifuse array region 10 in a first direction, and arranged along a second direction; and a selection transistor gate line 23 extending along the second direction and covering a portion of each second active region 22. In practice, the second active regions are disposed on a substrate, which may be silicon, silicon-germanium, germanium, or other suitable semiconductors. The second active regions can be formed as N-type doped regions by doping with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and can be formed as P-type doped regions by doping with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. In practice, the second active regions may include source / drain doped regions. The materials for the selection transistor gate lines include, but are not limited to, polysilicon, titanium nitride, tungsten metal, or combinations thereof.

[0051] In some embodiments, see Appendix Figure 2 The width W2 of the second active region 22 along the second direction is the same as the width W1 of the first active region along the second direction. Having the same width for both the second and first active regions facilitates mask fabrication and reduces the difficulty of the patterning process.

[0052] In some embodiments, see Appendix Figure 2The antifuse array structure further includes multiple bit lines 31 located above the first active region 12. These bit lines 31 are arranged parallel to each other and extend along a first direction. Each bit line 31 is electrically connected to the first and second terminals of multiple antifuse units 11, and each bit line 31 is electrically connected to the bit line signal input terminal 32 via a selection transistor 21. Here, the materials of the bit lines include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof.

[0053] The embodiments disclosed herein use a select transistor electrically connected to a column of antifuse units, so that a single select transistor drives a column of antifuse units. Compared with related technologies where a single select transistor controls a single antifuse unit, this greatly reduces the number of control signals.

[0054] Specifically, in conjunction with the appendix Figure 2 The antifuse cell array is an 8*8 antifuse array structure, meaning it includes 8 bit lines (BL) and 8 antifuse cell gate lines (FG), with 8 antifuse cells connected to each bit line. Although Figure 2 Only 8 bit lines BL and 8 antifuse cell gate lines FG are shown. In other embodiments, an antifuse array structure with any other number of bit lines BL and antifuse cell gate lines FG may be included, such as an antifuse array structure with 16 bit lines BL and 16 antifuse cell gate lines FG, or 32 bit lines BL and 32 antifuse cell gate lines FG.

[0055] In some embodiments, see Appendix Figure 2 The antifuse array structure also includes: a plurality of first contact plugs 14 located on the first active region 12, wherein the first and second poles of the antifuse unit 11 are electrically connected to the bit line 31 through the first contact plugs 14; and a plurality of second contact plugs 24 located on the second active region 22, wherein the first pole of the selection transistor 21 is electrically connected to the bit line 31 through the second contact plugs 24, and the second pole of the selection transistor 21 is electrically connected to the bit line signal input terminal 32 through the second contact plugs 24.

[0056] In some embodiments, ohmic contacts can be achieved between the bottom of the first contact plug and the first / second pole of the antifuse unit, and between the bottom of the second contact plug and the first / second pole of the select transistor, through a metal silicide layer to reduce series resistance. The metal silicide layer includes silicides of iron, cobalt, nickel, platinum, or alloys thereof, such as low-resistivity nickel silicide, platinum silicide, cobalt silicide, or alloys thereof.

[0057] In some embodiments, see Appendix Figure 2The antifuse array structure further includes: a third contact plug 15, through which the gate line 13 of the antifuse unit is electrically connected to the trace in the first metal layer 16; and a fourth contact plug 25, through which the gate line 23 of the select transistor is electrically connected to the trace in the second metal layer 26. The first metal layer 16 and the second metal layer 26 can be the same film layer or different film layers.

[0058] In some embodiments, see Appendix Figure 3 and attached Figure 4 The selection circuit region 20 includes a first selection circuit region 201 and a second selection circuit region 202; the first selection circuit region 201 is located on one side of the antifuse array region 10 in the first direction, and the second selection circuit region 202 is located on the other side of the antifuse array region 10 in the first direction. This increases the area occupied by the selection circuit region, thereby increasing the width of the second active region, and consequently increasing the drive current of the selection transistor.

[0059] In some embodiments, see Appendix Figure 4 The antifuse array region 10 includes multiple rows of antifuse units 11. Selector transistors 21 electrically connected to even-numbered rows of antifuse units 11 are located on one side of the antifuse array region 10 in the first direction; selector transistors 21 electrically connected to odd-numbered rows of antifuse units 11 are located on the other side of the antifuse array region 10 in the first direction. This fully utilizes the area on both sides of the antifuse array region, resulting in high space utilization for the selector transistors located on both sides. The symmetrical arrangement also makes the structure more stable, and the patterning process is easier to control and adjust. For example, the antifuse array region 10 includes 8 rows of antifuse units, each row electrically connected to BL0, BL1…BL7. Selector transistors electrically connected to BL0, BL2, BL4, and BL6 are located on one side of the antifuse array region; selector transistors electrically connected to BL1, BL3, BL5, and BL7 are located on the other side of the antifuse array region.

[0060] In some embodiments, see Appendix Figure 4The selection circuit region 20 includes: a plurality of second active regions 22, which are arranged on both sides of the antifuse array region 10 in a first direction, with the plurality of second active regions 22 on each side arranged along a second direction; a first selection transistor gate line 231, which extends along the second direction and covers a portion of each second active region 22 located on one side of the antifuse array region 10 in the first direction; a second selection transistor gate line 232, which extends along the second direction and covers a portion of each second active region 22 located on the other side of the antifuse array region 10 in the first direction; and a connector 27, which electrically connects the first selection transistor gate line 231 and the second selection transistor gate line 232. The connector is made of conductive materials, including but not limited to tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof. The connector may extend in a direction parallel to the first direction.

[0061] In some embodiments, see Appendix Figure 4 The width W2 of the second active region along the second direction is greater than or equal to twice the width W1 of the first active region along the second direction. This increases the drive current of the selection transistor.

[0062] This disclosure also provides an operation method for an antifuse array structure, as shown in the attached figure. Figure 5 As shown, it includes:

[0063] Step 501: Provide an antifuse array structure as described in any of the above embodiments;

[0064] Step 502: Perform programming or reading operations on the antifuse array structure.

[0065] The operation method of the antifuse array structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0066] First, see appendix Figure 2 and attached Figure 4 Step 501 is executed to provide an antifuse array structure as described in any of the above embodiments.

[0067] In some embodiments, see Appendix Figure 2 An antifuse array structure includes an antifuse array region 10 and a selection circuit region 20; the antifuse array region 10 includes a plurality of antifuse units 11, and the selection circuit region 20 includes a plurality of selection transistors 21; wherein the selection circuit region 20 is located on at least one side of the antifuse array region 10.

[0068] In some embodiments, see Appendix Figure 2 Multiple antifuse units 11 are arranged in multiple rows and columns of antifuse units; wherein, a selection transistor 21 is electrically connected to a column of antifuse units 11, and the selection transistor 21 is used to select the antifuse unit 11 electrically connected to it from the antifuse unit array for programming operation.

[0069] In some embodiments, see Appendix Figure 2 The antifuse array region includes: a plurality of first active regions 12, which are arranged in parallel to each other and extend along a first direction; a plurality of antifuse unit gate lines 13, which are arranged in parallel to each other and extend along a second direction, and the plurality of first active regions 12 and the plurality of antifuse unit gate lines 13 intersect each other to define a plurality of antifuse units 11 arranged in the array.

[0070] In some embodiments, see Appendix Figure 2 The selection circuit area 20 is located on one side of the antifuse array area 10 in the first direction. In this way, the overall layout is simple, the antifuse array structure occupies a small area, the process is simple, there are few interconnects, and the integration is high.

[0071] In some embodiments, see Appendix Figure 2 The selection circuit region 20 includes: a plurality of second active regions 22, which are located on the same side of the antifuse array region 10 in a first direction and are arranged along a second direction; and a selection transistor gate line 23, which extends along the second direction and covers a portion of each second active region 22.

[0072] In some embodiments, see Appendix Figure 2 The width W2 of the second active region 22 along the second direction is the same as the width W1 of the first active region along the second direction. Having the same width for both the second and first active regions facilitates mask fabrication and reduces the difficulty of the patterning process.

[0073] In some embodiments, see Appendix Figure 2 The antifuse array structure further includes multiple bit lines 31 located above the first active region 12. These bit lines 31 are arranged parallel to each other and extend along a first direction. Each bit line 31 is electrically connected to the first and second terminals of multiple antifuse units 11, and each bit line 31 is electrically connected to the bit line signal input terminal 32 via a selection transistor 21. This embodiment of the present disclosure uses a selection transistor to electrically connect to a column of antifuse units, enabling one selection transistor to drive a column of antifuse units. Compared to related technologies where one selection transistor controls one antifuse unit, this significantly reduces the number of control signals required.

[0074] In some embodiments, see Appendix Figure 2 The antifuse array structure also includes: a plurality of first contact plugs 14 located on the first active region 12, wherein the first and second poles of the antifuse unit 11 are electrically connected to the bit line 31 through the first contact plugs 14; and a plurality of second contact plugs 24 located on the second active region 22, wherein the first pole of the selection transistor 21 is electrically connected to the bit line 31 through the second contact plugs 24, and the second pole of the selection transistor 21 is electrically connected to the bit line signal input terminal 32 through the second contact plugs 24.

[0075] In some embodiments, see Appendix Figure 4 The selection circuit region 20 includes a first selection circuit region 201 and a second selection circuit region 202; the first selection circuit region 201 is located on one side of the antifuse array region 10 in the first direction, and the second selection circuit region 202 is located on the other side of the antifuse array region 10 in the first direction. This increases the area occupied by the selection circuit region, thereby increasing the width of the second active region, and consequently increasing the drive current of the selection transistor.

[0076] In some embodiments, see Appendix Figure 4 The antifuse array region 10 includes multiple rows of antifuse cells 11. Selector transistors 21 electrically connected to the even-numbered rows of antifuse cells 11 are located on one side of the antifuse array region 10 in the first direction; selector transistors 21 electrically connected to the odd-numbered rows of antifuse cells 11 are located on the other side of the antifuse array region 10 in the first direction. This fully utilizes the area on both sides of the antifuse array region, resulting in high space utilization for the selector transistors located on both sides of the antifuse array region.

[0077] In some embodiments, see Appendix Figure 4 The selection circuit region 20 includes: a plurality of second active regions 22, which are arranged on both sides of the antifuse array region 10 in a first direction, with the plurality of second active regions 22 on each side arranged along a second direction; a first selection transistor gate line 231, which extends along the second direction and covers a portion of each second active region 22 located on one side of the antifuse array region 10 in the first direction; a second selection transistor gate line 232, which extends along the second direction and covers a portion of each second active region 22 located on the other side of the antifuse array region 10 in the first direction; and a connector 27, which electrically connects the first selection transistor gate line 231 and the second selection transistor gate line 232.

[0078] In some embodiments, see Appendix Figure 4The width W2 of the second active region along the second direction is greater than or equal to twice the width W1 of the first active region along the second direction. This increases the drive current of the selection transistor.

[0079] Next, step 502 is executed to perform programming or reading operations on the antifuse array structure.

[0080] In some embodiments, in conjunction with the appendix Figure 2 The programming operation includes: selecting the antifuse cell to be programmed; applying a first voltage to the gate line of the antifuse cell to be programmed, while leaving the gate lines of other antifuse cells floating; applying a second voltage to the gate line of the select transistor; applying a third voltage to the bit line signal input terminal electrically connected to the antifuse cell to be programmed, while leaving the other bit line signal input terminals floating; wherein, the first voltage is greater than the third voltage, and the difference between the first voltage and the third voltage is sufficient to break down the gate dielectric layer of the antifuse cell, and the second voltage is the turn-on voltage of the select transistor. Here, the gate dielectric layer can be, for example, an oxide layer.

[0081] For example, combined with appendix Figure 2 First, select the antifuse cell to be programmed. For example, the antifuse cell to be programmed may be the antifuse cell in the third column and fourth row of the antifuse cell array.

[0082] Next, a first voltage is applied to the gate line of the antifuse cell to be programmed, while the other antifuse cell gate lines are left floating. For example, a first voltage is applied to the gate line FG3 of the third column, fourth row, while the other antifuse cell gate lines FG0, FG1, FG2, FG4...FG7 are left floating. The first voltage can be, for example, around 6V.

[0083] Next, a second voltage is applied to the gate line of the select transistor, which is the turn-on voltage of the select transistor.

[0084] Then, a third voltage is applied to the bit line signal input terminal electrically connected to the antifuse cell to be programmed, while the other bit line signal input terminals are left floating. For example, a third voltage is applied to the bit line signal input terminal of bit line BL2, which is electrically connected to the antifuse cell in the third column, fourth row, while the other bit lines BL0, BL1, BL3…BL7 are left floating. The third voltage can be, for example, around 0V. The difference between the first voltage and the third voltage can break down the gate dielectric layer of the antifuse cell, causing the antifuse cell to break down.

[0085] In some embodiments, in conjunction with the appendix Figure 2The read operation includes: applying a fourth voltage to the gate line of the select transistor; selecting the antifuse cell to be read; applying a fifth voltage to the bit line signal input terminal electrically connected to the antifuse cell to be read; leaving other bit line signal input terminals floating; applying a sixth voltage to the gate line of the antifuse cell to be read; leaving other antifuse cell gate lines floating or applying a seventh voltage; wherein the fifth voltage is greater than the sixth voltage, the fifth voltage and the seventh voltage are equal, and the fourth voltage is the turn-on voltage of the select transistor.

[0086] For example, combined with appendix Figure 2 First, a fourth voltage is applied to the gate line of the select transistor; this fourth voltage is the turn-on voltage of the select transistor. In practice, the fourth voltage can be equal to the second voltage.

[0087] Select the antifuse cell to be read, for example, the antifuse cell to be read is the antifuse cell in the third column and fourth row of the antifuse cell array.

[0088] Next, a fifth voltage is applied to the bit line signal input terminal electrically connected to the antifuse cell to be read, while the other bit line signal input terminals are left floating. For example, a fifth voltage is applied to the bit line signal input terminal of bit line BL2, which is electrically connected to the antifuse cell in the third column, fourth row, while the other bit lines BL0, BL1, BL3...BL7 are left floating. The third voltage can be, for example, around 1V.

[0089] Then, a sixth voltage is applied to the gate line of the antifuse cell to be read, while the other antifuse cell gate lines are left floating or a seventh voltage is applied. For example, a sixth voltage is applied to the gate line FG3 in the third column, fourth row, while the other antifuse cell gate lines FG0, FG1, FG2, FG4…FG7 are left floating or have a seventh voltage applied. The fifth voltage is greater than the sixth voltage, and the fifth and seventh voltages are equal. The sixth voltage can be, for example, around 0V, and the seventh voltage can be, for example, around 1V.

[0090] This disclosure also provides a memory, which includes the antifuse memory array circuit as described in any of the above embodiments. For example, the memory includes, but is not limited to, DRAM, NAND, and other types of memory.

[0091] In summary, the antifuse array structure provided in this disclosure places the select transistors on the periphery of the antifuse array region, thereby greatly reducing the length and width of the antifuse array and significantly decreasing its area. Based on this structure, the layout of the antifuse cell gate lines and active regions can be more uniform, contributing to improved uniformity of the antifuse array. Simultaneously, most of the select transistor gate line control signals can be eliminated, requiring only one set of select transistor gate line control signals.

[0092] It should be noted that the antifuse array structure and its operation method provided in this disclosure can be applied to any integrated circuit including this structure. The technical features described in each embodiment can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described forming method steps without departing from the protection scope of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.

[0093] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An antifuse array structure, characterized in that, include: Antifuse array area and selection circuit area; The antifuse array region includes multiple antifuse units, and the selection circuit region includes multiple selection transistors; wherein... The selection circuit area is located on at least one side of the antifuse array area; The multiple antifuse units are arranged in multiple rows of antifuse units and multiple columns of antifuse units; In this configuration, one of the selection transistors is electrically connected to a column of antifuse units, and the selection transistor is used to select the antifuse unit electrically connected to it from the antifuse unit array for programming operations; The antifuse array region includes: Multiple first active regions are arranged in parallel to each other and extend along a first direction; Multiple antifuse unit gate lines are arranged in parallel to each other and extend along a second direction. Multiple first active regions intersect with the multiple antifuse unit gate lines to define multiple antifuse units arranged in an array. The selection circuit area includes a first selection circuit area and a second selection circuit area; The first selection circuit area is located on one side of the antifuse array area in the first direction, and the second selection circuit area is located on the other side of the antifuse array area in the first direction; The antifuse array region includes multiple rows of antifuse units, wherein the selection transistors electrically connected to the even-numbered rows of antifuse units are located on one side of the antifuse array region in the first direction; and the selection transistors electrically connected to the odd-numbered rows of antifuse units are located on the other side of the antifuse array region in the first direction.

2. The structure according to claim 1, characterized in that, The selection circuit area includes: Multiple second active regions are arranged on both sides of the antifuse array region in the first direction, and the multiple second active regions on each side are arranged along the second direction; The first selection transistor gate line extends along the second direction and covers a portion of each of the second active regions located on one side of the antifuse array region in the first direction. The second selection transistor gate line extends along the second direction and covers a portion of each of the second active regions located on the other side of the antifuse array region in the first direction. A connector that electrically connects the first select transistor gate line and the second select transistor gate line.

3. The structure according to claim 2, characterized in that, The width of the second active region along the second direction is greater than or equal to twice the width of the first active region along the second direction.

4. The structure according to claim 2, characterized in that, Also includes: Multiple bit lines are located above the first active region. The multiple bit lines are arranged in parallel to each other and extend along the first direction. Each bit line is electrically connected to the first and second poles of multiple antifuse units, and each bit line is electrically connected to the bit line signal input terminal through a selection transistor.

5. The structure according to claim 4, characterized in that, Also includes: A plurality of first contact plugs are located on the first active region, and the first and second poles of the antifuse unit are electrically connected to the bit line through the first contact plugs; Multiple second contact plugs are located on the second active region. The first terminal of the selection transistor is electrically connected to the bit line through the second contact plugs, and the second terminal of the selection transistor is electrically connected to the bit line signal input terminal through the second contact plugs.

6. A method for operating an antifuse array structure, characterized in that, include: Provide an antifuse array structure as described in any one of claims 1-5; Perform programming or reading operations on the antifuse array structure.

7. The operating method according to claim 6, characterized in that, The programming operations include: Select the antifuse cell to be programmed, apply a first voltage to the gate line of the antifuse cell to be programmed, and leave the gate lines of other antifuse cells floating. A second voltage is applied to the gate line of the selected transistor; A third voltage is applied to the bit line signal input terminal electrically connected to the antifuse unit to be programmed, while the other bit line signal input terminals are left floating; wherein, The first voltage is greater than the third voltage, and the difference between the first voltage and the third voltage is sufficient to break down the gate dielectric layer of the antifuse unit, and the second voltage is the turn-on voltage of the select transistor.

8. The operating method according to claim 7, characterized in that, The read operation includes: A fourth voltage is applied to the gate line of the selected transistor; Select the antifuse transistor to be read, apply the fifth voltage to the bit line signal input terminal electrically connected to the antifuse transistor to be read, and leave the other bit line signal input terminals floating. A sixth voltage is applied to the gate line of the antifuse transistor to be read, while the other antifuse transistor gate lines are either left floating or a seventh voltage is applied; wherein, The fifth voltage is greater than the sixth voltage, the fifth voltage is equal to the seventh voltage, and the fourth voltage is the turn-on voltage of the selection transistor.

9. A memory, characterized in that, Includes the antifuse array structure as described in any one of claims 1-5.

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