Acceleration of s-polarized ecc throughput by a scheduler

Abstract

Acceleration of S-polarized ECC throughput by a scheduler is disclosed. A method of simplified successive cancellation list (SSCL) error decoding of an S-polar code includes representing an S-polar code as a perfect binary tree; providing a node v with a soft information vector from a parent node of v to compute a soft information vector for a left child node of v; providing v with a hard decision vector from the left child node and using it with to create a soft information vector and pass it to a right child node of v; providing v with a hard decision vector from its right child node and using it with to create a hard decision vector β v and pass it to its parent node; when v is an i-th leaf node of the perfect tree, updating two path metrics and selecting a path obtained by extending a current path by the lowest path metric.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a method of performing error correction in digital communication with shortened latency, and to a hardware implementation of the method. BACKGROUND

[0002] S-polarization (S-Polar) is a generalized concatenated code (GCC) that takes a Reed-Solomon (RS) code as its outer code and a polar code as its inner code. In a GCC, S-1 outer codes and S inner codes are used to encode information into an N x J array. The inner codes are linear nested codes, i.e., for 1 < s < S-1, the s-th code is contained in the S-1-th code. Specifically, if is the dimension of the s-th code, then The outer codes are assumed to be systematic codes with length J and dimension When considering the outer codes, it is convenient to include two trivial outer codes with dimensions and for stages 0 and S, respectively. The s-th outer code (1 < s < S) is defined over an extension field of GF(2) of dimension The inner codes encode the information of the outer code and some parity bits into rows of the array. The encoded rows are mapped into a coset domain, on which the outer codes operate. A coset of a row code word is a vector of length such that for each stage s, the first bits of the vector allow to reduce a code word of C (0) to a code word of C (s) Thus, the side information from the coset increases the correctability of the rows. More precisely, the encoding of the GCC is performed in S stages, where at each stage s, new information bits and parity bits from the previous outer code are encoded into code words of C (s) and stored as n rows of the array. The encoded rows are mapped into a coset domain. The s+1-th outer code systematically encodes the current columns of the coset array. The parity bits of the obtained code words are sent to the next inner code for encoding. Figure 1 The structure of a code word of an N x J GCC with S stages is illustrated. The white cells represent information symbols, whereas the grey cells represent parity bits. SUMMARY

[0003] According to embodiments of this disclosure, a method for Simplified Successive Elimination List (SSCL) error decoding of S-polar codes is provided, comprising: dividing a length N = 2 n The S-polar code is represented as a perfect binary tree with 2N-1 nodes, where n is a non-negative integer, and for the l-th path in the list of L paths through the binary tree, 1 ≤ l ≤ L. The S-polar code is a generalized concatenated code (GCC) with Reed-Solomon (RS) codes as its outer codes and polar codes as its inner codes, where S-1 outer codes and S inner codes are used to encode information into an N×J array, where S and J are non-negative integers. The GCC is encoded in S stages, where in each stage s, new information bits and parity bits from the previous outer codes are encoded into C. (s) of The codewords are stored as n rows of the array, where C (s) It is the codeword in stage s, where This refers to the amount of data in the foreign codeword of stage s, where the encoded lines are mapped to a coset array, in which the (s+1)th foreign codeword systematically corresponds to the current value of the coset array. Each column is encoded, and the parity bits of the obtained codewords are sent to the next inner code for encoding; the node v in the decoding path l at depth d in the perfect binary tree is provided with information from the parent node v. p The length of the soft information 2 d vector For each path in the list of paths in the binary tree, compute the left child node v of node v. l The length of the soft information 2 d-1 vector Provide node v with a hard decision of length 2 from the left child node. d-1 vector And use the vector together With the vector To create a length of 2 d-1 soft information vector and the vector Pass the result to the right child of node v; provide node v with the length 2 of the hard decision from its right child. d-1 vector And use the vector together With the vector To create a hard decision length of 2 d The hard decision vector β v and the vector β vpassed to its parent node; when v is the i-th leaf node of the perfect tree, where 0 ≤ i < 2n, then, for each path in the list of paths, update two path metrics according to and where is the log-likelihood ratio representing the codeword for the path (l) passing through leaf node i; select L paths out of the 2L paths obtained by extending the current L paths with either 0 bit or 1 bit according to the lowest path metric; and if the l-th path is extended with 0 bit, set the vector to 0, otherwise, set the vector to 1.

[0004] According to another embodiment of the present disclosure, the method includes, when v is a frozen leaf node, extending all paths with 0 bit, and for each path index 1 ≤ l ≤ L, setting the vector to 0, where the frozen leaf node forces the hard decision to be zero.

[0005] According to another embodiment of the present disclosure, the method includes, for a node (RATE-0 node) that is the root of a subtree having only frozen leaf nodes, for a node (RATE-1 node) that is the root of a subtree having information leaf nodes, and for a node that is the root of a subtree whose leaf nodes are all frozen leaf nodes, except for the rightmost leaf node (REP node), updating the L best path metrics without accessing other nodes in the subtree of the binary tree, and the L best path metrics calculate the corresponding hard decision vectors.

[0006] According to another embodiment of the present disclosure, for RATE-0 nodes and REP nodes, update the L best path metrics in parallel for all paths in the list, where the latency of the path metric update depends on the depth of the node rather than the list size.

[0007] According to another embodiment of the present disclosure, updating the L best path metrics includes, for a RATE-1 node at depth d, sequentially calculating m = min{L - 1; 2 n-d} bits of the hard decision, where the latency of the path metric update depends on the list size.

[0008] According to another embodiment of the present disclosure, the method includes selecting t paths for those leaf nodes where the correct path is likely to be among the best t paths, where t < L; applying a CRC detector at the k-th leaf node; and continuing the decoding until the number of paths equals one.

[0009] According to another embodiment of the present disclosure, determining the leaf nodes for which the correct path is likely among the best t < L paths includes one or more of the following steps: selecting those paths whose path metrics are greater than a predetermined threshold, using machine learning to select the best t < L decoding paths, using a classifier to select the best t < L decoding paths, or using positive predictions for each path to select the best t < L decoding paths.

[0010] According to another embodiment of the present disclosure, different paths are processed in parallel, each path being associated with a memory storing 2N - 1 soft decision values, and each memory being assigned a unique processing block for performing soft computations along the decoding tree.

[0011] According to another embodiment of the present disclosure, each node in the decoding tree stores soft computations and hard decisions, where the hard decision is represented by one bit and the soft computation is represented by multiple bits. The method further includes: for a node at depth d, saving 2 n-d soft computations and 2 n-d hard decisions for each path in the list; and pruning paths in the decoding tree.

[0012] According to an embodiment of the present disclosure, a method for simplified successive cancellation list (SSCL) error decoding of S - polar codes is provided, including: representing an S - polar code of length N = 2 n as a perfect binary tree having 2N - 1 nodes, where n is a non - negative integer, where, for the l - th path in a list of L paths through the binary tree, 1 ≤ l ≤ L, where the S - polar code is a generalized concatenated code (GCC) having a Reed - Solomon (RS) code as its outer code and a polar code as its inner code, where S - 1 outer codes and S inner codes are used to encode information into an N×J array, where S and J are non - negative integers, where the GCC is encoded in S stages, where in each stage s, new information bits and parity check bits from the previous outer code are encoded into C (s) codewords and stored as n rows of the array, where C is the codeword in stage s, where (s) is the amount of data in the outer codeword in stage s, where the encoded rows are mapped into a coset array, in which the (s + 1) - th outer code systematically encodes the current columns of the coset array, and where the parity check bits of the obtained codewords are sent to the next inner code for encoding; receiving a vector of length 2 n of log - likelihood ratios (LLRs), where each entry of the vector can take one of q possible values and L is the list size. For the first - layer decoding, at the left child node v of the root​l The soft calculation in 2 takes the length 2 of the values in the set of size q n-1 of the vector α l , while the soft calculation in the right child node v of the root r takes the length 2 of the entries of the values in the set of size 2q 2 of the vector α n-1 , where α r depends on the hard decision bit β r,i . When 3q l,I f + N log2q << Nf (where f is the number of bits representing the soft calculation value), the method includes: for 0 ≤ i < 2 2 , determining the values of α for coordinates 2i and 2i + 1 by accessing a lookup table of size q n-1 ; and determining the value of α 2 by accessing a lookup table of size 2q l,i . For the second - layer decoding, the first node from the left has q 2 possible values for soft calculation, the second node from the left has 2q r,i possible values for soft calculation, the third node from the left has 4q 4 possible values for soft calculation, and the last node has 8q 4 possible values for soft calculation. When 15q 4 + N log 4 2 << f N(L / 2 + 1), the method includes: determining the value of α of the left - most node by accessing a lookup table of size q 4 ; determining the value of α of the second - left - most node by accessing a lookup table of size 2q q ; determining the value of α of the second - right - most node by accessing a lookup table of size 4q 4 ; and determining the value of α of the right - most node by accessing a lookup table of size 8q l,i . 4 ; and determining the value of α of the right - most node by accessing a lookup table of size 8q l,i . 4 ; and determining the value of α of the second - right - most node by accessing a lookup table of size 4q l,i . 4 ; and determining the value of α of the right - most node by accessing a lookup table of size 8q l,i .

[0013] According to an embodiment of the present disclosure, a method for error decoding an S - polarization code is provided, including: setting the length N = 2 nThe S-polar code is represented as a perfect binary tree with 2N-1 nodes, where for the l-th path in the list of L paths through the binary tree, 1 ≤ l ≤ L. The S-polar code is a generalized concatenated code (GCC) with Reed-Solomon (RS) codes as its outer codes and polar codes as its inner codes. Information is encoded into an N×J array using S-1 outer codes and S inner codes. The GCC is encoded in S stages, where in each stage s, new information bits and parity bits from the previous outer codes are encoded into C. (s) of Each codeword is stored as n rows of the array, wherein the encoded rows are mapped to a coset array, and the (s+1)th foreign code in the coset array is systematically mapped to the current codeword in the coset array. Each column is encoded, and the parity bits of the obtained codewords are sent to the next inner code for encoding; multiple frames are submitted to multiple row decoders, and the number of frames successfully decoded is counted, where a frame is decoded into C... (0) Multiple rows of the S-polar code array of the codeword; when the number of successfully decoded frames reaches K+2m, the C... (0) The codeword is subjected to Reed-Solomon (RS) decoding, where K is C. (0) The codeword dimension and m is the uncorrected number, while decoding multiple additional frames in the same stage; and wherein when the RS decoding is successful, the coset from the RS decoding is used to decode the upcoming multiple frames in the next stage of decoding, otherwise, RS decoding is repeated for the additional multiple frames.

[0014] According to another embodiment of this disclosure, each row of the S-polar code array is decoded into C... (0) The codewords include: providing the node v in the decoding path l at depth d in the perfect binary tree with the codewords from the parent node v. p The length of the soft information 2 d vector For each path in the list of paths in the binary tree, compute the left child node v of node v. l The length of the soft information 2 d-1 vector Provide node v with a hard decision of length 2 from the left child node. d-1 vector And use the vector together With the vector To create a length of 2 d-1 soft information vector and the vector Pass the result to the right child of node v; provide node v with the length 2 of the hard decision from its right child. d-1 vector And use the vector together With the vector To create a hard decision length of 2 d vector β v and the vector β v Pass it to its parent node; when v is the i-th leaf node of the perfect tree, 0 ≤ i < 2n, then, for each path in the list of paths, according to and To update two path metrics, where The path (l) through leaf node i represents the log-likelihood ratio of the codeword; L paths are selected from the 2L paths obtained by expanding the current L paths with 0 bits or 1 bit according to the lowest path metric; and if the l-th path is expanded with 0 bits, the vector is... Set to 0, otherwise, set the vector Set to 1.

[0015] According to another embodiment of this disclosure, the method includes, when v is a frozen leaf node, expanding all paths using 0 bits, and for each path index 1≤l≤L, dividing the vector... Set to 0, where freezing leaf nodes forces hard decisions to be zero.

[0016] According to another embodiment of this disclosure, the method includes updating L optimal path metrics (RATE-0 node) for nodes that are the roots of subtrees with only frozen leaf nodes, nodes that are the roots of subtrees with information leaf nodes (RATE-1 node), and nodes that are the roots of subtrees whose leaf nodes are all frozen leaf nodes, except for the rightmost leaf node (REP node), without visiting other nodes in the subtrees of the binary tree, wherein the L optimal path metrics compute corresponding hard decision vectors.

[0017] According to another embodiment of this disclosure, for RATE-0 nodes and REP nodes, the L best path metrics are updated in parallel for all paths in the list, wherein the latency of the path metric update depends on the depth of the node and not on the list size.

[0018] According to another embodiment of this disclosure, updating the L best path metrics includes, for a RATE-1 node at depth d, sequentially calculating m = min{L-1; 2} for the hard decision. n-d} bits, wherein the latency of the path metric update depends on the list size.

[0019] According to another embodiment of the present disclosure, the method includes: selecting t paths for those leaf nodes where the correct path is likely to be among the best t paths, where t < L; applying a CRC detector at the k-th leaf node; and continuing decoding until the number of paths equals one.

[0020] According to another embodiment of the present disclosure, determining those leaf nodes where the correct path is likely to be among the best t < L paths includes one or more of the following steps: selecting those paths whose path metrics are greater than a predetermined threshold, using machine learning to select the best t < L decoding paths, using a classifier to select the best t < L decoding paths, or using positive predictions for each path to select the best t < L decoding paths.

[0021] According to another embodiment of the present disclosure, different paths are processed in parallel, each path is associated with a memory storing 2N - 1 soft decision values, and each memory is assigned a unique processing block for performing soft computations along the decoding tree.

[0022] According to another embodiment of the present disclosure, each node in the decoding tree stores soft computations and hard decisions, where the hard decision is represented by one bit and the soft computation is represented by multiple bits. The method further includes: for a node at depth d, saving 2 n-d soft computations and 2 n-d hard decisions for each path in the list; and pruning paths in the decoding tree. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Illustrates the structure of a codeword of an N × J GCC with S stages.

[0024] Figure 2 Illustrates message passing of nodes in a binary tree according to an embodiment of the present disclosure.

[0025] Figure 3 Illustrates step-by-step SCL decoding in a pipeline according to an embodiment of the present disclosure.

[0026] Figure 4 Shows an example of a decoding tree of a polar code with a length of 16 and a dimension of 10 using step-by-step SCL decoding and step-by-step SSCL decoding according to an embodiment of the present disclosure, where the perfect tree is shown in Figure 4 (A) of, and the pruned tree for step-by-step SSCL decoding of this code is shown in Figure 4 (B) of.

[0027] Figure 5 Illustrates the throughput of an efficient chunk scheduler according to an embodiment of the present disclosure.

[0028] Figure 6 This is a block diagram of a system for implementing error correction of S-polar codes with reduced latency, according to embodiments of the present disclosure.

[0029] Figure 7 This is a flowchart of a method for Simplified Sequential Elimination List (SSCL) error decoding of S-polar codes according to embodiments of the present disclosure.

[0030] Figure 8 This is a simplified successive elimination list (SSCL) error decoding for S-polar codes with a small output alphabet, according to embodiments of the present disclosure.

[0031] Figure 9 This is a flowchart of a method for operating a latency-improving scheduler according to an embodiment of the present disclosure. Detailed Implementation

[0032] I. Introduction

[0033] Embodiments of this disclosure provide latency improvement techniques for S-polar codes, relying on stepped SCL decoding, early CRC detection, and a combination of stepped SCL decoding and simplified SCL decoding. When the channel output alphabet is small, memory size and latency are reduced by pre-computing all possible results of one of the first few levels in the tree and by using a lookup table. For GCC, embodiments provide a throughput-efficient scheduler implemented on frame chunks to utilize hardware replication of the line decoder.

[0034] GCC decoding is also performed in multiple stages. In the first stage, the rows of the noise array are decoded into C. (0) The codewords. These lines are called frames. Successfully decoded frames are mapped to a coset. If

[0035] With enough cosets, the first foreign code can be applied to all frames for the first coset. Decoding is performed bit by bit, which in turn allows for the use of code C. (1) For better correctability, the remaining two frames are decoded. This process continues until the outer code fails or all frames are successfully decoded by the inner code decoder and all cosets are successfully decoded by the outer code decoder.

[0036] The embodiments of this disclosure (1) apply CRC detection earlier and use a shorter list size (stepped SCL) where possible; (2) provide pipelined decoding for S-polar code frames for a given hardware resource such as memory and processing unit, which uses stepped SCL decoding to increase throughput; (3) combine (1) and (2) with simplified SCL decoding to further reduce latency, memory size and power consumption; (4) perform pre-computation stored on a lookup table if the channel output alphabet is small to save computation and memory on the massive first layer of the decoding tree used for SCL decoding; (5) provide a throughput-efficient scheduler for GCC that applies row and column decoding simultaneously and reduces latency by reducing the expected number of frames being decoded. If the row decoder is duplicated, the scheduler can be applied to blocks of frames.

[0037] To achieve high performance, polar codes in S-polarity are decoded using a Sequential Elimination List (SCL) decoder. The SCL decoder outputs a list of L codewords, each with a score indicating the probability that the codeword is correct. Performance is further improved by using CRC-assisted polar codes to detect correct codewords from the list. However, the SCL decoder has high latency. The latency of the SCL decoder can be reduced by using a simplified sequential elimination list SCL (SSCL). A simplified method for sequential elimination decoding is proposed, which is identical to the SCL with a list of size one. In this technique, the decoder tree of the list decoder is pruned, and a hard-decision process for the leaf nodes of the tree is defined, resulting in the same decisions as the SCL decoder, thus without performance loss. The decoder tree of the SCL decoder is N=2^N, with the list decoder sequentially traversed above. n The SSCL decoder is a perfect binary tree with leaf nodes, and its size determines the latency of the decoder. By pruning the tree, the SSCL has fewer operations that are executed sequentially, resulting in latency improvements.

[0038] For each node in the tree, the number of operations that can potentially be performed in parallel depends on the size of the list. A useful observation is that the list size does not have to be the same throughout the decoding process, and there are points where the list size L can be much smaller without affecting performance. Such a list decoder is called a step-SCL decoder. It can divide the leaf nodes of the tree into four groups of N=4 consecutive leaf nodes, and different list sizes are used for each group.

[0039] According to the embodiment, simulation is used to optimize the list size for each leaf node, minimizing performance loss. In the optimal series of list sizes, the list size is gradually increased until it reaches its maximum size. Furthermore, the CRC code for reducing L codewords in the list to one codeword can be applied early in the decoding process; therefore, at some point in the decoding process, the list size can be reduced to one and maintained until the end of decoding with minimal performance loss. According to the embodiment, combining stepped SCL, early CRC, and SSCL into a single decoding technique can provide latency improvements in practical situations with limited memory and processing units. This combined technique is described in Section II. Note that both the simplified SCL and stepped SCL methods, as well as early CRC, also save time complexity and memory.

[0040] The stepped SCL decoder according to the embodiment can also be S-polarized to decode many lines simultaneously, while sharing memory and processing units between different frames, thereby allowing for better use of available hardware. When the list size is small, more lines can be processed simultaneously using available resources. As the list size increases, more processing units are required per line, thus fewer lines can be processed until the list size drops back to one through early CRC detection. This sharing of resources among multiple lines will result in a further reduction in overall latency. This method will be described in Section II.

[0041] In an embodiment, if the noisy channel has a small output alphabet, it is possible to skip the processing and storage of the first few layers of the tree, which have the largest amount of data to store and the largest number of operations. While it is possible to perform operations on nodes in parallel, this would require more logic gates that may not exist in a real hardware implementation. To skip these layers, a lookup table is used that includes all possible results of the values ​​to be stored in the first layer. The number of layers thus stored depends on the size of the channel output alphabet, the length of the polar codes, and the size of the list.

[0042] Finally, in this embodiment, another throughput improvement for S-polar codes is achieved by selecting a more throughput-oriented scheduler. The scheduler for the S-polar decoder decides when to apply the outer code decoder and when to apply the inner code decoder. A naive scheduler would decode all rows, then apply the outer code decoder only for the next outer code, and repeat the process for the remaining rows that were not successfully decoded. The throughput-oriented scheduler can decode rows until the number of decoded rows is large enough for the next outer code decoder to succeed. It can also continue to apply the outer code decoder as it can, thus returning to the row decoder at a higher stage where the probability of decoding errors is lower. While this scheduling increases throughput, it can also potentially reduce performance because the outer code decoder is more likely to produce miss-corrected results. However, this performance penalty can be mitigated by increasing the number of corrected rows the scheduler needs before it invokes the outer code decoder. Additionally, the hardware architecture can implement a throughput-oriented scheduler where blocks of C rows are decoded simultaneously by the row decoders. This hardware architecture is described in Section IV.

[0043] II. Stepped SSCL for S-polarization decoders

[0044] This section describes the concepts of SSCL decoding and step SCL decoding separately, and then combines these two concepts into step SSCL decoding.

[0045] A.SSCL Decoding

[0046] According to the embodiment, the length N = 2 n SCL decoding of polar codes is based on soft and hard decision message passing through the nodes of a perfect binary tree with 2N-1 nodes. Since message passing is performed sequentially on the nodes of the tree, the decoder's latency increases with the size of the tree. When the decoder reaches a leaf node, it makes a hard decision on a single bit and then propagates that hard decision back to the parent node. If the list size is L, hard decision is performed by taking the L most likely paths out of the 2L paths obtained by expanding the current L paths with 0 or 1 bits. Some leaf nodes, called frozen leaf nodes, force the decoder's hard decision to be zero, so all paths in the list are expanded with 0 bits. SSCL decoding is based on the observation that some nodes in the tree have enough information available to make hard decisions efficiently on these nodes without traversing their subtrees. Currently, there are three types of nodes that can be handled in this way by SSCL.

[0047] (1) RATE-0 node: This node is the root of a subtree with only frozen leaf nodes, so the hard decision in this node must also be zero, and no other nodes in its subtree need to be visited.

[0048] (2) RATE-1 node: This node is the root of the subtree with only information leaf nodes, so hard decisions in this node can be obtained from soft decisions available in this node, and again, it is not necessary to visit other nodes in its subtree.

[0049] (3) REP node: This node is the root of the subtree whose leaf nodes are all frozen leaf nodes, except for the rightmost leaf node corresponding to the maximum index. For such a node, the hard decision can be all zeros or all ones, and both options are considered for each path without having to visit other nodes in the REP node subtree.

[0050] In addition to the three node types mentioned above, there is another type that can be used for successive elimination decoding, which is equivalent to an SCL with a list of size one.

[0051] (4) SPC node: This node is the root of the subtree of the information leaf node, except for the leftmost leaf node corresponding to the minimum index.

[0052] This method has no effect on the frame error rate (FER).

[0053] According to embodiments of this disclosure, in Figure 2 The diagram illustrates message passing between nodes in a tree. Figure 2 In the diagram, the central node v represents the current node, and node v l and v r These are the left and right child nodes of the current node, respectively, and p v It is the parent node of the current node.

[0054] Figure 7 This is a flowchart of a method for Simplified Sequential Elimination List (SSCL) error decoding of S-polar codes according to embodiments of the present disclosure. In step 71, the length N = 2... n After the S-polar code is represented as a perfect binary tree with 2N-1 nodes, for the l-th path in the list, 1≤l≤L, the node v of depth d receives information from its parent node v in step 72. p The length of the soft information 2 d vector In step 73, for each path in the list, node v calculates its left child node v l The length of the soft information 2 d-1 vector In step 74, node v receives a hard decision of length 2 from its left child node. d-1 vector And with Use it to create a length of 2 d-1 vector Then it is passed to its right child node. In step 75, v receives the length 2 of the hard decision from its right child node. d-1 vector And with Use it to create a hard decision length of 2 d vector β v Then pass it to its parent node. If in step 76, v is the i-th leaf node of the perfect tree, 0 ≤ i < 2N, then for each path in the list, according to and Update the two path metrics; and in step 77, select the L paths with the lowest path metrics from the 2L paths. Path metrics The path l through leaf node i is the log-likelihood ratio of the correct decoding path representing the codeword. In step 78, if the l-th path is extended by 0 bits, then... Set to 0. Otherwise, It is set to 1. If v is a frozen leaf node, all paths are expanded using 0 bits, and for each path index 1≤l≤L, it is... Set to 0.

[0055] For nodes of types RATE-0, RATE-1, and REP, L optimal path metrics can be updated, and the corresponding hard decision vector can be computed without visiting other nodes in the subtree. Note that for nodes of types RATE-0 and REP, path metric updates can be performed in parallel for all paths in the list, and the latency of path metric updates depends primarily on the node depth, not the list size. However, for RATE-1 nodes at depth d, the hard decision vector is computed sequentially as m = min{L-1; 2}. n-d} bits, therefore, the list size of this node type does indeed affect the latency of its path metric updates.

[0056] B. Stepped SCL Decoding

[0057] In an embodiment, recall that in SCL decoding of a list of size L, 2L path metrics are computed at each leaf node and L paths with the lowest path metrics are selected. The probability that the correct path is among the best t < L paths varies from leaf node to leaf node. At some leaf nodes, the correct path is likely to be among the best t paths, and thus reducing the list size to t < L may have a negligible impact on the FER. Additionally, since SCL is often applied to CRC-aided polar codes, only a portion of the information bits are CRC-encoded, which will allow the CRC detector to be applied at the k-th leaf node rather than at the end of decoding. Once the CRC detector is applied, decoding continues until the size of the path list is one, i.e., successive cancellation decoding is used. Note that for SC (Successive Cancellation) decoding, there are also nodes of type SPC.

[0058] Example 1. For a CRC-aided polar code of length 512 and dimension 480, by counting the positions of the correct paths in the list, it is found that almost the same FER of SCL decoding as that with a list of size 64 is obtained by taking the list size as 32 before the leaf node at index 256 and then increasing the list size to 64. Additionally, the CRC detector can be applied when reaching the leaf node at index 300, and SC decoding can be used on the remaining 212 leaf nodes without a significant reduction in FER.

[0059] According to an embodiment, in a hardware implementation of SCL decoding, different paths are processed in parallel. Each path requires its own memory for storing 2N - 1 soft decision values, and each memory is assigned a unique processing block for performing soft calculations along the decoding tree. The S polarization setting benefits from the fact that many frames have to be decoded, and by efficiently allocating memories in pipelined decoding, it can reduce the latency without a significant FER penalty. In the successive cancellation decoding mode, the latency reduction is due to the fact that most memories are released earlier, so decoding of a new frame in the pipeline can start while decoding of the previous frame is in progress. The following example illustrates the stepped SCL pipeline decoding in Example 1 when using 4 × 32 memories.

[0060] Example 2. The step-SCL decoding in Example 1 consists of three stages. The list size is 32 in stage 1; 64 in stage 2; and 1 in stage 3. Since stage 2 only extends from leaf node index 256 to leaf node index 300, it has the lowest latency. Assume the latency of stage 2 is x cycles and the latency of stage 1 is 2x cycles. Also assume a total of 4×32 memory is available. Decoding of the first frame begins in stage 1, and decoding of the second frame begins in stage 1 after x cycles, using 2×32 memory for both frames. After 2x cycles, another 32 memory is used to decode the first frame in stage 2, and another 32 memory is used to decode the third frame in stage 1. When decoding of the first frame in stage 2 is complete, the 2×32 memory is released and can be used to decode the second frame in stage 2 and the new frame in stage 1. Simultaneously, a separate memory can be used to decode the first frame in stage 3. In this way, the decoding of stage 2 is completed sequentially, frame by frame, with a delay of approximately x cycles per frame. Figure 3 The illustration shows a step-by-step SCL decoding process in a pipeline according to an embodiment of the present disclosure. Stages 1, 2, and 3 are depicted using medium gray rectangles, dark gray rectangles, and light gray rectangles, respectively. The latency per frame is approximately x cycles, where x is the latency of stage 2, depicted as a dark gray rectangle.

[0061] Alternatively, in an embodiment, it is possible to divide the memory into 4×32 segments between two frames and to apply stages 1 and 2 simultaneously on both frames. In this case, the latency of each frame will be the average of the latencies of stages 1 and 2, which is 1.5x cycles.

[0062] C. Step-by-step SSCL decoding

[0063] Section II-A reviews SSCL decoding and describes how it reduces latency by pruning the decoding tree. Section II-B suggests that stepped SCL decoding with early CRC detection can reduce decoding latency when decoding frames in a pipeline for a given amount of memory, as the memory is freed earlier and becomes available for new frames. This section will describe the effects of embodiments of this disclosure that combine the two concepts of stepped SCL decoding and simplified SCL decoding.

[0064] Since the latency of step-SCL decoding in a pipeline is determined by the stage latency in decoding with the largest list size, simplifying SCL decoding can reduce latency by reducing the latency of this stage. For other stages, it reduces memory size, which allows for hardware replication and reduces latency. Combinatorial decoding also saves power.

[0065] To understand the efficiency of the combinatorial concept, examine the decoding tree and the memory size required at each node. Each node in the decoding tree stores both soft computation and hard decision. While a hard decision is represented by only one bit, a soft computation is represented by many bits. If the node is at depth d, then 2 bits are stored for each path in the list. n-d One soft computing and 2 n-d A hard decision. In step-SCL decoding, the list size on a given node may differ for soft computation and hard decision because the former is used when traversing down from the parent node to its child nodes, while the latter is used later when traversing up from the child nodes to their parent nodes.

[0066] exist Figure 4 An example of a decoding tree using a 16-length polar code with 10 dimensions and step SCL decoding and step SSCL decoding, according to an embodiment of the present disclosure, is shown. A perfect tree is shown in... Figure 4 In (A), white leaf nodes are frozen leaf nodes, while black leaf nodes are information leaf nodes. The list size for each leaf node is written below the leaf node, and early CRC detection occurs in the 10th leaf node, thus reducing the list size to one.

[0067] exist Figure 4(B) shows the pruned tree for step SSCL decoding for this code. The number assigned to each directed edge is the list size when traversing the tree along that edge. The list size for soft computation at the root of the tree (level 0) is one, while the list size for its hard decisions is 8. Note that once the CRC detector is applied, the list size is one, so SPC-type nodes can also be used. In the first level from left: the first node has a list size of one for soft computation and a list size of 8 for hard decisions, while the second node consumes much more memory, with a list size of 8 for soft computation and a list size of one for hard decisions. Note that when traversing from a node to its right child, the memory for soft computation is no longer needed and can be freed. Similarly, when traversing from a node to its parent node, the hard decisions of that node are no longer needed. For example, the left child of the root has a list size of one for soft computation. This means that when decoding reaches the right child of the root, it uses memory for an additional 7 soft computation vectors. In the second level from the left: the first and last nodes are leaf nodes, so only the path metric needs to be updated at these nodes, which doesn't use a lot of memory because it's one value per list. The second node has a list of size 2 for soft computation and a list of size 8 for hard decision, while the third node has a list of size 8 for soft computation and a list of size 1 for hard decision. Again, when reaching the third node in the second level, memory is added for an additional 6 soft computation vectors. All nodes in the last level are leaf nodes and require no additional memory other than the relatively small amount used for path metrics. Therefore, by combining the step SCL with SSCL decoding, only two nodes in the pruned tree use the maximum list size for their soft computation.

[0068] Another interesting observation is that in the final stage of decoding, when the list size is one, nodes of type SPC can be considered, thus allowing for further pruning of the tree at this stage, thereby saving latency, power, and memory. Figure 4 The pruning tree in (B) has SPC nodes.

[0069] III. Skip the first level of the decoder tree in channels with small output alphabets.

[0070] This section describes a method according to an embodiment that saves memory and soft computation in the first layer of the decoding tree used for SCL decoding when the channel output alphabet is small and the code length and list size are large. In the embodiments, the method described herein is also applicable to stepped SCL decoding and simplified SCL decoding.

[0071] Let q be the number of channel outputs, and N = 2. n L is the length of the polar code, and L is the size of the list. Figure 8is a simplified successive cancellation list (SSCL) error decoding of an S-polar code for a channel with a small output alphabet according to an embodiment. At the start of decoding, assuming that the S-polar code has been represented as a perfect binary tree in step 81, the decoder receives in step 82 a vector of length 2 n of log-likelihood ratios (LLRs), and each entry of the vector can take one of q possible values. The soft calculation in the left child node v l of the root is to take a vector α 2 of length 2 n-1 whose values are from a set of size q l . Instead of calculating these values, for 0 ≤ i < 2 n-1 , it is sufficient to know the outputs of the channels in coordinates 2i and 2i + 1, and a lookup table of size q 2 can be used to directly access the values of α l,i . Similarly, the soft calculation in the right child node vr of the root is a vector α 2 of length 2 n-1 whose entries take values from a set of size 2q r , because α r,i also depends on the hard decision bit β l,i . A lookup table of size 2q 2 is used to look up the values of α r,i . Thus, to completely skip the soft calculations of the first layer and save the memory of the zero layer, 3 lookup tables of size q 2 are used and the channel outputs can be represented by N log2q bits. If in step 83, 3q 2 f + N log2 q << Nf, where f is the number of bits representing the soft calculation values, then this technique saves both memory and computation. Then, in step 84, the values of α 2 are determined by accessing a lookup table of size q l,i , and the values of α 2 are determined by accessing a lookup table of size 2q r,i .

[0072] This idea can be applied to the second layer, where there are q 4 possible values for the soft calculation in the first node from the left, 2q 4 possible values for the second node from the left, 4q 4 possible values for the third node, and 8q 4 possible values for the last node of this layer. Thus, a lookup table of size (1 + 2 + 4 + 8)q 4 = 15q 4The table can completely save the first layer and can directly perform all soft calculations of the second layer for each path in the list based on the lookup table of the second layer, the channel output vector, and the hard decision. If in step 85, 15q 4 +N log q 2<<f N(L / 2+1), the memory can be saved, the calculation of the first layer can be completely skipped, and the lookup table can be used to update the soft calculation of the second layer. Then, in step 86, by accessing the lookup table of size q 4 to determine the α l,i value of the leftmost node; by accessing the lookup table of size 2q 4 to determine the α l,i value of the second leftmost node; by accessing the lookup table of size 4q 4 to determine the α l,i value of the second rightmost node; and by accessing the lookup table of size 8q 4 to determine the α l,i value of the rightmost node.

[0073] Example 3. Assume q = 2, n = 9, L = 16, and f = 7. 2 9 bits are needed to represent the channel output vector instead of 7×512 = 3584 bits. To directly use the lookup table to update the nodes in the second layer, 15×2 4 ×7 = 1680 bits are needed, and the memory of the first layer is saved, which is 7×16×2 8 = 28,672 bits. Overall, 30,064 bits are saved. Since the total required memory size is 512×16×7 + 512 = 60,928, about half of the memory is saved and the latency is reduced in this example.

[0074] IV. Latency Improvement Scheduler

[0075] According to the embodiment, when decoding a GCC with an RS code as its outer code, for an S polar code, there is a degree of freedom in determining the number of frames to be decoded in a certain stage before attempting to use an RS decoder to decode the cosets of that stage. The block of the decoder that determines which frames to decode and when to call the RS decoder is called a scheduler. This section describes an efficient scheduler according to the embodiment and also describes its architecture.

[0076] The naive scheduler decodes all frames that have not yet been successfully decoded at each stage. In this method, the RS decoder must wait until the line decoder has finished. The method according to the embodiment decodes only a sufficient number of frames for the RS decoder, which is likely to succeed. In the method according to the embodiment, the RS decoder and line decoder can work simultaneously, which increases throughput. Furthermore, many frames are decoded in later stages, which has a greater probability of success; therefore, on average, the method according to the embodiment reduces the expected number of times the line decoder is being used, which increases throughput.

[0077] To determine how many successful frames are needed for the RS decoder to have a good success probability, the fact that the RS code is a maximum separable distance (MDS) code is used. Therefore, if J is the length of the RS code and K is its dimension, successful decoding is guaranteed at most JK if the number of erased frames (e.g., frames that have not yet been decoded or failed to be decoded) plus twice the number of uncorrected frames. This can be written as n e +2n mc ≤JK, where n e It is the number of erased frames and n mc This represents the number of uncorrected frames. If the probability of having more than m uncorrected frames is negligible, then having K+2m decoded frames will be sufficiently significant. This is because there will be n e =JK-2m and n mc ≤m, therefore n is required. e +2n mc ≤JK-2m+2m=JK. The quantity m can be determined using the probability of failure and uncorrection at each stage of the line decoder and the expected total failure probability.

[0078] According to the hardware implementation of the embodiment, the throughput-efficient scheduler can operate on a group of C frames that are symmetrically grouped. Figure 9 This is a flowchart of a method for operating a latency-improving scheduler according to an embodiment of the present disclosure. Assuming the S-polar code has been represented as a perfect binary tree in step 91, the scheduler submits C frames to multiple line decoders in step 92 and counts the number of decoded frames (e.g., frames successfully decoded). The line decoders decode the frames as described above. Once this number reaches K+2m, RS decoding at this stage begins in step 93, while frames for more blocks are decoded in the same stage. If the RS decoder succeeds in step 94, the coset from the RS decoder is used in step 95 to decode the upcoming block in the next stage of decoding. Otherwise, in step 96, RS decoding is repeated for more frames because frames for new blocks are being decoded at this time.

[0079] Figure 5The diagram illustrates the throughput of an efficient chunk scheduler according to an embodiment of the present disclosure. Figure 5 In this diagram, RSD refers to the Reed-Solomon decoder. At ①, decoding of the i-th block begins in stage 0. At ②, decoding of the i-th block ends in stage 0 and decoding of the (i+1)-th block begins in stage 0. There are enough decoded frames for the RS decoder to begin in stage 1. At ③, the RS decoder has succeeded and the (i+2)-th block is decoded in stage 1. At ④, decoding of the (i+2)-th block ends in stage 1, but there are not enough decoded frames to apply to the RS decoder in stage 2. Additionally, decoding of the (i+3)-th frame begins in stage 1. At ⑤, decoding of the (i+3)-th frame ends in stage 1 and decoding of the (i+4)-th frame begins in stage 1. There are enough decoded frames, and the RS decoder begins in stage 2.

[0080] System Implementation Method

[0081] It should be understood that embodiments of this disclosure can be implemented in various forms of hardware, software, firmware, dedicated processes, or combinations thereof. In one embodiment, this disclosure can be implemented in hardware as an application-specific integrated circuit (ASIC) or as a field-programmable gate array (FPGA). In another embodiment, this disclosure can be implemented in software as an application tangibly embodied on a computer-readable program storage device. The application can be uploaded to and executed by a machine including any suitable architecture.

[0082] Figure 6 This is a block diagram of a system for implementing error correction of S-polar codes with shortened latency, according to embodiments of the present disclosure. Reference is now made to... Figure 6 The computer system 61 used to implement this disclosure can in particular include a central processing unit (CPU) or controller 62, a memory 63, and an input / output (I / O) interface 64. The computer system 61 is typically coupled to a display 65 and various input devices 36, such as a mouse and keyboard, via the I / O interface 64. Supporting circuitry can include circuitry such as cache, power supply, clock circuitry, and communication buses. The memory 63 can include random access memory (RAM), read-only memory (ROM), a disk drive, a tape drive, or combinations thereof. This disclosure can be implemented as routines 67 stored in the memory 63 and executed by the CPU or controller 62 to process signals from a signal source 68. Therefore, the computer system 61 is a general-purpose computer system that becomes a dedicated computer system when executing the routines 67 of this disclosure. Alternatively, as described above, embodiments of this disclosure can be implemented as an ASIC or FPGA 67 that communicates signalally with the CPU or controller 62 to process signals from a signal source 68.

[0083] Computer system 61 also includes an operating system and microinstruction code. The various processes and functions described herein may be part of the microinstruction code or part of an application program (or a combination thereof) executed via the operating system. Additionally, various other peripheral devices, such as additional data storage devices and printing devices, can be connected to the computer platform.

[0084] It should be further understood that, because some of the system components and method steps depicted in the accompanying drawings can be implemented in software, the actual connections between system components (or process steps) can vary depending on how this disclosure is programmed. Given the teachings of this disclosure provided herein, those skilled in the art will be able to conceive of these and similar implementations or configurations of this disclosure.

[0085] Although this disclosure has been described in detail with reference to exemplary embodiments, those skilled in the art will appreciate that various modifications and substitutions can be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A method for SSCL error decoding of an S polar code, where SSCL is Simplified Successive Cancellation List, and the method includes: With length N = 2 n The S-polar code is represented as a perfect binary tree with 2N - 1 nodes, where n is a non-negative integer, and for each of the L paths in the list traversing the perfect binary tree, the nth node is the first node. l 1 ≤ l ≤ L, where the S polar code is a GCC with the RS code as its outer code and the polar code as its inner code, where RS is the Reed-Solomon code and GCC is the generalized concatenated code, where S - 1 outer codes and S inner codes are used to encode information into an N × J array, where S and J are non-negative integers, where the GCC is encoded in S stages, where in each stage s, new information bits and parity bits from the previous outer codes are encoded into C (s) of Each codeword is stored as A rows of the array, where C (s) It is in the stage s The code words, among which It is in the stage s The amount of data in the foreign codeword It is in the stage s The data volume in the +1 foreign codeword, where the encoded lines are mapped to a coset array, in which the current coset array is systematically processed at stage s+1. Each column is encoded, and the parity check bit of the obtained codeword is sent to the next internal code for encoding; Give the decoding path at depth d in the perfect binary tree l Node v in the middle provides information from its parent node. v p Length 2 d soft information vector ; For each path in the list of paths in the perfect binary tree, compute the left child node of node v. v l Length 2 d-1 soft information vector ; Provide node v with a length of 2 from the left child node. d-1 Hard decision vector And use the vector together and the vector To create a length of 2 d-1 soft information vector and the vector Passed to the right child node of node v; Provide node v with a length of 2 from its right child. d-1 Hard decision vector And use the vector together and the vector To create a length of 2 d The hard decision vector β v and the vector β v Pass it to its parent node; When v is the i-th leaf node of the perfect binary tree, 0 ≤ i < 2B, then, for each path in the list of paths, according to and To update two path metrics, where the path metric is... Through leaf nodes i Path 2 l It is the log-likelihood ratio representing the correct decoding path of a codeword; a path metric. Through leaf nodes i - 1 path l It represents the log-likelihood ratio of the correct decoding path for the codeword, and the path metric. Through leaf nodes i Path 2 l +1 represents the log-likelihood ratio of the correct decoding path for the codeword; select L paths with the lowest path metrics from the 2L paths obtained by extending the current L paths with 0 bits or 1 bit; and If the first bit is extended by 0 bits l If there is a path, then the vector will be... Set to 0, otherwise, set the vector Set to 1, where It comes from the parent node. v p Length 2 d The hard decision vector.

2. The method of claim 1, further comprising, when the node v is a frozen leaf node, expanding all paths using 0 bits, and for each path index 1 ≤ l ≤ L, the vector Set to 0, where freezing leaf nodes forces hard decisions to be zero.

3. The method according to claim 2, further including, for a node that is the root of a subtree having only frozen leaf nodes, i.e., a RATE-0 node, for a node that is the root of a subtree having information leaf nodes, i.e., a RATE-1 node, and for a node that is the root of a subtree whose leaf nodes except the rightmost leaf node are all frozen leaf nodes, i.e., a REP node, updating the L best path metrics and calculating the corresponding hard decision vectors without accessing other nodes in the subtree of the perfect binary tree.

4. The method according to claim 3, wherein for RATE-0 nodes and REP nodes, updating the L best path metrics is performed in parallel for all paths in the list, and the latency of the update depends on the depth of the node rather than the list size.

5. The method according to claim 3, wherein, Updating the L optimal path metrics involves, for a RATE-1 node at depth d, sequentially calculating the hard decision m = min{ L-1; 2 n-d } bits, wherein the latency of the update depends on the list size.

6. The method according to claim 1, further including: Selecting t paths for those leaf nodes where the correct path is likely to be among the best t paths, where t < L; Applying a CRC detector at the k-th leaf node; and Continuing the decoding until the number of paths equals one.

7. The method according to claim 6, wherein, Determining those leaf nodes where the correct path is likely to be among the best t < L paths includes one or more of the following operations: selecting those paths whose path metrics are greater than a predetermined threshold, using machine learning to select the best t < L decoding paths, using a classifier to select the best t < L decoding paths, or using positive predictions for each path to select the best t < L decoding paths.

8. The method according to claim 6, wherein different paths are processed in parallel, each path is associated with a memory storing 2N - 1 soft decision values, and each memory is assigned a unique processing block for performing soft information processing along the decoding tree.

9. The method according to claim 6, wherein each node in the decoding tree stores soft information and a hard decision, where the hard decision is represented by one bit and the soft information is represented by multiple bits, and the method further includes For a node at depth d, save the 2^d values ​​of each path in the list. n-d One soft message and 2 n-d A firm ruling; and Pruning the paths in the decoding tree.

10. A method for error decoding an S polar code, the method includes: With length N = 2 n The S-polar code is represented as a perfect binary tree with 2N - 1 nodes, where for the L paths in the list of the perfect binary tree, the first... l 1 ≤ l ≤ L, where the S polar code is a GCC with the RS code as its outer code and the polar code as its inner code, where RS is the Reed-Solomon code and GCC is the generalized concatenated code, where S-1 outer codes and S inner codes are used to encode information into an N × J array, where the GCC is encoded in S stages, and in each stage s, new information bits and parity bits from the previous outer codes are encoded into C (s) of Each codeword is stored as A rows of the array, where C (s) It is in the stage s The code words, among which It is in the stage s The amount of data in the foreign codeword It is in the stage s The data volume in the +1 foreign codeword, where the encoded lines are mapped to a coset array, in which the current coset array is systematically processed at stage s+1. Each column is encoded, and the parity bits of the codewords obtained therein are sent to the next internal code for encoding; Multiple frames are submitted to multiple line decoders, and the number of frames successfully decoded is counted, where a frame is decoded into C... (0) Multiple rows of the S-polar code array of the codeword; When the number of successfully decoded frames reaches K + 2m, the C... (0) The codeword is decoded using RS, where RS stands for Reed-Solomon, and K is C. (0) The dimension of the codewords and m is the uncorrected number, while decoding multiple other frames in the same stage; and Wherein, when the RS decoding is successful, using the cosets from the RS decoding to decode multiple upcoming frames in the next stage of decoding, Otherwise, repeating the RS decoding for another multiple frames.

11. The method according to claim 10, wherein, Decode each row of the S polar code array into C. (0) The code words include: From the parent node v p Decoding path at depth d in the perfect binary tree l The node v in the middle provides a length of 2 d soft information vector ; For each path in the list of paths in the perfect binary tree, compute the left child node of node v. v l Length 2 d-1 soft information vector ; Provide a length of 2 from the left child node to node v. d-1 Hard decision vector and use the vector together and the vector To create a length of 2 d-1 soft information vector and the vector Passed to the right child node of node v; Provide a length of 2 from the right child of node v to node v. d-1 Hard decision vector and use the vector together and the vector To create a length of 2 d The hard decision vector β v and the vector β v Passed to the parent node of node v; When v is the i-th leaf node of the perfect binary tree, 0 ≤ i < 2B, then, for each path in the list of paths, according to and To update two path metrics, where the path metric is... Through leaf nodes i Path 2 l It is the log-likelihood ratio representing the correct decoding path of a codeword; a path metric. Through leaf nodes i - 1 path l It represents the log-likelihood ratio of the correct decoding path for the codeword, and the path metric. Through leaf nodes i Path 2 l +1 represents the log-likelihood ratio of the correct decoding path for the codeword; select L paths with the lowest path metrics from the 2L paths obtained by extending the current L paths with 0 bits or 1 bit; and If the first bit is extended by 0 bits l If there is a path, then the vector will be... Set to 0, otherwise, set the vector Set to 1, where It comes from the parent node. v p Length 2 d The hard decision vector.

12. The method of claim 11, further comprising, when v is a frozen leaf node, expanding all paths using 0 bits, and for each path index 1 ≤ l ≤ L, the vector Set to 0, where freezing leaf nodes forces hard decisions to be zero.

13. The method according to claim 12, further comprising, for a node that is the root of a subtree having only frozen leaf nodes, i.e., a RATE-0 node, for a node that is the root of a subtree having informative leaf nodes, i.e., a RATE-1 node, and for a node that is the root of a subtree in which all but the rightmost leaf nodes are frozen leaf nodes, i.e., a REP node, updating the L best path metrics and calculating the corresponding hard decision vectors without accessing other nodes in the subtree of the perfect binary tree.

14. The method according to claim 13, wherein for RATE-0 nodes and REP nodes, the update of the L best path metrics is performed in parallel for all paths in the list, and the latency of the update depends on the depth of the node and not on the list size.

15. The method of claim 13, wherein updating the L best path metrics comprises, for a RATE-1 node of depth d, sequentially calculating m = min{L-1; 2} for the hard decision. n-d } bits, wherein the latency of the update depends on the list size.

16. The method according to claim 11, further comprising: selecting t paths for those leaf nodes where the correct path is likely to be among the best t paths, where t < L; applying a CRC detector at the k-th leaf node; and continuing decoding until the number of paths equals one.

17. The method according to claim 16, wherein determining those leaf nodes where the correct path is likely to be among the best t < L paths includes one or more of the following operations: selecting those paths whose path metrics are greater than a predetermined threshold, using machine learning to select the best t < L decoding paths, using a classifier to select the best t < L decoding paths, or using a positive prediction for each path to select the best t < L decoding paths.

18. The method according to claim 16, wherein different paths are processed in parallel, each path is associated with a memory storing 2N - 1 soft decision values, and each memory is assigned a unique processing block for performing the processing of soft information along the decoding tree.

19. The method according to claim 16, wherein each node in the decoding tree stores soft information and a hard decision, the hard decision is represented by one bit, the soft information is represented by multiple bits, and the method further comprises For a node at depth d, save the 2^d values ​​of each path in the list. n-d One soft message and 2 n-d A firm ruling; and pruning the paths in the decoding tree.

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